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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 21:30:09 11/08/2009
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-- Create Date: 21:30:09 11/08/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: bus_register_x16 - Behavioral
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-- Module Name: bus_register_x16 - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity bus_register_x16 is
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entity bus_register_x16 is
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Port ( clk : in STD_LOGIC;
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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re : in STD_LOGIC;
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re : in STD_LOGIC;
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we : in STD_LOGIC;
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we : in STD_LOGIC;
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dataIn : in STD_LOGIC_VECTOR (15 downto 0);
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dataIn : in STD_LOGIC_VECTOR (15 downto 0);
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dataOut : out STD_LOGIC_VECTOR (15 downto 0));
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dataOut : out STD_LOGIC_VECTOR (15 downto 0));
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end bus_register_x16;
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end bus_register_x16;
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architecture Behavioral of bus_register_x16 is
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architecture Behavioral of bus_register_x16 is
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signal data: std_logic_vector(15 downto 0);
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signal data: std_logic_vector(15 downto 0);
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component bus_access_x16
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Port ( en : in STD_LOGIC;
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dataRead : in STD_LOGIC_VECTOR (15 downto 0);
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dataWrite : out STD_LOGIC_VECTOR (15 downto 0));
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end component;
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begin
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begin
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ba: bus_access_x16
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tristate: process(we, data) is
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port map( en => we,
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begin
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dataRead=>data,
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if we = '1' then
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dataWrite=>dataOut);
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dataOut <= data;
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else
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dataOut <= (others=>'Z');
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end if;
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end process;
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readData: process(clk) is
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readData: process(clk) is
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if re = '1' then
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if re = '1' then
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data <= dataIn;
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data <= dataIn;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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