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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:33:01 2011
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//-- Invoked Fri Mar 25 23:33:01 2011
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//--
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//--
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//-- Source file: dma_ch_outs.v
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//-- Source file: dma_ch_outs.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_ahb64_core0_ch_outs(clk,reset,cmd,clr,outs_max,outs,outs_empty,stall,timeout);
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module dma_ahb64_core0_ch_outs(clk,reset,cmd,clr,outs_max,outs,outs_empty,stall,timeout);
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input clk;
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input clk;
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input reset;
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input reset;
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input cmd;
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input cmd;
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input clr;
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input clr;
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input [`OUT_BITS-1:0] outs_max;
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input [`OUT_BITS-1:0] outs_max;
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output [`OUT_BITS-1:0] outs;
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output [`OUT_BITS-1:0] outs;
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output outs_empty;
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output outs_empty;
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output stall;
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output stall;
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output timeout;
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output timeout;
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reg [`OUT_BITS-1:0] outs;
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reg [`OUT_BITS-1:0] outs;
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wire [`OUT_BITS-1:0] outs_pre;
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wire [`OUT_BITS-1:0] outs_pre;
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reg stall;
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reg stall;
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reg [`TIMEOUT_BITS-1:0] counter;
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reg [`TIMEOUT_BITS-1:0] counter;
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assign outs_empty = outs == 'd0;
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assign outs_empty = outs == 'd0;
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assign outs_pre = outs + cmd - clr;
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assign outs_pre = outs + cmd - clr;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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outs <= #1 'd0;
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outs <= #1 'd0;
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else if (cmd | clr)
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else if (cmd | clr)
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outs <= #1 outs_pre;
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outs <= #1 outs_pre;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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stall <= #1 1'b0;
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stall <= #1 1'b0;
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else if (|outs_max)
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else if (|outs_max)
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stall <= #1 outs >= outs_max;
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stall <= #1 outs >= outs_max;
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assign timeout = (counter == 'd0);
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assign timeout = (counter == 'd0);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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counter <= #1 {`TIMEOUT_BITS{1'b1}};
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counter <= #1 {`TIMEOUT_BITS{1'b1}};
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else if (clr)
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else if (clr)
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counter <= #1 {`TIMEOUT_BITS{1'b1}};
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counter <= #1 {`TIMEOUT_BITS{1'b1}};
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else if (|outs)
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else if (|outs)
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counter <= #1 counter - 1'b1;
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counter <= #1 counter - 1'b1;
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endmodule
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endmodule
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