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-------------------------------------------------------------------------------
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-- Politecnico di Torino
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-- Politecnico di Torino
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-- Dipartimento di Automatica e Informatica
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-- Dipartimento di Automatica e Informatica
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : EPC Class1 Gen2 RFID Tag - Inventoried and Selected Flags Controller
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-- Title : EPC Class1 Gen2 RFID Tag - Inventoried and Selected Flags Controller
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--
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--
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-- File name : InvSelFlagsCtrl.vhd
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-- File name : InvSelFlagsCtrl.vhd
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--
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--
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-- Description : Inventoried and Selected flag controller. It provides a
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-- Description : Inventoried and Selected flag controller. It provides a
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-- suitable interface with the flag model and deals with
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-- suitable interface with the flag model and deals with
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-- refreshing procedures.
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-- refreshing procedures.
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--
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--
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-- Authors : Erwing R. Sanchez <erwing.sanchezsanchez@polito.it>
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-- Authors : Erwing R. Sanchez <erwing.sanchez@polito.it>
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--
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-- Rev. History : 29 June 06
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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entity InvSelFlagCtrl is
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entity InvSelFlagCtrl is
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generic (
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generic (
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REFRESHING_CLK_CYC : integer := 255); -- Number of clock cycles to refresh flags
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REFRESHING_CLK_CYC : integer := 255); -- Number of clock cycles to refresh flags
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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S0in : in std_logic;
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S0in : in std_logic;
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S1in : in std_logic;
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S1in : in std_logic;
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S2in : in std_logic;
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S2in : in std_logic;
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S3in : in std_logic;
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S3in : in std_logic;
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SLin : in std_logic;
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SLin : in std_logic;
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S0en : in std_logic;
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S0en : in std_logic;
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S1en : in std_logic;
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S1en : in std_logic;
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S2en : in std_logic;
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S2en : in std_logic;
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S3en : in std_logic;
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S3en : in std_logic;
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SLen : in std_logic;
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SLen : in std_logic;
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S0out : out std_logic;
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S0out : out std_logic;
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S1out : out std_logic;
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S1out : out std_logic;
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S2out : out std_logic;
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S2out : out std_logic;
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S3out : out std_logic;
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S3out : out std_logic;
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SLout : out std_logic);
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SLout : out std_logic);
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end InvSelFlagCtrl;
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end InvSelFlagCtrl;
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architecture FlagController1 of InvSelFlagCtrl is
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architecture FlagController1 of InvSelFlagCtrl is
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component InvSelFlag
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component InvSelFlag
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port (
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port (
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S1i : in std_logic;
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S1i : in std_logic;
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S2i : in std_logic;
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S2i : in std_logic;
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S3i : in std_logic;
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S3i : in std_logic;
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SLi : in std_logic;
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SLi : in std_logic;
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S1o : out std_logic;
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S1o : out std_logic;
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S2o : out std_logic;
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S2o : out std_logic;
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S3o : out std_logic;
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S3o : out std_logic;
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SLo : out std_logic);
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SLo : out std_logic);
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end component;
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end component;
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-- synopsys synthesis_off
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-- synopsys synthesis_off
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signal S0out_i, S1out_i, S2out_i, S3out_i, SLout_i : std_logic;
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signal S0out_i, S1out_i, S2out_i, S3out_i, SLout_i : std_logic;
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signal S1i, S2i, S3i, SLi : std_logic;
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signal S1i, S2i, S3i, SLi : std_logic;
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signal S1o, S2o, S3o, SLo : std_logic;
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signal S1o, S2o, S3o, SLo : std_logic;
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signal RefCnt : integer;
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signal RefCnt : integer;
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-- synopsys synthesis_on
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-- synopsys synthesis_on
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begin -- FlagController1
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begin -- FlagController1
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-- synopsys synthesis_off
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-- synopsys synthesis_off
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-- OUTPUT WIRES
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-- OUTPUT WIRES
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S0out <= S0out_i;
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S0out <= S0out_i;
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S1out <= S1out_i;
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S1out <= S1out_i;
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S2out <= S2out_i;
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S2out <= S2out_i;
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S3out <= S3out_i;
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S3out <= S3out_i;
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SLout <= SLout_i;
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SLout <= SLout_i;
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REGISTERS : process (clk, rst_n)
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REGISTERS : process (clk, rst_n)
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begin -- process REGISTERS
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begin -- process REGISTERS
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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S0out_i <= '0';
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S0out_i <= '0';
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S1out_i <= '0';
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S1out_i <= '0';
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S2out_i <= '0';
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S2out_i <= '0';
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S3out_i <= '0';
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S3out_i <= '0';
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SLout_i <= '0';
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SLout_i <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if S0en = '1' then
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if S0en = '1' then
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S0out_i <= S0in;
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S0out_i <= S0in;
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else
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else
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S0out_i <= S0out_i;
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S0out_i <= S0out_i;
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end if;
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end if;
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-- Flag Model Input Registers
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-- Flag Model Input Registers
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--S1
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--S1
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if S1en = '1' then
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if S1en = '1' then
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S1i <= S1in;
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S1i <= S1in;
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elsif RefCnt = REFRESHING_CLK_CYC then
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elsif RefCnt = REFRESHING_CLK_CYC then
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S1i <= S1out_i;
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S1i <= S1out_i;
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else
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else
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S1i <= 'Z';
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S1i <= 'Z';
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end if;
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end if;
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--S2
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--S2
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if S2en = '1' then
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if S2en = '1' then
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S2i <= S2in;
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S2i <= S2in;
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elsif RefCnt = REFRESHING_CLK_CYC then
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elsif RefCnt = REFRESHING_CLK_CYC then
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S2i <= S2out_i;
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S2i <= S2out_i;
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else
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else
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S2i <= 'Z';
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S2i <= 'Z';
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end if;
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end if;
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--S3
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--S3
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if S3en = '1' then
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if S3en = '1' then
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S3i <= S3in;
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S3i <= S3in;
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elsif RefCnt = REFRESHING_CLK_CYC then
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elsif RefCnt = REFRESHING_CLK_CYC then
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S3i <= S3out_i;
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S3i <= S3out_i;
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else
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else
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S3i <= 'Z';
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S3i <= 'Z';
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end if;
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end if;
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--SL
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--SL
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if SLen = '1' then
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if SLen = '1' then
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SLi <= SLin;
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SLi <= SLin;
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elsif RefCnt = REFRESHING_CLK_CYC then
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elsif RefCnt = REFRESHING_CLK_CYC then
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SLi <= SLout_i;
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SLi <= SLout_i;
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else
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else
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SLi <= 'Z';
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SLi <= 'Z';
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end if;
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end if;
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-- Flag Model Output Registers
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-- Flag Model Output Registers
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S1out_i <= S1o;
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S1out_i <= S1o;
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S2out_i <= S2o;
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S2out_i <= S2o;
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S3out_i <= S3o;
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S3out_i <= S3o;
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SLout_i <= SLo;
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SLout_i <= SLo;
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end if;
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end if;
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end process REGISTERS;
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end process REGISTERS;
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REF_COUNTER : process (clk, rst_n)
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REF_COUNTER : process (clk, rst_n)
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begin -- process REF_COUNTER
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begin -- process REF_COUNTER
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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RefCnt <= 0;
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RefCnt <= 0;
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if RefCnt = REFRESHING_CLK_CYC then
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if RefCnt = REFRESHING_CLK_CYC then
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RefCnt <= 0;
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RefCnt <= 0;
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else
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else
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RefCnt <= RefCnt + 1;
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RefCnt <= RefCnt + 1;
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end if;
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end if;
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end if;
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end if;
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end process REF_COUNTER;
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end process REF_COUNTER;
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InvSelFlag_i : InvSelFlag
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InvSelFlag_i : InvSelFlag
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port map (
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port map (
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S1i => S1i,
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S1i => S1i,
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S2i => S2i,
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S2i => S2i,
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S3i => S3i,
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S3i => S3i,
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SLi => SLi,
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SLi => SLi,
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S1o => S1o,
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S1o => S1o,
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S2o => S2o,
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S2o => S2o,
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S3o => S3o,
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S3o => S3o,
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SLo => SLo);
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SLo => SLo);
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-- synopsys synthesis_on
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-- synopsys synthesis_on
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end FlagController1;
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end FlagController1;
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