-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Politecnico di Torino
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-- Politecnico di Torino
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-- Dipartimento di Automatica e Informatica
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-- Dipartimento di Automatica e Informatica
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : EPC Class1 Gen2 RFID Tag - CRC16 encoder/decoder
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-- Title : EPC Class1 Gen2 RFID Tag - CRC16 encoder/decoder
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--
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--
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-- File name : crc16encdec.vhd
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-- File name : crc16encdec.vhd
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--
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--
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-- Description : Tag CRC16 encoder/decoder
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-- Description : Tag CRC16 encoder/decoder
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--
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--
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-- Authors : Erwing R. Sanchez <erwing.sanchezsanchez@polito.it>
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-- Authors : Erwing R. Sanchez <erwing.sanchez@polito.it>
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--
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-- Rev. History : 10 July 06
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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entity crc16encdec is
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entity crc16encdec is
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generic(
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generic(
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PRESET_CRC16 : integer := 65535); -- X"FFFF"
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PRESET_CRC16 : integer := 65535); -- X"FFFF"
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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init : in std_logic;
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init : in std_logic;
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ce : in std_logic;
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ce : in std_logic;
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sdi : in std_logic;
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sdi : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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cout : out std_logic_vector(15 downto 0));
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end crc16encdec;
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end crc16encdec;
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architecture CRC16beh of crc16encdec is
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architecture CRC16beh of crc16encdec is
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signal crc16reg : std_logic_vector(15 downto 0);
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signal crc16reg : std_logic_vector(15 downto 0);
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begin -- CRC16beh
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begin -- CRC16beh
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process (clk, rst_n)
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process (clk, rst_n)
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begin -- process
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begin -- process
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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crc16reg <= (others => '0');
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crc16reg <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if init = '1' then
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if init = '1' then
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crc16reg <= conv_std_logic_vector(PRESET_CRC16,16);
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crc16reg <= conv_std_logic_vector(PRESET_CRC16,16);
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elsif ce = '1' then
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elsif ce = '1' then
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crc16reg(0) <= crc16reg(15) xor sdi;
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crc16reg(0) <= crc16reg(15) xor sdi;
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crc16reg(4 downto 1) <= crc16reg(3 downto 0);
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crc16reg(4 downto 1) <= crc16reg(3 downto 0);
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crc16reg(5) <= crc16reg(15) xor sdi xor crc16reg(4);
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crc16reg(5) <= crc16reg(15) xor sdi xor crc16reg(4);
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crc16reg(11 downto 6) <= crc16reg(10 downto 5);
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crc16reg(11 downto 6) <= crc16reg(10 downto 5);
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crc16reg(12) <= crc16reg(15) xor sdi xor crc16reg(11);
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crc16reg(12) <= crc16reg(15) xor sdi xor crc16reg(11);
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crc16reg(15 downto 13) <= crc16reg(14 downto 12);
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crc16reg(15 downto 13) <= crc16reg(14 downto 12);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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cout <= crc16reg;
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cout <= crc16reg;
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end CRC16beh;
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end CRC16beh;
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