----------------------------------------------------------------------------------
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-- Company: Carnegie Mellon University, Pittsburgh PA
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-- Engineer: Justin Wagner
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--
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-- Create Date: 7/Oct/2011
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-- Design Name:
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-- Module Name: tb_arp_package - testbench
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-- Project Name:
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-- Target Devices: n/a
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-- Tool versions:
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--
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-- Dependencies: arp_package.vhdl (Definitions of various constants)
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--
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use std.textio.all;
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use std.textio.all;
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use work.arp_package.all;
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use work.arp_package.all;
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entity tb_arp_responder is
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entity tb_arp_responder is
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--empty
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--empty
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end tb_arp_responder;
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end tb_arp_responder;
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architecture beh of tb_arp_responder is
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architecture beh of tb_arp_responder is
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COMPONENT arp_responder
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COMPONENT arp_responder
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PORT(
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PORT(
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ARESET : IN std_logic;
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ARESET : IN std_logic;
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MY_MAC : IN std_logic_vector(47 downto 0);
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MY_MAC : IN std_logic_vector(47 downto 0);
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MY_IPV4 : IN std_logic_vector(31 downto 0);
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MY_IPV4 : IN std_logic_vector(31 downto 0);
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CLK_RX : IN std_logic;
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CLK_RX : IN std_logic;
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DATA_VALID_RX : IN std_logic;
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DATA_VALID_RX : IN std_logic;
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DATA_RX : IN std_logic_vector(7 downto 0);
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DATA_RX : IN std_logic_vector(7 downto 0);
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CLK_TX : IN std_logic;
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CLK_TX : IN std_logic;
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DATA_ACK_TX : IN std_logic;
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DATA_ACK_TX : IN std_logic;
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DATA_VALID_TX : OUT std_logic;
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DATA_VALID_TX : OUT std_logic;
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DATA_TX : OUT std_logic_vector(7 downto 0)
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DATA_TX : OUT std_logic_vector(7 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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constant severity_c : severity_level := failure;
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constant severity_c : severity_level := failure;
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--Inputs
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--Inputs
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signal ARESET : std_logic := '0';
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signal ARESET : std_logic := '0';
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signal MY_MAC : std_logic_vector(47 downto 0) := x"00_01_42_00_5F_FF";
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signal MY_MAC : std_logic_vector(47 downto 0) := x"00_01_42_00_5F_FF";
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signal MY_IPV4 : std_logic_vector(31 downto 0) := x"C0_A8_01_02";
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signal MY_IPV4 : std_logic_vector(31 downto 0) := x"C0_A8_01_02";
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signal CLK_RX : std_logic := '0';
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signal CLK_RX : std_logic := '0';
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signal DATA_VALID_RX : std_logic := '0';
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signal DATA_VALID_RX : std_logic := '0';
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signal DATA_RX : std_logic_vector(7 downto 0) := (others => '0');
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signal DATA_RX : std_logic_vector(7 downto 0) := (others => '0');
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signal CLK_TX : std_logic := '0';
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signal CLK_TX : std_logic := '0';
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signal TB_CLK : std_logic := '0';
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signal TB_CLK : std_logic := '0';
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signal DATA_ACK_TX : std_logic := '0';
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signal DATA_ACK_TX : std_logic := '0';
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--Outputs
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--Outputs
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signal DATA_VALID_TX : std_logic;
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signal DATA_VALID_TX : std_logic;
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signal DATA_TX : std_logic_vector(7 downto 0);
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signal DATA_TX : std_logic_vector(7 downto 0);
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-- Clock period definitions
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-- Clock period definitions
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constant CLK_period : time := 8 ns;
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constant CLK_period : time := 8 ns;
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constant TB_CLK_SKEW : time := 1 ns;
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constant TB_CLK_SKEW : time := 1 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: arp_responder PORT MAP (
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uut: arp_responder PORT MAP (
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ARESET => ARESET,
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ARESET => ARESET,
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MY_MAC => MY_MAC,
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MY_MAC => MY_MAC,
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MY_IPV4 => MY_IPV4,
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MY_IPV4 => MY_IPV4,
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CLK_RX => CLK_RX,
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CLK_RX => CLK_RX,
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DATA_VALID_RX => DATA_VALID_RX,
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DATA_VALID_RX => DATA_VALID_RX,
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DATA_RX => DATA_RX,
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DATA_RX => DATA_RX,
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CLK_TX => CLK_TX,
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CLK_TX => CLK_TX,
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DATA_ACK_TX => DATA_ACK_TX,
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DATA_ACK_TX => DATA_ACK_TX,
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DATA_VALID_TX => DATA_VALID_TX,
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DATA_VALID_TX => DATA_VALID_TX,
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DATA_TX => DATA_TX
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DATA_TX => DATA_TX
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);
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);
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----Testbench Clock Generator:
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----Testbench Clock Generator:
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tb_clk_gen : process
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tb_clk_gen : process
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begin
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begin
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TB_CLK <= '0';
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TB_CLK <= '0';
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wait for CLK_period/2;
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wait for CLK_period/2;
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TB_CLK <= '1';
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TB_CLK <= '1';
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wait for CLK_period/2;
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wait for CLK_period/2;
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end process;
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end process;
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CLK_RX <= transport TB_CLK after TB_CLK_SKEW;
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CLK_RX <= transport TB_CLK after TB_CLK_SKEW;
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CLK_TX <= not(CLK_RX);
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CLK_TX <= not(CLK_RX);
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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--
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--
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-- wait for the rising edge of tb_ck
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-- wait for the rising edge of tb_ck
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--
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--
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procedure wait_tb_clk(num_cyc : integer := 1) is
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procedure wait_tb_clk(num_cyc : integer := 1) is
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begin
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begin
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for i in 1 to num_cyc loop
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for i in 1 to num_cyc loop
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wait until TB_CLK'event and TB_CLK = '1';
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wait until TB_CLK'event and TB_CLK = '1';
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end loop;
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end loop;
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end wait_tb_clk;
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end wait_tb_clk;
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--
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--
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-- wait for the rising edge of rx clk
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-- wait for the rising edge of rx clk
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--
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--
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procedure wait_rx_clk(num_cyc : integer := 1) is
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procedure wait_rx_clk(num_cyc : integer := 1) is
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begin
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begin
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for i in 1 to num_cyc loop
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for i in 1 to num_cyc loop
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wait until CLK_RX'event and CLK_RX = '1';
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wait until CLK_RX'event and CLK_RX = '1';
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end loop;
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end loop;
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end wait_rx_clk;
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end wait_rx_clk;
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--
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--
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-- wait for the rising edge of tx clk
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-- wait for the rising edge of tx clk
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--
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--
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procedure wait_tx_clk(num_cyc : integer := 1) is
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procedure wait_tx_clk(num_cyc : integer := 1) is
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begin
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begin
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for i in 1 to num_cyc loop
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for i in 1 to num_cyc loop
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wait until CLK_TX'event and CLK_TX = '1';
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wait until CLK_TX'event and CLK_TX = '1';
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end loop;
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end loop;
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end wait_tx_clk;
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end wait_tx_clk;
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--
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--
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-- Generate a valid ARP request
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-- Generate a valid ARP request
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--
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--
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procedure gen_valid_arp_req is
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procedure gen_valid_arp_req is
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begin
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begin
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-- Set the Data Valid flag
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-- Set the Data Valid flag
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DATA_VALID_RX <= '1';
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DATA_VALID_RX <= '1';
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-- Generate BDCST DA
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-- Generate BDCST DA
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for i in 0 to 5 loop
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for i in 0 to 5 loop
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DATA_RX <= MAC_BDCST_ADDR(i);
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DATA_RX <= MAC_BDCST_ADDR(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate SA
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-- Generate SA
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for i in 0 to 5 loop
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for i in 0 to 5 loop
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DATA_RX <= CMP_A_MAC_ADDR(i);
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DATA_RX <= CMP_A_MAC_ADDR(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate ARP E_TYPE
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-- Generate ARP E_TYPE
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for i in 0 to 1 loop
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for i in 0 to 1 loop
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DATA_RX <= E_TYPE_ARP(i);
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DATA_RX <= E_TYPE_ARP(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate Ethernet H_TYPE
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-- Generate Ethernet H_TYPE
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for i in 0 to 1 loop
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for i in 0 to 1 loop
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DATA_RX <= H_TYPE_ETH(i);
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DATA_RX <= H_TYPE_ETH(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate IPV4 P_TYPE
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-- Generate IPV4 P_TYPE
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for i in 0 to 1 loop
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for i in 0 to 1 loop
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DATA_RX <= P_TYPE_IPV4(i);
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DATA_RX <= P_TYPE_IPV4(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate Ethernet H_LEN
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-- Generate Ethernet H_LEN
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DATA_RX <= H_TYPE_ETH_LEN;
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DATA_RX <= H_TYPE_ETH_LEN;
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wait_tb_clk;
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wait_tb_clk;
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-- Generate IPV4 P_LEN
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-- Generate IPV4 P_LEN
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DATA_RX <= P_TYPE_IPV4_LEN;
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DATA_RX <= P_TYPE_IPV4_LEN;
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wait_tb_clk;
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wait_tb_clk;
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-- Generate OPER for ARP Request
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-- Generate OPER for ARP Request
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for i in 0 to 1 loop
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for i in 0 to 1 loop
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DATA_RX <= ARP_OPER_REQ(i);
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DATA_RX <= ARP_OPER_REQ(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate SHA
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-- Generate SHA
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for i in 0 to 5 loop
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for i in 0 to 5 loop
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DATA_RX <= CMP_A_MAC_ADDR(i);
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DATA_RX <= CMP_A_MAC_ADDR(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate SPA
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-- Generate SPA
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for i in 0 to 3 loop
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for i in 0 to 3 loop
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DATA_RX <= CMP_A_IPV4_ADDR(i);
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DATA_RX <= CMP_A_IPV4_ADDR(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate THA
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-- Generate THA (Zero since we don't know it!)
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for i in 0 to 5 loop
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for i in 0 to 5 loop
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DATA_RX <= MY_MAC((47-i*8) downto (40-i*8));
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DATA_RX <= (others => '0');
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate TPA
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-- Generate TPA
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for i in 0 to 3 loop
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for i in 0 to 3 loop
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DATA_RX <= MY_IPV4((31-i*8) downto (24-i*8));
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DATA_RX <= MY_IPV4((31-i*8) downto (24-i*8));
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Remove the Data Valid flag
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-- Remove the Data Valid flag
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DATA_VALID_RX <= '0';
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DATA_VALID_RX <= '0';
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-- End of Generated ARP Packet
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-- End of Generated ARP Packet
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end gen_valid_arp_req;
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end gen_valid_arp_req;
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--
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--
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-- Generate a valid ARP request
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-- Generate a valid ARP request
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--
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--
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procedure gen_valid_eth_pkt(payload_size_bytes : integer := 46) is
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procedure gen_valid_eth_pkt(payload_size_bytes : integer := 46) is
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begin
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begin
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-- Set the Data Valid flag
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-- Set the Data Valid flag
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DATA_VALID_RX <= '1';
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DATA_VALID_RX <= '1';
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-- Generate BDCST DA
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-- Generate BDCST DA
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for i in 0 to 5 loop
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for i in 0 to 5 loop
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DATA_RX <= MY_MAC((47-i*8) downto (40-i*8));
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DATA_RX <= MY_MAC((47-i*8) downto (40-i*8));
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate SA
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-- Generate SA
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for i in 0 to 5 loop
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for i in 0 to 5 loop
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DATA_RX <= CMP_A_MAC_ADDR(i);
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DATA_RX <= CMP_A_MAC_ADDR(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate E_TYPE for IPV4
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-- Generate E_TYPE for IPV4
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for i in 0 to 1 loop
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for i in 0 to 1 loop
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DATA_RX <= P_TYPE_IPV4(i);
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DATA_RX <= P_TYPE_IPV4(i);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate Payload
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-- Generate Payload
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for i in 1 to payload_size_bytes loop
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for i in 1 to payload_size_bytes loop
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-- Incrementing bytes for payload
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-- Incrementing bytes for payload
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DATA_RX <= conv_std_logic_vector((i-1),8);
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DATA_RX <= conv_std_logic_vector((i-1),8);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Generate fake FCS
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-- Generate fake FCS
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for i in 1 to 4 loop
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for i in 1 to 4 loop
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-- Incrementing bytes for FCS (x"F0",x"F1",etc)
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-- Incrementing bytes for FCS (x"F0",x"F1",etc)
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DATA_RX <= conv_std_logic_vector(240+(i-1),8);
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DATA_RX <= conv_std_logic_vector(240+(i-1),8);
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wait_tb_clk;
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wait_tb_clk;
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end loop;
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end loop;
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-- Remove the Data Valid flag
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-- Remove the Data Valid flag
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DATA_VALID_RX <= '0';
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DATA_VALID_RX <= '0';
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-- End of Generated Ethernet Packet
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-- End of Generated Ethernet Packet
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end gen_valid_eth_pkt;
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end gen_valid_eth_pkt;
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--
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--
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-- Receive an ARP response
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-- Receive an ARP response
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--
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--
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procedure rec_arp_resp(wait_data_ack_tx : integer := 10) is
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procedure rec_arp_resp(wait_data_ack_tx : integer := 10) is
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begin
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begin
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-- Handle the response
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-- Handle the response
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wait until DATA_VALID_TX = '1';
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wait until DATA_VALID_TX = '1';
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wait_tx_clk(wait_data_ack_tx);
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wait_tx_clk(wait_data_ack_tx);
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DATA_ACK_TX <= '1';
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DATA_ACK_TX <= '1';
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wait_tx_clk;
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wait_tx_clk;
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DATA_ACK_TX <= '0';
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DATA_ACK_TX <= '0';
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wait until DATA_VALID_TX = '0';
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wait until DATA_VALID_TX = '0';
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end rec_arp_resp;
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end rec_arp_resp;
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--
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--
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-- Reset the Testbench
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-- Reset the Testbench
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--
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--
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procedure reset_tb(time : integer := 10) is
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procedure reset_tb(time : integer := 10) is
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begin
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begin
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-- hold reset state
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-- hold reset state
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wait_tb_clk;
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wait_tb_clk;
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ARESET <= '1';
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ARESET <= '1';
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wait_tb_clk(time);
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wait_tb_clk(time);
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ARESET <= '0';
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ARESET <= '0';
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end reset_tb;
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end reset_tb;
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-------------------------------------------------------------
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-------------------------------------------------------------
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----- BEGIN PROCESS -----------------------------------------
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----- BEGIN PROCESS -----------------------------------------
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-------------------------------------------------------------
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-------------------------------------------------------------
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begin
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begin
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reset_tb;
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reset_tb;
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gen_valid_arp_req;
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gen_valid_arp_req;
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rec_arp_resp;
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rec_arp_resp;
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wait_tb_clk(10);
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wait_tb_clk(10);
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gen_valid_eth_pkt(46);
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gen_valid_eth_pkt(46);
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wait_tb_clk(10);
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wait_tb_clk(10);
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gen_valid_arp_req;
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gen_valid_arp_req;
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rec_arp_resp;
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rec_arp_resp;
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wait_tb_clk(10);
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wait_tb_clk(10);
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gen_valid_arp_req;
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gen_valid_arp_req;
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rec_arp_resp;
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rec_arp_resp;
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wait_tb_clk(10);
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wait_tb_clk(10);
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gen_valid_eth_pkt(46);
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gen_valid_eth_pkt(46);
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wait_tb_clk(10);
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wait_tb_clk(10);
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gen_valid_eth_pkt(76);
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gen_valid_eth_pkt(76);
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wait_tb_clk(10);
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wait_tb_clk(10);
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-- stop the simulation once you're done
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-- stop the simulation once you're done
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wait_tb_clk(50);
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wait_tb_clk(50);
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assert false
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assert false
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report "End of Simulation"
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report "End of Simulation"
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severity severity_c;
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severity severity_c;
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end process;
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end process;
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end beh;
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end beh;
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