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https://opencores.org/ocsvn/ether_arp_1g/ether_arp_1g/trunk
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-- Company: Carnegie Mellon University, Pittsburgh PA
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-- Engineer: Justin Wagner
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--
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-- Create Date: 7/Oct/2011
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-- Design Name:
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-- Module Name: tb_edge_detector - testbench
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-- Project Name:
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-- Target Devices: n/a
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-- Tool versions:
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--
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-- Dependencies:
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--
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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entity tb_edge_detector is
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entity tb_edge_detector is
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--empty
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--empty
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end tb_edge_detector;
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end tb_edge_detector;
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architecture beh of tb_edge_detector is
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architecture beh of tb_edge_detector is
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component edge_detector
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component edge_detector
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port(
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port(
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din : in std_logic;
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din : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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dout : out std_logic
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dout : out std_logic
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);
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);
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end component edge_detector;
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end component edge_detector;
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--signal declaration
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--signal declaration
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signal clk_net : std_logic;
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signal clk_net : std_logic;
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signal rst_n_net : std_logic;
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signal rst_n_net : std_logic;
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signal din_net : std_logic;
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signal din_net : std_logic;
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signal dout_net : std_logic;
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signal dout_net : std_logic;
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begin
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begin
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inst_1: edge_detector
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inst_1: edge_detector
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port map(
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port map(
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din => din_net,
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din => din_net,
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clk => clk_net,
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clk => clk_net,
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rst_n => rst_n_net,
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rst_n => rst_n_net,
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dout => dout_net
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dout => dout_net
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);
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);
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clk_p : process
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clk_p : process
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begin
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begin
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clk_net <= '0';
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clk_net <= '0';
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wait for 2 ns;
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wait for 2 ns;
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clk_net <= '1';
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clk_net <= '1';
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wait for 2 ns;
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wait for 2 ns;
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end process clk_p;
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end process clk_p;
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input_data : process
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input_data : process
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begin
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begin
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din_net <= '0';
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din_net <= '0';
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wait for 7 ns;
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wait for 7 ns;
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din_net <= '1';
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din_net <= '1';
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wait for 10 ns;
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wait for 10 ns;
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din_net <= '0';
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din_net <= '0';
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wait for 20 ns;
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wait for 20 ns;
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end process input_data;
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end process input_data;
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test_bench : process
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test_bench : process
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begin
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begin
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rst_n_net <= '0';
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rst_n_net <= '0';
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wait for 1 ns;
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wait for 1 ns;
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rst_n_net <= '1';
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rst_n_net <= '1';
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wait for 100 ns;
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wait for 100 ns;
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assert false
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assert false
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report "End of Simulation"
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report "End of Simulation"
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severity failure;
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severity failure;
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end process test_bench;
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end process test_bench;
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end beh;
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end beh;
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