/******************************************************************************
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/******************************************************************************
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$Id: fifo_beh.v,v 1.1 2002-03-10 17:18:37 johnsonw10 Exp $
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$Id: fifo_beh.v,v 1.1 2002-03-10 17:18:37 johnsonw10 Exp $
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Author(s): Johnsonw10@opencors.org
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Author(s): Johnsonw10@opencors.org
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Revision History:
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Revision History:
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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******************************************************************************/
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******************************************************************************/
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`timescale 1 ns / 100 ps
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`timescale 1 ns / 100 ps
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module fifo_beh (
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module fifo_beh (
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clk,
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clk,
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reset_n,
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reset_n,
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wr,
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wr,
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din,
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din,
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rd,
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rd,
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dout,
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dout,
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empty,
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empty,
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full
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full
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);
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);
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parameter DATA_WIDTH = 32;
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parameter DATA_WIDTH = 32;
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parameter FIFO_SIZE = 64;
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parameter FIFO_SIZE = 64;
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input reset_n;
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input reset_n;
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input clk;
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input clk;
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input wr;
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input wr;
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input [0:DATA_WIDTH-1] din;
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input [0:DATA_WIDTH-1] din;
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input rd;
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input rd;
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output [0:DATA_WIDTH-1] dout;
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output [0:DATA_WIDTH-1] dout;
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reg [0:DATA_WIDTH-1] dout;
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reg [0:DATA_WIDTH-1] dout;
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output empty;
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output empty;
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output full;
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output full;
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reg [0:DATA_WIDTH-1] mem[0:FIFO_SIZE-1];
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reg [0:DATA_WIDTH-1] mem[0:FIFO_SIZE-1];
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integer rd_ptr, wr_ptr, dcnt;
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integer rd_ptr, wr_ptr, dcnt;
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wire empty_o, full_o;
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wire empty_o, full_o;
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wire rd_i = rd & (!empty_o);
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wire rd_i = rd & (!empty_o);
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wire wr_i = wr & (!full_o);
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wire wr_i = wr & (!full_o);
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always @ (negedge reset_n or posedge clk) begin
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always @ (negedge reset_n or posedge clk) begin
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if (!reset_n) begin
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if (!reset_n) begin
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rd_ptr <= 0;
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rd_ptr <= 0;
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wr_ptr <= 0;
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wr_ptr <= 0;
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dcnt <= 0;
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dcnt <= 0;
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end
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end
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else begin
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else begin
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if (rd_i) begin
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if (rd_i) begin
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dout <= mem[rd_ptr];
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dout <= mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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rd_ptr <= rd_ptr + 1;
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end
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end
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if (wr_i) begin
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if (wr_i) begin
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mem[wr_ptr] <= din;
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mem[wr_ptr] <= din;
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wr_ptr <= wr_ptr + 1;
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wr_ptr <= wr_ptr + 1;
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end
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end
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if (rd_i && wr_i)
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if (rd_i && wr_i)
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dcnt <= dcnt;
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dcnt <= dcnt;
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else if (rd_i)
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else if (rd_i)
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dcnt <= dcnt - 1;
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dcnt <= dcnt - 1;
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else if (wr_i)
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else if (wr_i)
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dcnt <= dcnt + 1;
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dcnt <= dcnt + 1;
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end
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end
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end
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end
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assign empty_o = (dcnt == 0);
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assign empty_o = (dcnt == 0);
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assign full_o = (dcnt == FIFO_SIZE);
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assign full_o = (dcnt == FIFO_SIZE);
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assign empty = empty_o;
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assign empty = empty_o;
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assign full = full_o;
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assign full = full_o;
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