// +----------------------------------------------------------------------------
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/* --------------------------------------------------------------------------------
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// Universidade Federal da Bahia
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This file is part of FPGA Median Filter.
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//------------------------------------------------------------------------------
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// PROJECT: FPGA Median Filter
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FPGA Median Filter is free software: you can redistribute it and/or modify
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//------------------------------------------------------------------------------
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it under the terms of the GNU General Public License as published by
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// FILE NAME : median.v
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the Free Software Foundation, either version 3 of the License, or
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// AUTHOR : Joo Carlos Bittencourt
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(at your option) any later version.
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// AUTHOR'S E-MAIL : joaocarlos@ieee.org
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// -----------------------------------------------------------------------------
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FPGA Median Filter is distributed in the hope that it will be useful,
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// RELEASE HISTORY
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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// VERSION DATE AUTHOR DESCRIPTION
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// 1.0 2013-08-13 joao.nunes initial version
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GNU General Public License for more details.
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// 2.0 2013-09-06 laur.rami fix minnor issues on memory address
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// -----------------------------------------------------------------------------
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You should have received a copy of the GNU General Public License
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// KEYWORDS: median, filter, image processing, state machine
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along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>.
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// -----------------------------------------------------------------------------
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-------------------------------------------------------------------------------- */
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// PURPOSE: Windowing Memory Address Controller.
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/* +----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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Universidade Federal da Bahia
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------------------------------------------------------------------------------
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PROJECT: FPGA Median Filter
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------------------------------------------------------------------------------
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FILE NAME : median.v
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AUTHOR : Joo Carlos Bittencourt
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AUTHOR'S E-MAIL : joaocarlos@ieee.org
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-----------------------------------------------------------------------------
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RELEASE HISTORY
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VERSION DATE AUTHOR DESCRIPTION
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1.0 2013-08-13 joao.nunes initial version
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2.0 2013-09-06 laur.rami fix minnor issues on memory address
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-----------------------------------------------------------------------------
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KEYWORDS: median, filter, image processing, state machine
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-----------------------------------------------------------------------------
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PURPOSE: Windowing Memory Address Controller.
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----------------------------------------------------------------------------- */
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module state_machine
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module state_machine
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#(
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#(
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parameter LUT_ADDR_WIDTH = 10,
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parameter LUT_ADDR_WIDTH = 10,
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parameter IMG_WIDTH = 234,
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parameter IMG_WIDTH = 234,
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parameter IMG_HEIGHT = 234
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parameter IMG_HEIGHT = 234
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)(
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)(
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input clk, // Clock
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input clk, // Clock
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input rst_n, // Asynchronous reset active low
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input rst_n, // Asynchronous reset active low
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output reg [LUT_ADDR_WIDTH-1:0] raddr_a,
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output reg [LUT_ADDR_WIDTH-1:0] raddr_a,
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output reg [LUT_ADDR_WIDTH-1:0] raddr_b,
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output reg [LUT_ADDR_WIDTH-1:0] raddr_b,
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output reg [LUT_ADDR_WIDTH-1:0] raddr_c,
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output reg [LUT_ADDR_WIDTH-1:0] raddr_c,
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output reg [LUT_ADDR_WIDTH-1:0] waddr,
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output reg [LUT_ADDR_WIDTH-1:0] waddr,
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output reg [1:0] window_line_counter,
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output reg [1:0] window_line_counter,
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output reg [9:0] window_column_counter,
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output reg [9:0] window_column_counter,
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output reg [9:0] memory_shift
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output reg [9:0] memory_shift
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);
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);
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reg valid;
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reg valid;
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always @(posedge clk or negedge rst_n)
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always @(posedge clk or negedge rst_n)
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begin : out_memory_counter
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begin : out_memory_counter
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if(~rst_n) begin
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if(~rst_n) begin
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waddr <= {LUT_ADDR_WIDTH{1'b0}};
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waddr <= {LUT_ADDR_WIDTH{1'b0}};
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end else if(valid) begin
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end else if(valid) begin
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waddr <= waddr + 1'b1;
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waddr <= waddr + 1'b1;
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end
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end
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end
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end
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always @(posedge clk or negedge rst_n)
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always @(posedge clk or negedge rst_n)
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begin : addr_counter
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begin : addr_counter
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if(~rst_n) begin
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if(~rst_n) begin
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window_column_counter <= 10'd0;
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window_column_counter <= 10'd0;
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window_line_counter <= 2'b00;
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window_line_counter <= 2'b00;
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raddr_a <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_a <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_b <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_b <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_c <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_c <= {LUT_ADDR_WIDTH{1'b0}};
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end else begin
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end else begin
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if(window_column_counter != ((IMG_WIDTH/4)-1)) begin
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if(window_column_counter != ((IMG_WIDTH/4)-1)) begin
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window_column_counter <= window_column_counter + 1'b1;
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window_column_counter <= window_column_counter + 1'b1;
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valid <= 1'b1;
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valid <= 1'b1;
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raddr_a <= raddr_a + 1'b1;
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raddr_a <= raddr_a + 1'b1;
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raddr_b <= raddr_b + 1'b1;
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raddr_b <= raddr_b + 1'b1;
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raddr_c <= raddr_c + 1'b1;
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raddr_c <= raddr_c + 1'b1;
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end else begin
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end else begin
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window_column_counter <= 10'd0;
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window_column_counter <= 10'd0;
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case (window_line_counter)
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case (window_line_counter)
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2'b00 :
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2'b00 :
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begin
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begin
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raddr_a <= raddr_a + 1'b1;
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raddr_a <= raddr_a + 1'b1;
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raddr_b <= raddr_b - window_column_counter;
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raddr_b <= raddr_b - window_column_counter;
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raddr_c <= raddr_c - window_column_counter;
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raddr_c <= raddr_c - window_column_counter;
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window_line_counter = window_line_counter + 1'b1;
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window_line_counter = window_line_counter + 1'b1;
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end
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end
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2'b01 :
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2'b01 :
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begin
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begin
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raddr_b <= raddr_b + 1'b1;
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raddr_b <= raddr_b + 1'b1;
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raddr_a <= raddr_a - window_column_counter;
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raddr_a <= raddr_a - window_column_counter;
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raddr_c <= raddr_c - window_column_counter;
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raddr_c <= raddr_c - window_column_counter;
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window_line_counter = window_line_counter + 1'b1;
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window_line_counter = window_line_counter + 1'b1;
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end
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end
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2'b10 :
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2'b10 :
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begin
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begin
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raddr_b <= raddr_b - window_column_counter;
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raddr_b <= raddr_b - window_column_counter;
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raddr_a <= raddr_a - window_column_counter;
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raddr_a <= raddr_a - window_column_counter;
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raddr_c <= raddr_c + 1'b1;
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raddr_c <= raddr_c + 1'b1;
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window_line_counter = 2'b00;
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window_line_counter = 2'b00;
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end
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end
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default :
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default :
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begin
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begin
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raddr_a <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_a <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_b <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_b <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_c <= {LUT_ADDR_WIDTH{1'b0}};
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raddr_c <= {LUT_ADDR_WIDTH{1'b0}};
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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