-- VHDL Entity HAVOC.FPadd_stage3.interface
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-- VHDL Entity work.FPadd_stage3.interface
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPadd_stage3 IS
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ENTITY FPadd_stage3 IS
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PORT(
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PORT(
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A_SIGN_stage2 : IN std_logic;
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A_SIGN_stage2 : IN std_logic;
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A_align : IN std_logic_vector (28 DOWNTO 0);
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A_align : IN std_logic_vector (28 DOWNTO 0);
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B_XSIGN_stage2 : IN std_logic;
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B_XSIGN_stage2 : IN std_logic;
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B_align : IN std_logic_vector (28 DOWNTO 0);
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B_align : IN std_logic_vector (28 DOWNTO 0);
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EXP_base_stage2 : IN std_logic_vector (7 DOWNTO 0);
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EXP_base_stage2 : IN std_logic_vector (7 DOWNTO 0);
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cin : IN std_logic;
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cin : IN std_logic;
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clk : IN std_logic;
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clk : IN std_logic;
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invert_A : IN std_logic;
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invert_A : IN std_logic;
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invert_B : IN std_logic;
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invert_B : IN std_logic;
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isINF_tab_stage2 : IN std_logic;
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isINF_tab_stage2 : IN std_logic;
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isNaN_stage2 : IN std_logic;
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isNaN_stage2 : IN std_logic;
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isZ_tab_stage2 : IN std_logic;
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isZ_tab_stage2 : IN std_logic;
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A_SIGN_stage3 : OUT std_logic;
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A_SIGN_stage3 : OUT std_logic;
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B_XSIGN_stage3 : OUT std_logic;
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B_XSIGN_stage3 : OUT std_logic;
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EXP_base : OUT std_logic_vector (7 DOWNTO 0);
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EXP_base : OUT std_logic_vector (7 DOWNTO 0);
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add_out : OUT std_logic_vector (28 DOWNTO 0);
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add_out : OUT std_logic_vector (28 DOWNTO 0);
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isINF_tab_stage3 : OUT std_logic;
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isINF_tab_stage3 : OUT std_logic;
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isNaN_stage3 : OUT std_logic;
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isNaN_stage3 : OUT std_logic;
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isZ_tab_stage3 : OUT std_logic
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isZ_tab_stage3 : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FPadd_stage3 ;
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END FPadd_stage3 ;
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--
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--
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-- VHDL Architecture HAVOC.FPadd_stage3.struct
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-- VHDL Architecture work.FPadd_stage3.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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LIBRARY HAVOC;
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ARCHITECTURE struct OF FPadd_stage3 IS
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ARCHITECTURE struct OF FPadd_stage3 IS
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL A_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL A_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL add_out_int : std_logic_vector(28 DOWNTO 0);
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SIGNAL add_out_int : std_logic_vector(28 DOWNTO 0);
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-- Component Declarations
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-- Component Declarations
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COMPONENT FPinvert
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COMPONENT FPinvert
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GENERIC (
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GENERIC (
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width : integer := 29
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width : integer := 29
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);
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);
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PORT (
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PORT (
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A_in : IN std_logic_vector (width-1 DOWNTO 0);
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A_in : IN std_logic_vector (width-1 DOWNTO 0);
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B_in : IN std_logic_vector (width-1 DOWNTO 0);
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B_in : IN std_logic_vector (width-1 DOWNTO 0);
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invert_A : IN std_logic ;
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invert_A : IN std_logic ;
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invert_B : IN std_logic ;
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invert_B : IN std_logic ;
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
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B_out : OUT std_logic_vector (width-1 DOWNTO 0)
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B_out : OUT std_logic_vector (width-1 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : FPinvert USE ENTITY HAVOC.FPinvert;
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FOR ALL : FPinvert USE ENTITY work.FPinvert;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 reg1
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-- HDL Embedded Text Block 1 reg1
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-- reg1 1
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-- reg1 1
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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add_out <= add_out_int;
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add_out <= add_out_int;
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EXP_base <= EXP_base_stage2;
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EXP_base <= EXP_base_stage2;
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A_SIGN_stage3 <= A_SIGN_stage2;
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A_SIGN_stage3 <= A_SIGN_stage2;
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B_XSIGN_stage3 <= B_XSIGN_stage2;
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B_XSIGN_stage3 <= B_XSIGN_stage2;
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isINF_tab_stage3 <= isINF_tab_stage2;
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isINF_tab_stage3 <= isINF_tab_stage2;
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isNaN_stage3 <= isNaN_stage2;
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isNaN_stage3 <= isNaN_stage2;
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isZ_tab_stage3 <= isZ_tab_stage2;
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isZ_tab_stage3 <= isZ_tab_stage2;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- ModuleWare code(v1.1) for instance 'I4' of 'add'
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-- ModuleWare code(v1.1) for instance 'I4' of 'add'
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I4combo: PROCESS (A_inv, B_inv, cin)
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I4combo: PROCESS (A_inv, B_inv, cin)
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VARIABLE mw_I4t0 : std_logic_vector(29 DOWNTO 0);
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VARIABLE mw_I4t0 : std_logic_vector(29 DOWNTO 0);
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VARIABLE mw_I4t1 : std_logic_vector(29 DOWNTO 0);
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VARIABLE mw_I4t1 : std_logic_vector(29 DOWNTO 0);
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VARIABLE mw_I4sum : signed(29 DOWNTO 0);
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VARIABLE mw_I4sum : signed(29 DOWNTO 0);
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VARIABLE mw_I4carry : std_logic;
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VARIABLE mw_I4carry : std_logic;
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BEGIN
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BEGIN
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mw_I4t0 := A_inv(28) & A_inv;
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mw_I4t0 := A_inv(28) & A_inv;
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mw_I4t1 := B_inv(28) & B_inv;
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mw_I4t1 := B_inv(28) & B_inv;
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mw_I4carry := cin;
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mw_I4carry := cin;
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mw_I4sum := signed(mw_I4t0) + signed(mw_I4t1) + mw_I4carry;
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mw_I4sum := signed(mw_I4t0) + signed(mw_I4t1) + mw_I4carry;
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add_out_int <= conv_std_logic_vector(mw_I4sum(28 DOWNTO 0),29);
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add_out_int <= conv_std_logic_vector(mw_I4sum(28 DOWNTO 0),29);
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END PROCESS I4combo;
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END PROCESS I4combo;
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-- Instance port mappings.
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-- Instance port mappings.
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I14 : FPinvert
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I14 : FPinvert
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GENERIC MAP (
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GENERIC MAP (
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width => 29
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width => 29
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)
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)
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PORT MAP (
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PORT MAP (
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A_in => A_align,
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A_in => A_align,
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B_in => B_align,
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B_in => B_align,
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invert_A => invert_A,
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invert_A => invert_A,
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invert_B => invert_B,
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invert_B => invert_B,
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A_out => A_inv,
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A_out => A_inv,
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B_out => B_inv
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B_out => B_inv
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);
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);
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END struct;
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END struct;
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