Subversion Repositories fpuvhdl

--

--

-- VHDL Architecture HAVOC.FPnormalize.FPnormalize

-- VHDL Architecture HAVOC.FPnormalize.FPnormalize

--

--

-- Created:

-- Created:

--          by - Guillermo

--          by - Guillermo

--          at - ITESM, 10:51:00 07/16/03

--          at - ITESM, 10:51:00 07/16/03

--

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)

-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)

--

--

-- hds interface_start

-- hds interface_start

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

USE ieee.std_logic_unsigned.all;

ENTITY FPnormalize IS

ENTITY FPnormalize IS

   GENERIC(

   GENERIC(

      SIG_width : integer := 28

      SIG_width : integer := 28

   );

   );

   PORT(

   PORT(

      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);

      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);

      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);

      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);

      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);

      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);

      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)

      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)

   );

   );

-- Declarations

-- Declarations

END FPnormalize ;

END FPnormalize ;

-- hds interface_end

-- hds interface_end

ARCHITECTURE FPnormalize OF FPnormalize IS

ARCHITECTURE FPnormalize OF FPnormalize IS

BEGIN

BEGIN

PROCESS(SIG_in, EXP_in)

PROCESS(SIG_in, EXP_in)

BEGIN

BEGIN

        IF (SIG_in( SIG_width-1 )='1') THEN

        IF (SIG_in( SIG_width-1 )='1') THEN

                SIG_out <= '0' & SIG_in(SIG_width-1 DOWNTO 2) & (SIG_in(1) AND SIG_in(0));

                SIG_out <= '0' & SIG_in(SIG_width-1 DOWNTO 2) & (SIG_in(1) AND SIG_in(0));

                EXP_out <= EXP_in + 1;

                EXP_out <= EXP_in + 1;

        ELSE

        ELSE

                SIG_out <= SIG_in;

                SIG_out <= SIG_in;

                EXP_out <= EXP_in;

                EXP_out <= EXP_in;

        END IF;

        END IF;

END PROCESS;

END PROCESS;

END FPnormalize;

END FPnormalize;