OpenCores
URL https://opencores.org/ocsvn/fpuvhdl/fpuvhdl/trunk

Subversion Repositories fpuvhdl

[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [common/] [fpround_fpround.vhd] - Diff between revs 3 and 5

Only display areas with differences | Details | Blame | View Log

Rev 3 Rev 5
--
--
-- VHDL Architecture HAVOC.FPround.FPround
-- VHDL Architecture HAVOC.FPround.FPround
--
--
-- Created:
-- Created:
--          by - Guillermo
--          by - Guillermo
--          at - ITESM, 11:08:16 07/16/03
--          at - ITESM, 11:08:16 07/16/03
--
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
--
-- hds interface_start
-- hds interface_start
LIBRARY ieee;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_unsigned.all;
 
 
 
 
ENTITY FPround IS
ENTITY FPround IS
   GENERIC(
   GENERIC(
      SIG_width : integer := 28
      SIG_width : integer := 28
   );
   );
   PORT(
   PORT(
      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
   );
   );
 
 
-- Declarations
-- Declarations
 
 
END FPround ;
END FPround ;
 
 
 
 
-- hds interface_end
-- hds interface_end
ARCHITECTURE FPround OF FPround IS
ARCHITECTURE FPround OF FPround IS
BEGIN
BEGIN
        EXP_out <= EXP_in;
        EXP_out <= EXP_in;
 
 
PROCESS(SIG_in)
PROCESS(SIG_in)
BEGIN
BEGIN
--   IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
--   IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
--   IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(2)='1') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
--   IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(2)='1') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
   IF (SIG_in(2)='0') THEN
   IF (SIG_in(2)='0') THEN
                SIG_out <= SIG_in;
                SIG_out <= SIG_in;
   ELSE
   ELSE
                SIG_out <= (SIG_in(SIG_width-1 DOWNTO 3) + 1) & "000";
                SIG_out <= (SIG_in(SIG_width-1 DOWNTO 3) + 1) & "000";
        END IF;
        END IF;
END PROCESS;
END PROCESS;
 
 
END FPround;
END FPround;
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.