--
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--
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-- VHDL Architecture HAVOC.UnpackFP.UnpackFP
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-- VHDL Architecture HAVOC.UnpackFP.UnpackFP
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--
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--
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-- Created:
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-- Created:
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-- by - Guillermo
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-- by - Guillermo
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-- at - ITESM, 09:06:00 07/16/03
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-- at - ITESM, 09:06:00 07/16/03
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
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--
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--
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-- hds interface_start
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-- hds interface_start
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY UnpackFP IS
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ENTITY UnpackFP IS
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PORT(
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PORT(
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FP : IN std_logic_vector (31 DOWNTO 0);
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FP : IN std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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SIGN : OUT std_logic;
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SIGN : OUT std_logic;
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isNaN : OUT std_logic;
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isNaN : OUT std_logic;
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isINF : OUT std_logic;
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isINF : OUT std_logic;
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isZ : OUT std_logic;
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isZ : OUT std_logic;
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isDN : OUT std_logic
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isDN : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END UnpackFP ;
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END UnpackFP ;
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-- hds interface_end
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-- hds interface_end
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ARCHITECTURE UnpackFP OF UnpackFP IS
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ARCHITECTURE UnpackFP OF UnpackFP IS
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SIGNAL exp_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL exp_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL sig_int : std_logic_vector(22 DOWNTO 0);
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SIGNAL sig_int : std_logic_vector(22 DOWNTO 0);
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SIGNAL expZ, expFF, sigZ : std_logic;
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SIGNAL expZ, expFF, sigZ : std_logic;
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BEGIN
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BEGIN
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exp_int <= FP(30 DOWNTO 23);
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exp_int <= FP(30 DOWNTO 23);
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sig_int <= FP(22 DOWNTO 0);
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sig_int <= FP(22 DOWNTO 0);
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SIGN <= FP(31);
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SIGN <= FP(31);
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EXP <= exp_int;
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EXP <= exp_int;
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SIG(22 DOWNTO 0) <= sig_int;
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SIG(22 DOWNTO 0) <= sig_int;
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expZ <= '1' WHEN (exp_int=X"00") ELSE '0';
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expZ <= '1' WHEN (exp_int=X"00") ELSE '0';
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expFF <= '1' WHEN (exp_int=X"FF") ELSE '0';
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expFF <= '1' WHEN (exp_int=X"FF") ELSE '0';
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sigZ <= '1' WHEN (sig_int="00000000000000000000000") ELSE '0';
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sigZ <= '1' WHEN (sig_int="00000000000000000000000") ELSE '0';
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isNaN <= expFF AND (NOT sigZ);
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isNaN <= expFF AND (NOT sigZ);
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isINF <= expFF AND sigZ;
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isINF <= expFF AND sigZ;
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isZ <= expZ AND sigZ;
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isZ <= expZ AND sigZ;
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isDN <= expZ AND (NOT sigZ);
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isDN <= expZ AND (NOT sigZ);
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-- Restore hidden 1.ffff when not zero or denormal
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-- Restore hidden 1.ffff when not zero or denormal
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SIG(23) <= NOT expZ;
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SIG(23) <= NOT expZ;
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SIG(31 DOWNTO 24) <= (OTHERS => '0');
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SIG(31 DOWNTO 24) <= (OTHERS => '0');
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END UnpackFP;
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END UnpackFP;
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