-- VHDL Entity HAVOC.FPmul_stage3.interface
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-- VHDL Entity HAVOC.FPmul_stage3.interface
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPmul_stage3 IS
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ENTITY FPmul_stage3 IS
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PORT(
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PORT(
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_neg_stage2 : IN std_logic;
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EXP_neg_stage2 : IN std_logic;
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EXP_pos_stage2 : IN std_logic;
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EXP_pos_stage2 : IN std_logic;
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SIGN_out_stage2 : IN std_logic;
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SIGN_out_stage2 : IN std_logic;
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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clk : IN std_logic;
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clk : IN std_logic;
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isINF_stage2 : IN std_logic;
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isINF_stage2 : IN std_logic;
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isNaN_stage2 : IN std_logic;
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isNaN_stage2 : IN std_logic;
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isZ_tab_stage2 : IN std_logic;
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isZ_tab_stage2 : IN std_logic;
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EXP_neg : OUT std_logic;
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EXP_neg : OUT std_logic;
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EXP_out_round : OUT std_logic_vector (7 DOWNTO 0);
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EXP_out_round : OUT std_logic_vector (7 DOWNTO 0);
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EXP_pos : OUT std_logic;
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EXP_pos : OUT std_logic;
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SIGN_out : OUT std_logic;
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SIGN_out : OUT std_logic;
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SIG_out_round : OUT std_logic_vector (27 DOWNTO 0);
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SIG_out_round : OUT std_logic_vector (27 DOWNTO 0);
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isINF_tab : OUT std_logic;
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isINF_tab : OUT std_logic;
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isNaN : OUT std_logic;
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isNaN : OUT std_logic;
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isZ_tab : OUT std_logic
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isZ_tab : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FPmul_stage3 ;
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END FPmul_stage3 ;
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--
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--
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-- VHDL Architecture HAVOC.FPmul_stage3.struct
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-- VHDL Architecture HAVOC.FPmul_stage3.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
|
-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE struct OF FPmul_stage3 IS
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ARCHITECTURE struct OF FPmul_stage3 IS
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
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SIGNAL SIG_out : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
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-- Component Declarations
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-- Component Declarations
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COMPONENT FPnormalize
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COMPONENT FPnormalize
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPround
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COMPONENT FPround
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
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FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
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FOR ALL : FPround USE ENTITY work.FPround;
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FOR ALL : FPround USE ENTITY work.FPround;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 latch
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-- HDL Embedded Text Block 1 latch
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-- latch 1
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-- latch 1
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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EXP_out_round <= EXP_out;
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EXP_out_round <= EXP_out;
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SIG_out_round <= SIG_out;
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SIG_out_round <= SIG_out;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 2 latch2
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-- HDL Embedded Text Block 2 latch2
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-- latch2 2
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-- latch2 2
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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isINF_tab <= isINF_stage2;
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isINF_tab <= isINF_stage2;
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isNaN <= isNaN_stage2;
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isNaN <= isNaN_stage2;
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isZ_tab <= isZ_tab_stage2;
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isZ_tab <= isZ_tab_stage2;
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SIGN_out <= SIGN_out_stage2;
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SIGN_out <= SIGN_out_stage2;
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EXP_pos <= EXP_pos_stage2;
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EXP_pos <= EXP_pos_stage2;
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EXP_neg <= EXP_neg_stage2;
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EXP_neg <= EXP_neg_stage2;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- Instance port mappings.
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-- Instance port mappings.
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I9 : FPnormalize
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I9 : FPnormalize
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GENERIC MAP (
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GENERIC MAP (
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SIG_width => 28
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SIG_width => 28
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)
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)
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PORT MAP (
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PORT MAP (
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SIG_in => SIG_in,
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SIG_in => SIG_in,
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EXP_in => EXP_in,
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EXP_in => EXP_in,
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SIG_out => SIG_out_norm,
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SIG_out => SIG_out_norm,
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EXP_out => EXP_out_norm
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EXP_out => EXP_out_norm
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);
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);
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I11 : FPround
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I11 : FPround
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GENERIC MAP (
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GENERIC MAP (
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SIG_width => 28
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SIG_width => 28
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)
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)
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PORT MAP (
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PORT MAP (
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SIG_in => SIG_out_norm,
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SIG_in => SIG_out_norm,
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EXP_in => EXP_out_norm,
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EXP_in => EXP_out_norm,
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SIG_out => SIG_out,
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SIG_out => SIG_out,
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EXP_out => EXP_out
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EXP_out => EXP_out
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);
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);
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END struct;
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END struct;
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