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`include "defines.v"
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`include "defines.v"
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module odd(clk, out, N, reset, enable);
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module odd(clk, out, N, reset, enable);
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input clk; // slow clock
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input clk; // slow clock
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output out; // fast output clock
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output out; // fast output clock
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input [`SIZE-1:0] N; // division factor
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input [`SIZE-1:0] N; // division factor
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input reset; // synchronous reset
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input reset; // synchronous reset
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input enable; // odd enable
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input enable; // odd enable
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reg [`SIZE-1:0] counter; // these 2 counters are used
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reg [`SIZE-1:0] counter; // these 2 counters are used
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reg [`SIZE-1:0] counter2; // to non-overlapping signals
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reg [`SIZE-1:0] counter2; // to non-overlapping signals
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reg out_counter; // positive edge triggered counter
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reg out_counter; // positive edge triggered counter
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reg out_counter2; // negative edge triggered counter
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reg out_counter2; // negative edge triggered counter
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reg rst_pulse; // pulse generated when vector N changes
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reg rst_pulse; // pulse generated when vector N changes
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reg [`SIZE-1:0] old_N; // gets set to old N when N is changed
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reg [`SIZE-1:0] old_N; // gets set to old N when N is changed
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wire not_zero; // if !not_zero, we devide by 1
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wire not_zero; // if !not_zero, we devide by 1
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assign out = out_counter2 ^ out_counter; // xor to generate 50% duty, half-period
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assign out = out_counter2 ^ out_counter; // xor to generate 50% duty, half-period
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// waves of final output
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// waves of final output
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// positive edge counter/divider
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// positive edge counter/divider
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if(reset | rst_pulse)
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if(reset | rst_pulse)
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begin
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begin
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counter <= N;
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counter <= N;
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out_counter <= 1;
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out_counter <= 1;
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end
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end
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else if (enable)
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else if (enable)
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begin
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begin
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if(counter == 1)
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if(counter == 1)
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begin
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begin
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counter <= N;
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counter <= N;
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out_counter <= ~out_counter;
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out_counter <= ~out_counter;
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end
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end
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else
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else
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begin
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begin
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counter <= counter-1;
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counter <= counter - 1'b1;
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end
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end
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end
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end
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end
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end
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reg [`SIZE-1:0] initial_begin; // this is used to offset the negative edge counter
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reg [`SIZE-1:0] initial_begin; // this is used to offset the negative edge counter
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wire [`SIZE:0] interm_3; // from the positive edge counter in order to
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wire [`SIZE:0] interm_3; // from the positive edge counter in order to
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assign interm_3 = {1'b0,N} + 3; // guarante 50% duty cycle.
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assign interm_3 = {1'b0,N} + 2'b11; // guarante 50% duty cycle.
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// counter driven by negative edge of clock.
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// counter driven by negative edge of clock.
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always @(negedge clk)
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always @(negedge clk)
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begin
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begin
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if(reset | rst_pulse) // reset the counter at system reset
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if(reset | rst_pulse) // reset the counter at system reset
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begin // or change of N.
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begin // or change of N.
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counter2 <= N;
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counter2 <= N;
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initial_begin <= interm_3[`SIZE:1];
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initial_begin <= interm_3[`SIZE:1];
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out_counter2 <= 1;
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out_counter2 <= 1;
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end
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end
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else if(initial_begin <= 1 && enable) // Do normal logic after odd calibration.
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else if(initial_begin <= 1 && enable) // Do normal logic after odd calibration.
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begin // This is the same as the even counter.
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begin // This is the same as the even counter.
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if(counter2 == 1)
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if(counter2 == 1)
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begin
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begin
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counter2 <= N;
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counter2 <= N;
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out_counter2 <= ~out_counter2;
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out_counter2 <= ~out_counter2;
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end
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end
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else
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else
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begin
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begin
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counter2 <= counter2-1;
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counter2 <= counter2 - 1'b1;
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end
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end
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end
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end
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else if(enable)
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else if(enable)
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begin
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begin
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initial_begin <= initial_begin - 1;
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initial_begin <= initial_begin - 1'b1;
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end
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end
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end
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end
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//
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//
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// reset pulse generator:
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// reset pulse generator:
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// __ __ __ __ _
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// __ __ __ __ _
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// clk: __/ \__/ \__/ \__/ \__/
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// clk: __/ \__/ \__/ \__/ \__/
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// _ __________________________
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// _ __________________________
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// N: _X__________________________
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// N: _X__________________________
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// _____
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// _____
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// rst_pulse: __/ \___________________
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// rst_pulse: __/ \___________________
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//
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//
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// This block generates an internal reset for the odd divider in the
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// This block generates an internal reset for the odd divider in the
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// form of a single pulse signal when the odd divider is enabled.
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// form of a single pulse signal when the odd divider is enabled.
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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begin
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begin
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if(reset)
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if(reset)
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begin
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begin
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rst_pulse <= 0;
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rst_pulse <= 0;
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end
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end
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else if(enable)
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else if(enable)
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begin
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begin
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if(N != old_N) // pulse when reset changes
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if(N != old_N) // pulse when reset changes
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begin
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begin
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rst_pulse <= 1;
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rst_pulse <= 1;
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end
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end
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else
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else
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begin
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begin
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rst_pulse <= 0;
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rst_pulse <= 0;
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end
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end
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end
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end
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end
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always @(posedge clk)
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begin
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old_N <= N; // always save the old N value to guarante reset from
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old_N <= N; // always save the old N value to guarante reset from
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end // an even-to-odd transition.
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end // an even-to-odd transition.
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endmodule //odd
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endmodule //odd
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