|
|
|
|
|
|
|
|
|
|
|
|
Altera
|
Altera
|
ip.hwp.cpu
|
ip.hwp.cpu
|
nios_ii_sdram
|
nios_ii_sdram
|
1.0
|
1.0
|
Nios2 SDRAM subsystem.
|
Nios2 SDRAM subsystem.
|
|
|
|
|
clk
|
clk
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
CLK
|
CLK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
clk_0
|
clk_0
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
hibi_master
|
hibi_master
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
AV
|
AV
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_av_out_from_the_hibi_pe_dma_1
|
hibi_av_out_from_the_hibi_pe_dma_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
hibi_comm_out_from_the_hibi_pe_dma_1
|
hibi_comm_out_from_the_hibi_pe_dma_1
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
hibi_data_out_from_the_hibi_pe_dma_1
|
hibi_data_out_from_the_hibi_pe_dma_1
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
RE
|
RE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_re_out_from_the_hibi_pe_dma_1
|
hibi_re_out_from_the_hibi_pe_dma_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
WE
|
WE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_we_out_from_the_hibi_pe_dma_1
|
hibi_we_out_from_the_hibi_pe_dma_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
rst_n
|
rst_n
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
RESETn
|
RESETn
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
reset_n
|
reset_n
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
sdram_if
|
sdram_if
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
sdram_address_out
|
sdram_address_out
|
|
|
11
|
11
|
0
|
0
|
|
|
|
|
|
|
zs_addr_from_the_sdram_1
|
zs_addr_from_the_sdram_1
|
|
|
11
|
11
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_ba_out
|
sdram_ba_out
|
|
|
1
|
1
|
0
|
0
|
|
|
|
|
|
|
zs_ba_from_the_sdram_1
|
zs_ba_from_the_sdram_1
|
|
|
1
|
1
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_cas_n_out
|
sdram_cas_n_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
zs_cas_n_from_the_sdram_1
|
zs_cas_n_from_the_sdram_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_cke_out
|
sdram_cke_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
zs_cke_from_the_sdram_1
|
zs_cke_from_the_sdram_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_cs_n_out
|
sdram_cs_n_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
zs_cs_n_from_the_sdram_1
|
zs_cs_n_from_the_sdram_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_ras_n_out
|
sdram_ras_n_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
zs_ras_n_from_the_sdram_1
|
zs_ras_n_from_the_sdram_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_data_inout
|
sdram_data_inout
|
|
|
15
|
15
|
0
|
0
|
|
|
|
|
|
|
zs_dq_to_and_from_the_sdram_1
|
zs_dq_to_and_from_the_sdram_1
|
|
|
15
|
15
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_we_n_out
|
sdram_we_n_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
zs_we_n_from_the_sdram_1
|
zs_we_n_from_the_sdram_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
sdram_dqm_out
|
sdram_dqm_out
|
|
|
1
|
1
|
0
|
0
|
|
|
|
|
|
|
zs_dqm_from_the_sdram_1
|
zs_dqm_from_the_sdram_1
|
|
|
1
|
1
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
hibi_slave
|
hibi_slave
|
|
|
|
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
AV
|
AV
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_av_in_to_the_hibi_pe_dma_1
|
hibi_av_in_to_the_hibi_pe_dma_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
hibi_comm_in_to_the_hibi_pe_dma_1
|
hibi_comm_in_to_the_hibi_pe_dma_1
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
hibi_data_in_to_the_hibi_pe_dma_1
|
hibi_data_in_to_the_hibi_pe_dma_1
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
EMPTY
|
EMPTY
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_empty_in_to_the_hibi_pe_dma_1
|
hibi_empty_in_to_the_hibi_pe_dma_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
FULL
|
FULL
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_full_in_to_the_hibi_pe_dma_1
|
hibi_full_in_to_the_hibi_pe_dma_1
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
|
|
|
|
avalon_addr_space
|
avalon_addr_space
|
Avalon address space. (local)
|
Avalon address space. (local)
|
4G
|
4G
|
32
|
32
|
|
|
|
|
.bss
|
.bss
|
0x00800000
|
0x00800000
|
512
|
512
|
|
|
|
|
.exceptions
|
.exceptions
|
0x00800200
|
0x00800200
|
512
|
512
|
|
|
|
|
.entry
|
.entry
|
0x00800400
|
0x00800400
|
512
|
512
|
|
|
|
|
.stack
|
.stack
|
0x00800600
|
0x00800600
|
512
|
512
|
|
|
|
|
.heap
|
.heap
|
0x00800800
|
0x00800800
|
512
|
512
|
|
|
|
|
.rwdata
|
.rwdata
|
0x00800A00
|
0x00800A00
|
512
|
512
|
|
|
|
|
.text
|
.text
|
0x00800C00
|
0x00800C00
|
512
|
512
|
|
|
|
|
.rodata
|
.rodata
|
0x00800E00
|
0x00800E00
|
512
|
512
|
|
|
|
|
Shared_memory
|
Shared_memory
|
0x1000000
|
0x1000000
|
4K
|
4K
|
|
|
|
|
8
|
8
|
|
|
avalon_addr_space
|
avalon_addr_space
|
|
|
HIBI_PE_DMA
|
HIBI_PE_DMA
|
0x0
|
0x0
|
4
|
4
|
32
|
32
|
reserved
|
reserved
|
|
|
|
RX_INITIALIZE
|
|
Initializes the channel
|
|
0
|
|
0x0
|
|
32
|
|
false
|
|
write-only
|
|
|
|
|
|
CONTROL
|
|
Control register
|
|
0
|
|
0x1
|
|
32
|
|
false
|
|
read-write
|
|
|
|
|
|
IRQ_STATUS
|
|
Read IRQ status and acknoledge interrupts
|
|
0
|
|
0x2
|
|
32
|
|
false
|
|
read-write
|
|
|
|
|
|
TX_MEM_ADDR
|
|
Address where data to be sent begins
|
|
0
|
|
0x3
|
|
32
|
|
false
|
|
write-only
|
|
|
|
|
|
TX_WORDS
|
|
How many words to send
|
|
0
|
|
0x4
|
|
32
|
|
false
|
|
read-only
|
|
|
|
|
|
TX_COMM
|
|
Hibi command to send the data with
|
|
0
|
|
0x5
|
|
32
|
|
false
|
|
write-only
|
|
|
|
|
|
TX_HIBI_ADDR
|
|
Hibi address to send the data
|
|
0
|
|
0x6
|
|
32
|
|
false
|
|
write-only
|
|
|
|
|
|
RX_HIBI_DATA
|
|
Current data on hibi rx interface
|
|
0
|
|
0x7
|
|
32
|
|
false
|
|
read-only
|
|
|
|
|
|
RX_MEM_ADDR
|
|
Address where channel n stores received data
|
|
0
|
|
0x8
|
|
32
|
|
false
|
|
read-write
|
|
|
|
|
|
RX_WORDS
|
|
How many words to receive for packet channel n or read
|
|
0
|
|
0x9
|
|
32
|
|
read-write
|
|
|
|
|
|
RX_HIBI_ADDR
|
|
Hibi address for channel n to listen
|
|
0
|
|
0xA
|
|
32
|
|
false
|
|
read-write
|
|
|
|
|
|
|
JTAG_UART
|
JTAG_UART
|
0x4
|
0x4
|
4
|
4
|
32
|
32
|
reserved
|
reserved
|
|
|
|
|
TIMER
|
TIMER
|
0x8
|
0x8
|
4
|
4
|
32
|
32
|
reserved
|
reserved
|
|
|
|
|
SYSID
|
SYSID
|
0x10
|
0x10
|
4
|
4
|
32
|
32
|
reserved
|
reserved
|
|
|
|
|
ONCHIP_MEM
|
ONCHIP_MEM
|
0x1000000
|
0x1000000
|
4K
|
4K
|
32
|
32
|
memory
|
memory
|
|
|
|
|
SDRAM
|
SDRAM
|
0x00800000
|
0x00800000
|
8M
|
8M
|
32
|
32
|
memory
|
memory
|
|
|
|
|
|
|
|
|
hibi_addr_space
|
hibi_addr_space
|
HIBI address space
|
HIBI address space
|
4G
|
4G
|
32
|
32
|
8
|
8
|
|
|
|
|
|
|
|
|
hibi_mem_map
|
hibi_mem_map
|
|
|
|
hibi_addr_block
|
|
0x0
|
|
32
|
|
32
|
|
reserved
|
|
|
32
|
32
|
|
|
|
|
|
|
|
|
|
|
rtl
|
rtl
|
::
|
::
|
|
|
hdlSources
|
hdlSources
|
|
|
|
|
|
|
|
|
|
|
clk_0
|
clk_0
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_av_in_to_the_hibi_pe_dma_1
|
hibi_av_in_to_the_hibi_pe_dma_1
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
hibi_av_out_from_the_hibi_pe_dma_1
|
hibi_av_out_from_the_hibi_pe_dma_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
hibi_comm_in_to_the_hibi_pe_dma_1
|
hibi_comm_in_to_the_hibi_pe_dma_1
|
|
|
in
|
in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_comm_out_from_the_hibi_pe_dma_1
|
hibi_comm_out_from_the_hibi_pe_dma_1
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_data_in_to_the_hibi_pe_dma_1
|
hibi_data_in_to_the_hibi_pe_dma_1
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_data_out_from_the_hibi_pe_dma_1
|
hibi_data_out_from_the_hibi_pe_dma_1
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_empty_in_to_the_hibi_pe_dma_1
|
hibi_empty_in_to_the_hibi_pe_dma_1
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
hibi_full_in_to_the_hibi_pe_dma_1
|
hibi_full_in_to_the_hibi_pe_dma_1
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
hibi_re_out_from_the_hibi_pe_dma_1
|
hibi_re_out_from_the_hibi_pe_dma_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
hibi_we_out_from_the_hibi_pe_dma_1
|
hibi_we_out_from_the_hibi_pe_dma_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
reset_n
|
reset_n
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
zs_addr_from_the_sdram_1
|
zs_addr_from_the_sdram_1
|
|
|
out
|
out
|
|
|
11
|
11
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
zs_ba_from_the_sdram_1
|
zs_ba_from_the_sdram_1
|
|
|
out
|
out
|
|
|
1
|
1
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
zs_cas_n_from_the_sdram_1
|
zs_cas_n_from_the_sdram_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
zs_cke_from_the_sdram_1
|
zs_cke_from_the_sdram_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
zs_cs_n_from_the_sdram_1
|
zs_cs_n_from_the_sdram_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
zs_dq_to_and_from_the_sdram_1
|
zs_dq_to_and_from_the_sdram_1
|
|
|
inout
|
inout
|
|
|
15
|
15
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
zs_dqm_from_the_sdram_1
|
zs_dqm_from_the_sdram_1
|
|
|
out
|
out
|
|
|
1
|
1
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
zs_ras_n_from_the_sdram_1
|
zs_ras_n_from_the_sdram_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
zs_we_n_from_the_sdram_1
|
zs_we_n_from_the_sdram_1
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
hdlSources
|
hdlSources
|
|
|
../hdl/cpu_1.v
|
../hdl/cpu_1.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/cpu_1_jtag_debug_module_sysclk.v
|
../hdl/cpu_1_jtag_debug_module_sysclk.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/cpu_1_jtag_debug_module_tck.v
|
../hdl/cpu_1_jtag_debug_module_tck.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/cpu_1_jtag_debug_module_wrapper.v
|
../hdl/cpu_1_jtag_debug_module_wrapper.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/cpu_1_mult_cell.v
|
../hdl/cpu_1_mult_cell.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/cpu_1_oci_test_bench.v
|
../hdl/cpu_1_oci_test_bench.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/cpu_1_test_bench.v
|
../hdl/cpu_1_test_bench.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/hibi_pe_dma_1.vhd
|
../hdl/hibi_pe_dma_1.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../hdl/jtag_uart_1.v
|
../hdl/jtag_uart_1.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/nios_ii_sdram.qip
|
../hdl/nios_ii_sdram.qip
|
quartusIPFile
|
quartusIPFile
|
false
|
false
|
|
|
|
|
../hdl/nios_ii_sdram.v
|
../hdl/nios_ii_sdram.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/onchip_memory_1.v
|
../hdl/onchip_memory_1.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/sdram_1.v
|
../hdl/sdram_1.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
../hdl/timer_1.v
|
../hdl/timer_1.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
|
|
|
|
|
|
nios2
|
nios2
|
|
|
|
|
|
|
|
|
|
|
|
|
IP
|
IP
|
HW
|
HW
|
Fixed
|
Fixed
|
|
|
|
|
|
|
software
|
software
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
