|
|
|
|
|
|
|
|
|
|
|
|
TUT
|
TUT
|
ip.hwp.accelerator
|
ip.hwp.accelerator
|
dct_to_hibi
|
dct_to_hibi
|
1.0
|
1.0
|
DCT to Hibi. Connects dctQidct block to HIBI Wrapper
|
DCT to Hibi. Connects dctQidct block to HIBI Wrapper
|
|
|
Input:
|
Input:
|
1. Address to send the results to quant
|
1. Address to send the results to quant
|
2. Address to send the results to idct (set unused address if you don't use this)
|
2. Address to send the results to idct (set unused address if you don't use this)
|
2. Control word for the current macroblock
|
2. Control word for the current macroblock
|
Control word structure: bit 6: chroma(1)/luma(0) (NOT USED),
|
Control word structure: bit 6: chroma(1)/luma(0) NOT USED,
|
5: intra(1)/inter(0),
|
5: intra(1)/inter(0),
|
4..0: quantizer parameter (QP)
|
4..0: quantizer parameter (QP)
|
3. Then the DCT data ( 8x8x6 x 16-bit values = 384 x 16 bit )
|
3. Then the DCT data ( 8x8x6 x 16-bit values = 384 x 16 bit )
|
|
|
Only 9b DCT data values are supported currently.
|
Only 9b DCT data values are supported currently.
|
Send two DCT-values packed to upper and lower 16bits in the sigle hibi transmission.
|
Send two DCT-values packed to upper and lower 16bits in the sigle hibi transmission.
|
|
|
<31------------------16--------------------0> BIT index
|
<31------------------16--------------------0> BIT index
|
DCT_DATA_1 DCT_DATA_0 DATA
|
DCT_DATA_1 DCT_DATA_0 DATA
|
|
|
|
|
NOTE: If self release is used (use_self_rel_g=1) user gets the signal that dct_to_hibi is ready to receive data.
|
NOTE: If self release is used (use_self_rel_g=1) user gets the signal that dct_to_hibi is ready to receive data.
|
By default self release is disabled and you user can send data to dct_to_hibi after quant results are received.
|
By default self release is disabled and you user can send data to dct_to_hibi after quant results are received.
|
|
|
|
|
Outputs:
|
Outputs:
|
Outputs are 16-bit words which are packed up to hibi. If hibi width is
|
Outputs are 16-bit words which are packed up to hibi. If hibi width is
|
32b, then 2 16-bit words are combined into one hibi word.
|
32b, then 2 16-bit words are combined into one hibi word.
|
01. quant results: 1. 8*8 x 16bit values to quant result address
|
01. quant results: 1. 8*8 x 16bit values to quant result address
|
02. idct results: 1. 8*8 x 16bit values to idct result address
|
02. idct results: 1. 8*8 x 16bit values to idct result address
|
03. quant results: 2. 8*8 x 16bit values to quant result address
|
03. quant results: 2. 8*8 x 16bit values to quant result address
|
04. idct results: 2. 8*8 x 16bit values to idct result address
|
04. idct results: 2. 8*8 x 16bit values to idct result address
|
05. quant results: 3. 8*8 x 16bit values to quant result address
|
05. quant results: 3. 8*8 x 16bit values to quant result address
|
06. idct results: 3. 8*8 x 16bit values to idct result address
|
06. idct results: 3. 8*8 x 16bit values to idct result address
|
07. quant results: 4. 8*8 x 16bit values to quant result address
|
07. quant results: 4. 8*8 x 16bit values to quant result address
|
08. idct results: 4. 8*8 x 16bit values to idct result address
|
08. idct results: 4. 8*8 x 16bit values to idct result address
|
09. quant results: 5. 8*8 x 16bit values to quant result address
|
09. quant results: 5. 8*8 x 16bit values to quant result address
|
10. idct results: 5. 8*8 x 16bit values to idct result address
|
10. idct results: 5. 8*8 x 16bit values to idct result address
|
11. quant results: 6. 8*8 x 16bit values to quant result address
|
11. quant results: 6. 8*8 x 16bit values to quant result address
|
12. quant results: 1 word with bits 5..0 determing if 8x8 quant blocks(1-6)
|
12. quant results: 1 word with bits 5..0 determing if 8x8 quant blocks(1-6)
|
has all values zeros (except dc-component in intra)
|
has all values zeros (except dc-component in intra)
|
13. idct results: 6. 8*8 x 16bit values to idct result address
|
13. idct results: 6. 8*8 x 16bit values to idct result address
|
-
|
-
|
Total amount of 16-bit values is: 384 per result address + 1 hibi word to
|
Total amount of 16-bit values is: 384 per result address + 1 hibi word to
|
quantization result address.
|
quantization result address.
|
|
|
With default parameter:
|
With default parameter:
|
Total of 193 words of data to quant address (if data_width_g = 32)
|
Total of 193 words of data to quant address (if data_width_g = 32)
|
Total of 192 words of data to idct address (if data_width_g = 32)
|
Total of 192 words of data to idct address (if data_width_g = 32)
|
|
|
|
|
|
|
clk
|
clk
|
Clock interface
|
Clock interface
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
CLK
|
CLK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
clk
|
clk
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
dct_if
|
dct_if
|
Interface for connecting idctquant accelerator
|
Interface for connecting idctquant accelerator
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
CHROMA_TO_ACC
|
CHROMA_TO_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
chroma_out
|
chroma_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DCT_READY4COL_FROM_ACC
|
DCT_READY4COL_FROM_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
dct_ready4col_in
|
dct_ready4col_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
IDCT_READY4COL_TO_ACC
|
IDCT_READY4COL_TO_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
idct_ready4col_out
|
idct_ready4col_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
INTRA_TO_ACC
|
INTRA_TO_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
intra_out
|
intra_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
LOAD_QP_TO_ACC
|
LOAD_QP_TO_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
loadQP_out
|
loadQP_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
QP_TO_ACC
|
QP_TO_ACC
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
QP_out
|
QP_out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
WR_DCT_TO_ACC
|
WR_DCT_TO_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
wr_dct_out
|
wr_dct_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
WR_IDCT_FROM_ACC
|
WR_IDCT_FROM_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
wr_idct_in
|
wr_idct_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
WR_QUANT_FROM_ACC
|
WR_QUANT_FROM_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
wr_quant_in
|
wr_quant_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
QUANT_READY4COL_TO_ACC
|
QUANT_READY4COL_TO_ACC
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
quant_ready4col_out
|
quant_ready4col_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA_DCT_TO_ACC
|
DATA_DCT_TO_ACC
|
|
|
8
|
8
|
0
|
0
|
|
|
|
|
|
|
data_dct_out
|
data_dct_out
|
|
|
8
|
8
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA_IDCT_FROM_ACC
|
DATA_IDCT_FROM_ACC
|
|
|
8
|
8
|
0
|
0
|
|
|
|
|
|
|
data_idct_in
|
data_idct_in
|
|
|
8
|
8
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA_QUANT_FROM_ACC
|
DATA_QUANT_FROM_ACC
|
|
|
7
|
7
|
0
|
0
|
|
|
|
|
|
|
data_quant_in
|
data_quant_in
|
|
|
7
|
7
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
hibi_master
|
hibi_master
|
HIBI wrapper r4 version 2 master interface
|
HIBI wrapper r4 version 2 master interface
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
AV
|
AV
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_av_out
|
hibi_av_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
hibi_comm_out
|
hibi_comm_out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
hibi_data_out
|
hibi_data_out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
RE
|
RE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_re_out
|
hibi_re_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
WE
|
WE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_we_out
|
hibi_we_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
rst_n
|
rst_n
|
Active low reset input.
|
Active low reset input.
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
RESETn
|
RESETn
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
rst_n
|
rst_n
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
hibi_slave
|
hibi_slave
|
|
|
|
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
AV
|
AV
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_av_in
|
hibi_av_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
hibi_comm_in
|
hibi_comm_in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
hibi_data_in
|
hibi_data_in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
EMPTY
|
EMPTY
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_empty_in
|
hibi_empty_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
FULL
|
FULL
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
hibi_full_in
|
hibi_full_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
|
|
|
|
dct_mem_map
|
dct_mem_map
|
|
|
dct_regs
|
dct_regs
|
0x0
|
0x0
|
1
|
7
|
32
|
32
|
register
|
register
|
|
|
quant_result_addr
|
quant_result_addr
|
0
|
0
|
0x0
|
0x0
|
32
|
32
|
|
|
|
|
idct_result_addr
|
idct_result_addr
|
0
|
0
|
0x1
|
0x1
|
32
|
32
|
|
|
|
|
ctrl_reg
|
ctrl_reg
|
0
|
0
|
0x2
|
0x2
|
32
|
32
|
|
|
QP
|
QP
|
Quant parameter
|
Quant parameter
|
0
|
0
|
5
|
5
|
false
|
false
|
true
|
true
|
|
|
|
|
intra_or_inter
|
intra_or_inter
|
0=intra, 1=inter
|
0=intra, 1=inter
|
5
|
5
|
1
|
1
|
false
|
false
|
true
|
true
|
|
|
|
|
chroma_luma
|
chroma_luma
|
0=luma, 1=chroma
|
0=luma, 1=chroma
|
6
|
6
|
1
|
1
|
false
|
false
|
true
|
true
|
|
|
|
|
|
|
dct_data
|
dct_data
|
0
|
0
|
0x3
|
0x3
|
32
|
32
|
|
|
|
|
8
|
32
|
|
|
|
|
|
|
|
|
|
|
rtl
|
rtl
|
vhdl:quartus, modelsim:
|
vhdl:quartus, modelsim:
|
dct_to_hibi
|
dct_to_hibi
|
|
|
hdlSources
|
hdlSources
|
|
|
|
|
|
|
|
|
|
|
QP_out
|
QP_out
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
chroma_out
|
chroma_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
clk
|
clk
|
|
|
in
|
in
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
data_dct_out
|
data_dct_out
|
|
|
out
|
out
|
|
|
8
|
8
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
data_idct_in
|
data_idct_in
|
|
|
in
|
in
|
|
|
8
|
8
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
data_quant_in
|
data_quant_in
|
|
|
in
|
in
|
|
|
7
|
7
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
dct_ready4col_in
|
dct_ready4col_in
|
|
|
in
|
in
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
debug_out
|
debug_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_av_in
|
hibi_av_in
|
|
|
in
|
in
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
hibi_av_out
|
hibi_av_out
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
hibi_comm_in
|
hibi_comm_in
|
|
|
in
|
in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
hibi_comm_out
|
hibi_comm_out
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_data_in
|
hibi_data_in
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
hibi_data_out
|
hibi_data_out
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_empty_in
|
hibi_empty_in
|
|
|
in
|
in
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
hibi_full_in
|
hibi_full_in
|
|
|
in
|
in
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
hibi_re_out
|
hibi_re_out
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
hibi_we_out
|
hibi_we_out
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
idct_ready4col_out
|
idct_ready4col_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
intra_out
|
intra_out
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
loadQP_out
|
loadQP_out
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
quant_ready4col_out
|
quant_ready4col_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
rst_n
|
rst_n
|
|
|
in
|
in
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
wr_dct_out
|
wr_dct_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
wr_idct_in
|
wr_idct_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
wr_quant_in
|
wr_quant_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
comm_width_g
|
comm_width_g
|
5
|
5
|
|
|
|
|
data_width_g
|
data_width_g
|
32
|
32
|
|
|
|
|
dct_width_g
|
dct_width_g
|
Incoming data width(9b)
|
Incoming data width(9b)
|
9
|
9
|
|
|
|
|
debug_w_g
|
debug_w_g
|
1
|
1
|
|
|
|
|
idct_width_g
|
idct_width_g
|
Data width after IDCT(9b)
|
Data width after IDCT(9b)
|
9
|
9
|
|
|
|
|
own_address_g
|
own_address_g
|
Used for self-release
|
Used for self-release
|
0
|
0
|
|
|
|
|
quant_width_g
|
quant_width_g
|
Quantizated data width(8b)
|
Quantizated data width(8b)
|
8
|
8
|
|
|
|
|
rtm_address_g
|
rtm_address_g
|
Used for self-release
|
Used for self-release
|
0
|
0
|
|
|
|
|
use_self_rel_g
|
use_self_rel_g
|
Does it release itself from RTM?
|
Does it release itself from RTM?
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hdlSources
|
hdlSources
|
|
|
hdl/cl_cnt.vhd
|
hdl/cl_cnt.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
dct_to_hibi
|
dct_to_hibi
|
|
|
|
|
hdl/dct_to_hibi_v2.vhd
|
hdl/dct_to_hibi_v2.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
dct_to_hibi
|
dct_to_hibi
|
|
|
|
|
../../dctqidct/1.0/hdl/dctQidct/IDCT_fifo.vhd
|
../../dctqidct/1.0/hdl/dctQidct/IDCT_fifo.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
dct_to_hibi
|
dct_to_hibi
|
|
|
|
|
|
|
Documentation
|
Documentation
|
|
|
doc/dct_to_hibi_ports.csv
|
doc/dct_to_hibi_ports.csv
|
csvFile
|
csvFile
|
false
|
false
|
|
|
|
|
|
|
|
|
|
|
|
|
IP
|
IP
|
HW
|
HW
|
Mutable
|
Mutable
|
|
|
|
|
|
|
dct_data_in
|
dct_data_in
|
|
|
|
|
|
|
packet
|
packet
|
in
|
in
|
|
|
|
|
|
|
|
|
dct_data_out
|
dct_data_out
|
|
|
|
|
|
|
packet
|
packet
|
out
|
out
|
|
|
|
|
|
|
|
|
block_count_in
|
block_count_in
|
|
|
|
|
|
|
message
|
message
|
in
|
in
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
