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TUT
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TUT
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ip.hwp.communication
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ip.hwp.communication
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basic_tester_tx
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basic_tester_tx
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1.0
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1.0
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Simple unit for sending test data. There are separate units for transmitting (tx) and receiving (rx). This one sends commands to the tested IP (e.g. via HIBI). The other unit can then check the returned data.
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Simple unit for sending test data. There are separate units for transmitting (tx) and receiving (rx). This one sends commands to the tested IP (e.g. via HIBI). The other unit can then check the returned data.
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This IP-XACT component is fixed to 32-bit data and 5-bit command.
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This IP-XACT component is fixed to 32-bit data and 5-bit command.
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Works only in simulation because configuration is done with ASCII file.
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Works only in simulation because configuration is done with ASCII file.
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clock
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clock
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false
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false
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CLK
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CLK
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0
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0
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0
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0
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clk
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clk
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0
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0
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0
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0
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8
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8
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little
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little
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hibi_master
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hibi_master
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Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.
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Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.
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false
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false
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COMM
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COMM
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4
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4
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0
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0
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agent_comm_out
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agent_comm_out
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4
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4
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0
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0
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DATA
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DATA
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31
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31
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0
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0
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agent_data_out
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agent_data_out
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31
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31
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0
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0
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WE
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WE
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0
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0
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0
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0
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agent_we_out
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agent_we_out
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0
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0
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0
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0
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AV
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AV
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0
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0
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0
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0
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agent_av_out
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agent_av_out
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0
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0
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0
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0
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8
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8
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little
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little
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hibi_slave
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hibi_slave
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false
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false
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ONE_P
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ONE_P
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0
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0
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0
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0
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agent_one_p_in
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agent_one_p_in
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0
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0
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0
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0
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FULL
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FULL
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0
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0
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0
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0
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agent_full_in
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agent_full_in
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0
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0
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0
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0
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8
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8
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little
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little
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reset
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reset
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false
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false
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RESETn
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RESETn
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0
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0
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0
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0
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rst_n
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rst_n
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0
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0
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0
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0
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8
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8
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little
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little
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rtl
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rtl
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VHDL::
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VHDL::
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rtl
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rtl
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agent_av_out
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agent_av_out
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out
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out
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agent_comm_out
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agent_comm_out
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out
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out
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4
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4
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0
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0
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agent_data_out
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agent_data_out
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out
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out
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31
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31
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0
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0
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agent_full_in
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agent_full_in
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in
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in
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agent_one_p_in
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agent_one_p_in
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in
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in
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agent_we_out
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agent_we_out
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out
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out
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clk
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clk
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in
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in
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done_out
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done_out
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out
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out
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rst_n
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rst_n
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Active low
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Active low
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in
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in
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comm_width_g
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comm_width_g
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5
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5
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conf_file_g
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conf_file_g
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File that contains the sent data
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File that contains the sent data
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test_tx.txt
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test_tx.txt
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data_width_g
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data_width_g
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32
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32
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rtl
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rtl
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VHDL sources
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VHDL sources
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../vhd/txt_util.vhd
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../vhd/txt_util.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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../vhd/basic_tester_pkg.vhd
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../vhd/basic_tester_pkg.vhd
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vhdlSource
|
vhdlSource
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false
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false
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work
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work
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false
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../vhd/basic_tester_tx.vhd
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../vhd/basic_tester_tx.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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vhdlSource
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vhdlSource
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vcom
|
vcom
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-check_synthesis
|
-check_synthesis
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false
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false
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example_usage
|
example_usage
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Instantiates tx, rx and 2 hibi wrappers. Tx sends few values. Rx catches them and checks their contents and reception times.
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Instantiates tx, rx and 2 hibi wrappers. Tx sends few values. Rx catches them and checks their contents and reception times.
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../tb/tb_basic_tester.vhd
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../tb/tb_basic_tester.vhd
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vhdlSource
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vhdlSource
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false
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false
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work
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work
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false
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Top-level. Generates clock and reset, instantiates basic tester tx+rx and hibi wrappers.
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Top-level. Generates clock and reset, instantiates basic tester tx+rx and hibi wrappers.
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../vhd/basic_tester_rx.vhd
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../vhd/basic_tester_rx.vhd
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vhdlSource
|
vhdlSource
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false
|
false
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work
|
work
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false
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Receiver unit.
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Receiver unit.
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../sim/test_tx.txt
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../sim/test_tx.txt
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ASCII
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ASCII
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false
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false
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false
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Contents of transmitted values
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Contents of transmitted values
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../sim/compile_all.sh
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../sim/compile_all.sh
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shell script
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shell script
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false
|
false
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false
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Creates VHDL libraries and compiles everything.
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Creates VHDL libraries and compiles everything.
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../sim/tb_basic_tester.do
|
../sim/tb_basic_tester.do
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Modelsim macro
|
Modelsim macro
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false
|
false
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false
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Sets up the wave viewer
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Sets up the wave viewer
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../sim/test_rx.txt
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../sim/test_rx.txt
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ASCII
|
ASCII
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false
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false
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false
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Expected values for the receiver
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Expected values for the receiver
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vhdlSource
|
vhdlSource
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vcom
|
vcom
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-check_synthesis
|
-check_synthesis
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false
|
false
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../../../../ip.hwp.storage/fifos
|
../../../../ip.hwp.storage/fifos
|
../../../../ip.hwp.storage/fifos/multi_clk/vhd
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd
|
../../../hibi/3.0/vhd
|
../../../hibi/3.0/vhd
|
|
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IP
|
IP
|
HW
|
HW
|
Fixed
|
Fixed
|
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