/*
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/*
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*This file is part of fpga_gpib_controller.
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*
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* Fpga_gpib_controller is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Fpga_gpib_controller is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* GpibHwAdapter.h
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* GpibHwAdapter.h
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*
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*
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* Created on: 2012-01-29
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* Created on: 2012-01-29
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* Author: Andrzej Paluch
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* Author: Andrzej Paluch
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*/
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*/
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#ifndef __GPIB_HW_ADAPTER_H__
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#ifndef __GPIB_HW_ADAPTER_H__
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#define __GPIB_HW_ADAPTER_H__
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#define __GPIB_HW_ADAPTER_H__
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#include "GpibTypes.h"
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#include "GpibTypes.h"
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#include "GpibRegAccess.h"
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#include "GpibRegAccess.h"
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/** Register addresses */
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/** Register addresses */
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#define REG_ADDR_SETTING_0 0
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#define REG_ADDR_SETTING_0 0
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#define REG_ADDR_SETTING_1 1
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#define REG_ADDR_SETTING_1 1
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#define REG_ADDR_SEC_ADDR_0 2
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#define REG_ADDR_SEC_ADDR_0 2
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#define REG_ADDR_SEC_ADDR_1 3
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#define REG_ADDR_SEC_ADDR_1 3
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#define REG_ADDR_BUS_STATUS 4
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#define REG_ADDR_BUS_STATUS 4
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#define REG_ADDR_EVENT 5
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#define REG_ADDR_EVENT 5
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#define REG_ADDR_GPIB_STATUS 6
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#define REG_ADDR_GPIB_STATUS 6
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#define REG_ADDR_CONTROL 7
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#define REG_ADDR_CONTROL 7
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#define REG_ADDR_READER_CONTROL_0 8
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#define REG_ADDR_READER_CONTROL_0 8
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#define REG_ADDR_READER_CONTROL_1 9
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#define REG_ADDR_READER_CONTROL_1 9
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#define REG_ADDR_WRITER_CONTROL_0 10
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#define REG_ADDR_WRITER_CONTROL_0 10
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#define REG_ADDR_WRITER_CONTROL_1 11
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#define REG_ADDR_WRITER_CONTROL_1 11
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#define REG_ADDR_READER_FIFO 12
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#define REG_ADDR_READER_FIFO 12
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#define REG_ADDR_WRITER_FIFO 13
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#define REG_ADDR_WRITER_FIFO 13
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/* Setting 0 register masks. */
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/* Setting 0 register masks. */
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#define MASK_SETTING0_ton 0x8000
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#define MASK_SETTING0_ton 0x8000
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#define MASK_SETTING0_lon 0x4000
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#define MASK_SETTING0_lon 0x4000
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#define MASK_SETTING0_eosMark 6,0xFF
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#define MASK_SETTING0_eosMark 6,0xFF
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#define MASK_SETTING0_eosUsed 0x0020
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#define MASK_SETTING0_eosUsed 0x0020
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#define MASK_SETTING0_fixedPpLine 2,0x7
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#define MASK_SETTING0_fixedPpLine 2,0x7
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#define MASK_SETTING0_lpeUsed 0x0002
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#define MASK_SETTING0_lpeUsed 0x0002
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#define MASK_SETTING0_isLeTe 0x0001
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#define MASK_SETTING0_isLeTe 0x0001
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/* Setting 1 register masks. */
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/* Setting 1 register masks. */
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#define MASK_SETTING1_T1 5,0xFF
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#define MASK_SETTING1_T1 5,0xFF
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#define MASK_SETTING1_addr 0,0x1F
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#define MASK_SETTING1_addr 0,0x1F
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/* Secondary address register masks. */
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/* Secondary address register masks. */
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// nothing to define
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// nothing to define
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/* Bus status register masks. */
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/* Bus status register masks. */
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#define MASK_BUS_STATUS_REN 0x8000
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#define MASK_BUS_STATUS_REN 0x8000
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#define MASK_BUS_STATUS_IFC 0x4000
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#define MASK_BUS_STATUS_IFC 0x4000
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#define MASK_BUS_STATUS_SRQ 0x2000
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#define MASK_BUS_STATUS_SRQ 0x2000
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#define MASK_BUS_STATUS_EOI 0x1000
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#define MASK_BUS_STATUS_EOI 0x1000
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#define MASK_BUS_STATUS_NDAC 0x0800
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#define MASK_BUS_STATUS_NDAC 0x0800
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#define MASK_BUS_STATUS_NRFD 0x0400
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#define MASK_BUS_STATUS_NRFD 0x0400
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#define MASK_BUS_STATUS_DAV 0x0200
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#define MASK_BUS_STATUS_DAV 0x0200
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#define MASK_BUS_STATUS_ATN 0x0100
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#define MASK_BUS_STATUS_ATN 0x0100
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#define MASK_BUS_STATUS_DIO 0,0xFF
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#define MASK_BUS_STATUS_DIO 0,0xFF
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/* Event register masks. */
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/* Event register masks. */
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#define MASK_EVENT_IFC 0x8000
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#define MASK_EVENT_IFC 0x8000
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#define MASK_EVENT_ATN 0x4000
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#define MASK_EVENT_ATN 0x4000
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#define MASK_EVENT_REN 0x2000
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#define MASK_EVENT_REN 0x2000
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#define MASK_EVENT_stb_received 0x1000
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#define MASK_EVENT_stb_received 0x1000
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#define MASK_EVENT_ppr 0x0800
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#define MASK_EVENT_ppr 0x0800
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#define MASK_EVENT_srq 0x0400
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#define MASK_EVENT_srq 0x0400
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#define MASK_EVENT_cwrd 0x0200
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#define MASK_EVENT_cwrd 0x0200
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#define MASK_EVENT_cwrc 0x0100
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#define MASK_EVENT_cwrc 0x0100
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#define MASK_EVENT_spa 0x0080
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#define MASK_EVENT_spa 0x0080
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#define MASK_EVENT_atl 0x0040
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#define MASK_EVENT_atl 0x0040
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#define MASK_EVENT_att 0x0020
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#define MASK_EVENT_att 0x0020
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#define MASK_EVENT_trg 0x0010
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#define MASK_EVENT_trg 0x0010
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#define MASK_EVENT_clr 0x0008
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#define MASK_EVENT_clr 0x0008
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#define MASK_EVENT_out_buf_full 0x0004
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#define MASK_EVENT_out_buf_full 0x0004
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#define MASK_EVENT_in_buf_full 0x0002
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#define MASK_EVENT_in_buf_full 0x0002
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#define MASK_EVENT_isLocal 0x0001
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#define MASK_EVENT_isLocal 0x0001
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/* GPIB status register masks. */
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/* GPIB status register masks. */
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#define MASK_GPIB_STATUS_isLocal 0x1000
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#define MASK_GPIB_STATUS_isLocal 0x1000
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#define MASK_GPIB_STATUS_spa 0x0800
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#define MASK_GPIB_STATUS_spa 0x0800
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#define MASK_GPIB_STATUS_cwrd 0x0400
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#define MASK_GPIB_STATUS_cwrd 0x0400
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#define MASK_GPIB_STATUS_cwrc 0x0200
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#define MASK_GPIB_STATUS_cwrc 0x0200
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#define MASK_GPIB_STATUS_lac 0x0100
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#define MASK_GPIB_STATUS_lac 0x0100
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#define MASK_GPIB_STATUS_atl 0x0080
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#define MASK_GPIB_STATUS_atl 0x0080
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#define MASK_GPIB_STATUS_tac 0x0040
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#define MASK_GPIB_STATUS_tac 0x0040
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#define MASK_GPIB_STATUS_att 0x0020
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#define MASK_GPIB_STATUS_att 0x0020
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#define MASK_GPIB_STATUS_currentSecAddr 0,0x1F
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#define MASK_GPIB_STATUS_currentSecAddr 0,0x1F
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/* Control register masks. */
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/* Control register masks. */
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#define MASK_CONTROL_rec_stb 0x2000
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#define MASK_CONTROL_rec_stb 0x2000
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#define MASK_CONTROL_rpp 0x1000
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#define MASK_CONTROL_rpp 0x1000
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#define MASK_CONTROL_tca 0x0800
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#define MASK_CONTROL_tca 0x0800
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#define MASK_CONTROL_tcs 0x0400
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#define MASK_CONTROL_tcs 0x0400
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#define MASK_CONTROL_gts 0x0200
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#define MASK_CONTROL_gts 0x0200
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#define MASK_CONTROL_sre 0x0100
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#define MASK_CONTROL_sre 0x0100
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#define MASK_CONTROL_sic 0x0080
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#define MASK_CONTROL_sic 0x0080
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#define MASK_CONTROL_rsc 0x0040
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#define MASK_CONTROL_rsc 0x0040
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#define MASK_CONTROL_lpe 0x0020
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#define MASK_CONTROL_lpe 0x0020
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#define MASK_CONTROL_ist 0x0010
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#define MASK_CONTROL_ist 0x0010
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#define MASK_CONTROL_rsv 0x0008
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#define MASK_CONTROL_rsv 0x0008
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#define MASK_CONTROL_rtl 0x0004
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#define MASK_CONTROL_rtl 0x0004
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#define MASK_CONTROL_lun 0x0002
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#define MASK_CONTROL_lun 0x0002
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#define MASK_CONTROL_ltn 0x0001
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#define MASK_CONTROL_ltn 0x0001
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/* Reader control 0 register masks. */
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/* Reader control 0 register masks. */
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#define MASK_READER_CONTROL_0_dataSecAddr 4,0x1F
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#define MASK_READER_CONTROL_0_dataSecAddr 4,0x1F
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#define MASK_READER_CONTROL_0_resetBuffer 0x0008
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#define MASK_READER_CONTROL_0_resetBuffer 0x0008
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#define MASK_READER_CONTROL_0_endOfStream 0x0004
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#define MASK_READER_CONTROL_0_endOfStream 0x0004
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#define MASK_READER_CONTROL_0_dataAvailable 0x0002
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#define MASK_READER_CONTROL_0_dataAvailable 0x0002
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#define MASK_READER_CONTROL_0_bufInterrupt 0x0001
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#define MASK_READER_CONTROL_0_bufInterrupt 0x0001
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/* Reader control 1 register masks. */
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/* Reader control 1 register masks. */
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#define MASK_READER_CONTROL_1_bytesInFifo 0,0xFFF
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#define MASK_READER_CONTROL_1_bytesInFifo 0,0xFFF
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/* Writer control 0 register masks. */
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/* Writer control 0 register masks. */
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#define MASK_WRITER_CONTROL_0_statusByte 9,0x7F
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#define MASK_WRITER_CONTROL_0_statusByte 9,0x7F
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#define MASK_WRITER_CONTROL_0_dataSecAddr 4,0x1F
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#define MASK_WRITER_CONTROL_0_dataSecAddr 4,0x1F
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#define MASK_WRITER_CONTROL_0_resetBuffer 0x0008
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#define MASK_WRITER_CONTROL_0_resetBuffer 0x0008
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#define MASK_WRITER_CONTROL_0_endOfStream 0x0004
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#define MASK_WRITER_CONTROL_0_endOfStream 0x0004
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#define MASK_WRITER_CONTROL_0_dataAvailable 0x0002
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#define MASK_WRITER_CONTROL_0_dataAvailable 0x0002
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#define MASK_WRITER_CONTROL_0_bufInterrupt 0x0001
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#define MASK_WRITER_CONTROL_0_bufInterrupt 0x0001
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/* Writer control 1 register masks. */
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/* Writer control 1 register masks. */
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#define MASK_WRITER_CONTROL_1_bytesInFifo 0,0xFFF
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#define MASK_WRITER_CONTROL_1_bytesInFifo 0,0xFFF
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/** Encapsulates GPIB hardware adapter issues. */
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/** Encapsulates GPIB hardware adapter issues. */
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struct GpibHwAdapter
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struct GpibHwAdapter
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{
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{
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struct GpibRegAccess *regAccess;
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struct GpibRegAccess *regAccess;
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AddrType baseAddr;
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AddrType baseAddr;
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};
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};
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///////////// do not use //////////////////////////
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///////////// do not use //////////////////////////
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#define __GpibHwAdapter_getValue(reg, bitNum, valueMask)\
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#define __GpibHwAdapter_getValue(reg, bitNum, valueMask)\
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((reg >> bitNum) & valueMask)
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((reg >> bitNum) & valueMask)
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#define __GpibHwAdapter_setValue(pReg, bitNum, valueMask, value)\
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#define __GpibHwAdapter_setValue(pReg, bitNum, valueMask, value)\
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*pReg &= ( ~(valueMask << bitNum) ) & 0xFFFF;\
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*pReg &= ( ~(valueMask << bitNum) ) & 0xFFFF;\
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*pReg |= ((value) << bitNum) & (valueMask << bitNum);
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*pReg |= ((value) << bitNum) & (valueMask << bitNum);
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///////////// end of - do not use //////////////////
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///////////// end of - do not use //////////////////
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/** Initializes GpibHwAdapter */
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/** Initializes GpibHwAdapter */
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bool GpibHwAdapter_init(struct GpibHwAdapter *ghwa, struct GpibRegAccess *regAccess,
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bool GpibHwAdapter_init(struct GpibHwAdapter *ghwa, struct GpibRegAccess *regAccess,
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AddrType baseAddr);
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AddrType baseAddr);
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/** Releases GpibHwAdapter. */
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/** Releases GpibHwAdapter. */
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void GpibHwAdapter_release(struct GpibHwAdapter *ghwa);
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void GpibHwAdapter_release(struct GpibHwAdapter *ghwa);
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/** Gets register value. */
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/** Gets register value. */
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#define GpibHwAdapter_getReg(ghwa, regAddr, pvalue)\
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#define GpibHwAdapter_getReg(ghwa, regAddr, pvalue)\
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GpibRegAccess_readReg((ghwa)->regAccess,\
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GpibRegAccess_readReg((ghwa)->regAccess,\
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(ghwa)->baseAddr + regAddr, pvalue)
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(ghwa)->baseAddr + regAddr, pvalue)
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/** Sets register value. */
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/** Sets register value. */
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#define GpibHwAdapter_setReg(ghwa, regAddr, value)\
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#define GpibHwAdapter_setReg(ghwa, regAddr, value)\
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GpibRegAccess_writeReg((ghwa)->regAccess,\
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GpibRegAccess_writeReg((ghwa)->regAccess,\
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(ghwa)->baseAddr + regAddr, value)
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(ghwa)->baseAddr + regAddr, value)
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/** Reads data fifo. */
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/** Reads data fifo. */
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#define GpibHwAdapter_readFifo(ghwa, buf, bufLen)\
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#define GpibHwAdapter_readFifo(ghwa, buf, bufLen)\
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GpibRegAccess_repeatedlyRead((ghwa)->regAccess,\
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GpibRegAccess_repeatedlyRead((ghwa)->regAccess,\
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(ghwa)->baseAddr + REG_ADDR_READER_FIFO, buf, bufLen)
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(ghwa)->baseAddr + REG_ADDR_READER_FIFO, buf, bufLen)
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/** Writes to data fifo. */
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/** Writes to data fifo. */
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#define GpibHwAdapter_writeFifo(ghwa, buf, bufLen)\
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#define GpibHwAdapter_writeFifo(ghwa, buf, bufLen)\
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GpibRegAccess_repeatedlyWrite((ghwa)->regAccess,\
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GpibRegAccess_repeatedlyWrite((ghwa)->regAccess,\
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(ghwa)->baseAddr + REG_ADDR_WRITER_FIFO, buf, bufLen)
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(ghwa)->baseAddr + REG_ADDR_WRITER_FIFO, buf, bufLen)
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/** Gets register value's bit. */
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/** Gets register value's bit. */
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#define GpibHwAdapter_getBitValue(reg, mask) ((reg & mask) != 0)
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#define GpibHwAdapter_getBitValue(reg, mask) ((reg & mask) != 0)
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/** Sets register value's bit. */
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/** Sets register value's bit. */
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#define GpibHwAdapter_setBitValue(pReg, mask, newValue)\
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#define GpibHwAdapter_setBitValue(pReg, mask, newValue)\
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if(newValue == 0) {\
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if(newValue == 0) {\
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*pReg &= ( ~(mask) ) & 0xFFFF;\
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*pReg &= ( ~(mask) ) & 0xFFFF;\
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} else {\
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} else {\
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*pReg |= mask;\
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*pReg |= mask;\
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}
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}
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/** Gets register value's field. */
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/** Gets register value's field. */
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#define GpibHwAdapter_getFieldValue(reg, bitNumAndMask)\
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#define GpibHwAdapter_getFieldValue(reg, bitNumAndMask)\
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__GpibHwAdapter_getValue(reg, bitNumAndMask)
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__GpibHwAdapter_getValue(reg, bitNumAndMask)
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/** Sets register value's field. */
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/** Sets register value's field. */
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#define GpibHwAdapter_setFieldValue(pReg, bitNumAndMask, newValue)\
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#define GpibHwAdapter_setFieldValue(pReg, bitNumAndMask, newValue)\
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__GpibHwAdapter_setValue(pReg, bitNumAndMask, newValue)
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__GpibHwAdapter_setValue(pReg, bitNumAndMask, newValue)
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#endif /* __GPIB_HW_ADAPTER_H__ */
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#endif /* __GPIB_HW_ADAPTER_H__ */
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