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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Author: Andrzej Paluch
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-- Engineer:
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--
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--
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-- Create Date: 22:17:28 01/24/2012
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-- Create Date: 22:17:28 01/24/2012
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-- Design Name:
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-- Design Name:
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-- Module Name: main - Behavioral
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-- Module Name: main - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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use work.communication.ALL;
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use work.communication.ALL;
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use work.wrapperComponents.ALL;
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use work.wrapperComponents.ALL;
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use work.helperComponents.ALL;
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use work.helperComponents.ALL;
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entity main is
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entity main is
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port(
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port(
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--reset : in std_logic;
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--reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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------ UART ---------
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------ UART ---------
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RX : in std_logic;
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RX : in std_logic;
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TX : out std_logic;
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TX : out std_logic;
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------ GPIB ---------
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------ GPIB ---------
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DI : in std_logic_vector (7 downto 0);
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DI : in std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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ATN_in : in std_logic;
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ATN_in : in std_logic;
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ATN_out : out std_logic;
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ATN_out : out std_logic;
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DAV_in : in std_logic;
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DAV_in : in std_logic;
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DAV_out : out std_logic;
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DAV_out : out std_logic;
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NRFD_in : in std_logic;
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NRFD_in : in std_logic;
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NRFD_out : out std_logic;
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NRFD_out : out std_logic;
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NDAC_in : in std_logic;
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NDAC_in : in std_logic;
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NDAC_out : out std_logic;
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NDAC_out : out std_logic;
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EOI_in : in std_logic;
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EOI_in : in std_logic;
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EOI_out : out std_logic;
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EOI_out : out std_logic;
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SRQ_in : in std_logic;
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SRQ_in : in std_logic;
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SRQ_out : out std_logic;
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SRQ_out : out std_logic;
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IFC_in : in std_logic;
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IFC_in : in std_logic;
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IFC_out : out std_logic;
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IFC_out : out std_logic;
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REN_in : in std_logic;
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REN_in : in std_logic;
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REN_out : out std_logic;
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REN_out : out std_logic;
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------ LEDS ---------
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------ LEDS ---------
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led1 : out std_logic;
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led1 : out std_logic;
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led2 : out std_logic
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led2 : out std_logic
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------ DEBUG --------
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------ DEBUG --------
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;debug1 : out std_logic
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;debug1 : out std_logic
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;debug2 : out std_logic
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;debug2 : out std_logic
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);
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);
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end main;
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end main;
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architecture Behavioral of main is
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architecture Behavioral of main is
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constant BUF_LEN_MAX_BIT_NUM : integer := 11;
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constant BUF_LEN_MAX_BIT_NUM : integer := 11;
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type UART_REC_STATES is (
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type UART_REC_STATES is (
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ST_UART_REC_READ_ADDR,
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ST_UART_REC_READ_ADDR,
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ST_UART_REC_READ_B1,
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ST_UART_REC_READ_B1,
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ST_UART_REC_READ_B2,
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ST_UART_REC_READ_B2,
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ST_UART_REC_READ_BURST_W_LEN_B1,
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ST_UART_REC_READ_BURST_W_LEN_B1,
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ST_UART_REC_READ_BURST_W_LEN_B2,
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ST_UART_REC_READ_BURST_W_LEN_B2,
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ST_UART_REC_BURST_READ
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ST_UART_REC_BURST_READ
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);
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);
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type UART_TR_STATES is (
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type UART_TR_STATES is (
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ST_UART_TR_IDLE,
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ST_UART_TR_IDLE,
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ST_UART_TR_WAIT_NOT_READY_TO_SEND_1,
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ST_UART_TR_WAIT_NOT_READY_TO_SEND_1,
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ST_UART_TR_WRITE_B1,
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ST_UART_TR_WRITE_B1,
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ST_UART_TR_WAIT_NOT_READY_TO_SEND_2,
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ST_UART_TR_WAIT_NOT_READY_TO_SEND_2,
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ST_UART_TR_WRITE_B2,
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ST_UART_TR_WRITE_B2,
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ST_UART_TR_WRITE_BURST,
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ST_UART_TR_WRITE_BURST,
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ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND,
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ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND,
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ST_UART_TR_WAIT_BURST_READY_TO_SEND
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ST_UART_TR_WAIT_BURST_READY_TO_SEND
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);
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);
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---------- global -------------
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---------- global -------------
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signal reset : std_logic;
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signal reset : std_logic;
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signal reset_timer : integer range 0 to 50000000;
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signal reset_timer : integer range 0 to 50000000;
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---------- UART ---------------
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---------- UART ---------------
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signal uart_reset, uart_clk, uart_RX, uart_TX, uart_data_out_ready,
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signal uart_reset, uart_clk, uart_RX, uart_TX, uart_data_out_ready,
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uart_data_in_ready, uart_ready_to_send : std_logic;
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uart_data_in_ready, uart_ready_to_send : std_logic;
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signal uart_data_out, uart_data_in : std_logic_vector(7 downto 0);
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signal uart_data_out, uart_data_in : std_logic_vector(7 downto 0);
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---------- GPIB ------------------------
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---------- GPIB ------------------------
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signal gpib_reset, gpib_clk : std_logic;
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signal gpib_reset, gpib_clk : std_logic;
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---------- GPIB interface signals ------
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---------- GPIB interface signals ------
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signal gpib_DI, gpib_DO : std_logic_vector (7 downto 0);
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signal gpib_DI, gpib_DO : std_logic_vector (7 downto 0);
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signal gpib_output_valid : std_logic;
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signal gpib_output_valid : std_logic;
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signal gpib_ATN_in, gpib_ATN_out, gpib_DAV_in, gpib_DAV_out, gpib_NRFD_in,
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signal gpib_ATN_in, gpib_ATN_out, gpib_DAV_in, gpib_DAV_out, gpib_NRFD_in,
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gpib_NRFD_out, gpib_NDAC_in, gpib_NDAC_out, gpib_EOI_in, gpib_EOI_out,
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gpib_NRFD_out, gpib_NDAC_in, gpib_NDAC_out, gpib_EOI_in, gpib_EOI_out,
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gpib_SRQ_in, gpib_SRQ_out, gpib_IFC_in, gpib_IFC_out, gpib_REN_in,
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gpib_SRQ_in, gpib_SRQ_out, gpib_IFC_in, gpib_IFC_out, gpib_REN_in,
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gpib_REN_out : std_logic;
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gpib_REN_out : std_logic;
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---------- registers access -------------
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---------- registers access -------------
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signal gpib_data_in, gpib_data_out : std_logic_vector(15 downto 0);
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signal gpib_data_in, gpib_data_out : std_logic_vector(15 downto 0);
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signal gpib_reg_addr : std_logic_vector(14 downto 0);
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signal gpib_reg_addr : std_logic_vector(14 downto 0);
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signal gpib_strobe_read, gpib_strobe_write : std_logic;
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signal gpib_strobe_read, gpib_strobe_write : std_logic;
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----------- writer strobe pulse generator
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----------- writer strobe pulse generator
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signal t_in_strobe_write, t_out_strobe_write : std_logic;
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signal t_in_strobe_write, t_out_strobe_write : std_logic;
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----------- reader strobe pulse generator
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----------- reader strobe pulse generator
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signal t_in_strobe_read, t_out_strobe_read : std_logic;
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signal t_in_strobe_read, t_out_strobe_read : std_logic;
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---------- interrupt line ---------------
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---------- interrupt line ---------------
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signal gpib_interrupt_line : std_logic;
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signal gpib_interrupt_line : std_logic;
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---------- UART transceiver -------------
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---------- UART transceiver -------------
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signal uart_rec_state : UART_REC_STATES;
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signal uart_rec_state : UART_REC_STATES;
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signal uart_strobe_write_s1, uart_strobe_write_s2 : std_logic;
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signal uart_strobe_write_s1, uart_strobe_write_s2 : std_logic;
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signal uart_tr_state : UART_TR_STATES;
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signal uart_tr_state : UART_TR_STATES;
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signal burstLen : std_logic_vector (BUF_LEN_MAX_BIT_NUM downto 0);
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signal burstLen : std_logic_vector (BUF_LEN_MAX_BIT_NUM downto 0);
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signal isBurstRead : std_logic;
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signal isBurstRead : std_logic;
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signal subscribeBurstRead_1, subscribeBurstRead_2 : std_logic;
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signal subscribeBurstRead_1, subscribeBurstRead_2 : std_logic;
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signal currentBurstReadLen : integer range 0 to 2**BUF_LEN_MAX_BIT_NUM;
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signal currentBurstReadLen : integer range 0 to 2**BUF_LEN_MAX_BIT_NUM;
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-- GPIB synchronizer
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-- GPIB synchronizer
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signal gSync_clk : std_logic;
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signal gSync_clk : std_logic;
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signal gSync_DI : std_logic_vector(7 downto 0);
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signal gSync_DI : std_logic_vector(7 downto 0);
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signal gSync_DO : std_logic_vector(7 downto 0);
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signal gSync_DO : std_logic_vector(7 downto 0);
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signal gSync_ATN_in : std_logic;
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signal gSync_ATN_in : std_logic;
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signal gSync_ATN_Out : std_logic;
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signal gSync_ATN_Out : std_logic;
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signal gSync_DAV_in : std_logic;
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signal gSync_DAV_in : std_logic;
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signal gSync_DAV_out : std_logic;
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signal gSync_DAV_out : std_logic;
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signal gSync_NRFD_in : std_logic;
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signal gSync_NRFD_in : std_logic;
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signal gSync_NRFD_out : std_logic;
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signal gSync_NRFD_out : std_logic;
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signal gSync_NDAC_in : std_logic;
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signal gSync_NDAC_in : std_logic;
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signal gSync_NDAC_out : std_logic;
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signal gSync_NDAC_out : std_logic;
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signal gSync_EOI_in : std_logic;
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signal gSync_EOI_in : std_logic;
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signal gSync_EOI_out : std_logic;
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signal gSync_EOI_out : std_logic;
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signal gSync_SRQ_in : std_logic;
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signal gSync_SRQ_in : std_logic;
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signal gSync_SRQ_out : std_logic;
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signal gSync_SRQ_out : std_logic;
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signal gSync_IFC_in : std_logic;
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signal gSync_IFC_in : std_logic;
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signal gSync_IFC_out : std_logic;
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signal gSync_IFC_out : std_logic;
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signal gSync_REN_in : std_logic;
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signal gSync_REN_in : std_logic;
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signal gSync_REN_out : std_logic;
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signal gSync_REN_out : std_logic;
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begin
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begin
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-- UART
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-- UART
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uart_reset <= reset;
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uart_reset <= reset;
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uart_clk <= clk;
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uart_clk <= clk;
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uart_RX <= RX;
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uart_RX <= RX;
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TX <= uart_TX;
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TX <= uart_TX;
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-- GPIB sync
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-- GPIB sync
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gSync_clk <= clk;
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gSync_clk <= clk;
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gSync_DI <= DI;
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gSync_DI <= DI;
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gSync_ATN_in <= ATN_in;
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gSync_ATN_in <= ATN_in;
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gSync_DAV_in <= DAV_in;
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gSync_DAV_in <= DAV_in;
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gSync_NRFD_in <= NRFD_in;
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gSync_NRFD_in <= NRFD_in;
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gSync_NDAC_in <= NDAC_in;
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gSync_NDAC_in <= NDAC_in;
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gSync_EOI_in <= EOI_in;
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gSync_EOI_in <= EOI_in;
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gSync_SRQ_in <= SRQ_in;
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gSync_SRQ_in <= SRQ_in;
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gSync_IFC_in <= IFC_in;
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gSync_IFC_in <= IFC_in;
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gSync_REN_in <= REN_in;
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gSync_REN_in <= REN_in;
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-- GPIB
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-- GPIB
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gpib_reset <= reset;
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gpib_reset <= reset;
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gpib_clk <= clk;
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gpib_clk <= clk;
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gpib_DI <= not gSync_DO;
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gpib_DI <= not gSync_DO;
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DO <= gpib_DO when gpib_output_valid = '1' else "00000000";
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DO <= gpib_DO when gpib_output_valid = '1' else "00000000";
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gpib_ATN_in <= not gSync_ATN_Out;
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gpib_ATN_in <= not gSync_ATN_Out;
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ATN_out <= gpib_ATN_out;
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ATN_out <= gpib_ATN_out;
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gpib_DAV_in <= not gSync_DAV_out;
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gpib_DAV_in <= not gSync_DAV_out;
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DAV_out <= gpib_DAV_out;
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DAV_out <= gpib_DAV_out;
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gpib_NRFD_in <= not gSync_NRFD_out;
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gpib_NRFD_in <= not gSync_NRFD_out;
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NRFD_out <= gpib_NRFD_out;
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NRFD_out <= gpib_NRFD_out;
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gpib_NDAC_in <= not gSync_NDAC_out;
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gpib_NDAC_in <= not gSync_NDAC_out;
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NDAC_out <= gpib_NDAC_out;
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NDAC_out <= gpib_NDAC_out;
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gpib_EOI_in <= not gSync_EOI_out;
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gpib_EOI_in <= not gSync_EOI_out;
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EOI_out <= gpib_EOI_out;
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EOI_out <= gpib_EOI_out;
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gpib_SRQ_in <= not gSync_SRQ_out;
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gpib_SRQ_in <= not gSync_SRQ_out;
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SRQ_out <= gpib_SRQ_out;
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SRQ_out <= gpib_SRQ_out;
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gpib_IFC_in <= not gSync_IFC_out;
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gpib_IFC_in <= not gSync_IFC_out;
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IFC_out <= gpib_IFC_out;
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IFC_out <= gpib_IFC_out;
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gpib_REN_in <= not gSync_REN_out;
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gpib_REN_in <= not gSync_REN_out;
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REN_out <= gpib_REN_out;
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REN_out <= gpib_REN_out;
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-- DEBUG
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-- DEBUG
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--led1 <= reset;
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--led1 <= reset;
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led2 <= uart_data_out_ready;
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led2 <= uart_data_out_ready;
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--debug1 <= gpib_output_valid;
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--debug1 <= gpib_output_valid;
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---------- receive from UART -----------
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---------- receive from UART -----------
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process (reset, uart_data_out_ready, uart_strobe_write_s2) begin
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process (reset, uart_data_out_ready, uart_strobe_write_s2) begin
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if reset = '1' then
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if reset = '1' then
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uart_strobe_write_s1 <= uart_strobe_write_s2;
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uart_strobe_write_s1 <= uart_strobe_write_s2;
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t_in_strobe_write <= '0';
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t_in_strobe_write <= '0';
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subscribeBurstRead_1 <= '0';
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subscribeBurstRead_1 <= '0';
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uart_rec_state <= ST_UART_REC_READ_ADDR;
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uart_rec_state <= ST_UART_REC_READ_ADDR;
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elsif rising_edge(uart_data_out_ready) then
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elsif rising_edge(uart_data_out_ready) then
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case uart_rec_state is
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case uart_rec_state is
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when ST_UART_REC_READ_ADDR =>
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when ST_UART_REC_READ_ADDR =>
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gpib_reg_addr(14 downto 6) <= "000000000";
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gpib_reg_addr(14 downto 6) <= "000000000";
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gpib_reg_addr(5 downto 0) <= uart_data_out(5 downto 0);
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gpib_reg_addr(5 downto 0) <= uart_data_out(5 downto 0);
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if uart_data_out(7) = '1' then
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if uart_data_out(7) = '1' then
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if uart_data_out(6) = '1' then
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if uart_data_out(6) = '1' then
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isBurstRead <= '1';
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isBurstRead <= '1';
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uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
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uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
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else
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else
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uart_strobe_write_s1 <= not uart_strobe_write_s2;
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uart_strobe_write_s1 <= not uart_strobe_write_s2;
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uart_rec_state <= ST_UART_REC_READ_ADDR;
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uart_rec_state <= ST_UART_REC_READ_ADDR;
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end if;
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end if;
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else
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else
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if uart_data_out(6) = '1' then
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if uart_data_out(6) = '1' then
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isBurstRead <= '0';
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isBurstRead <= '0';
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uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
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uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
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else
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else
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uart_rec_state <= ST_UART_REC_READ_B1;
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uart_rec_state <= ST_UART_REC_READ_B1;
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end if;
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end if;
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end if;
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end if;
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when ST_UART_REC_READ_B1 =>
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when ST_UART_REC_READ_B1 =>
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gpib_data_in(7 downto 0) <= uart_data_out;
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gpib_data_in(7 downto 0) <= uart_data_out;
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uart_rec_state <= ST_UART_REC_READ_B2;
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uart_rec_state <= ST_UART_REC_READ_B2;
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when ST_UART_REC_READ_B2 =>
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when ST_UART_REC_READ_B2 =>
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gpib_data_in(15 downto 8) <= uart_data_out;
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gpib_data_in(15 downto 8) <= uart_data_out;
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t_in_strobe_write <= not t_out_strobe_write;
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t_in_strobe_write <= not t_out_strobe_write;
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uart_rec_state <= ST_UART_REC_READ_ADDR;
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uart_rec_state <= ST_UART_REC_READ_ADDR;
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|
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-- burst length
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-- burst length
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when ST_UART_REC_READ_BURST_W_LEN_B1 =>
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when ST_UART_REC_READ_BURST_W_LEN_B1 =>
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burstLen(7 downto 0) <= uart_data_out;
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burstLen(7 downto 0) <= uart_data_out;
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uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B2;
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uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B2;
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when ST_UART_REC_READ_BURST_W_LEN_B2 =>
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when ST_UART_REC_READ_BURST_W_LEN_B2 =>
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burstLen(11 downto 8) <= uart_data_out(3 downto 0);
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burstLen(11 downto 8) <= uart_data_out(3 downto 0);
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if isBurstRead = '1' then
|
if isBurstRead = '1' then
|
subscribeBurstRead_1 <= not subscribeBurstRead_2;
|
subscribeBurstRead_1 <= not subscribeBurstRead_2;
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uart_rec_state <= ST_UART_REC_READ_ADDR;
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uart_rec_state <= ST_UART_REC_READ_ADDR;
|
else
|
else
|
uart_rec_state <= ST_UART_REC_BURST_READ;
|
uart_rec_state <= ST_UART_REC_BURST_READ;
|
end if;
|
end if;
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|
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when ST_UART_REC_BURST_READ =>
|
when ST_UART_REC_BURST_READ =>
|
gpib_data_in(7 downto 0) <= uart_data_out;
|
gpib_data_in(7 downto 0) <= uart_data_out;
|
t_in_strobe_write <= not t_out_strobe_write;
|
t_in_strobe_write <= not t_out_strobe_write;
|
burstLen <= burstLen - 1;
|
burstLen <= burstLen - 1;
|
|
|
if burstLen = "000000000001" then
|
if burstLen = "000000000001" then
|
uart_rec_state <= ST_UART_REC_READ_ADDR;
|
uart_rec_state <= ST_UART_REC_READ_ADDR;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
uart_rec_state <= ST_UART_REC_READ_ADDR;
|
uart_rec_state <= ST_UART_REC_READ_ADDR;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
---------- write to UART ---------------------
|
---------- write to UART ---------------------
|
process (reset, clk, uart_strobe_write_s1) begin
|
process (reset, clk, uart_strobe_write_s1) begin
|
if reset = '1' then
|
if reset = '1' then
|
uart_strobe_write_s2 <= uart_strobe_write_s1;
|
uart_strobe_write_s2 <= uart_strobe_write_s1;
|
uart_data_in_ready <= '0';
|
uart_data_in_ready <= '0';
|
t_in_strobe_read <= '0';
|
t_in_strobe_read <= '0';
|
|
|
subscribeBurstRead_2 <= '0';
|
subscribeBurstRead_2 <= '0';
|
|
|
led1 <= '0';
|
led1 <= '0';
|
|
|
uart_tr_state <= ST_UART_TR_IDLE;
|
uart_tr_state <= ST_UART_TR_IDLE;
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
case uart_tr_state is
|
case uart_tr_state is
|
when ST_UART_TR_IDLE =>
|
when ST_UART_TR_IDLE =>
|
if uart_strobe_write_s2 /= uart_strobe_write_s1 and
|
if uart_strobe_write_s2 /= uart_strobe_write_s1 and
|
uart_ready_to_send = '1' then
|
uart_ready_to_send = '1' then
|
uart_strobe_write_s2 <= uart_strobe_write_s1;
|
uart_strobe_write_s2 <= uart_strobe_write_s1;
|
uart_data_in <= gpib_data_out(7 downto 0);
|
uart_data_in <= gpib_data_out(7 downto 0);
|
uart_data_in_ready <= '1';
|
uart_data_in_ready <= '1';
|
uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_1;
|
uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_1;
|
elsif subscribeBurstRead_1 /= subscribeBurstRead_2 and
|
elsif subscribeBurstRead_1 /= subscribeBurstRead_2 and
|
uart_ready_to_send = '1' then
|
uart_ready_to_send = '1' then
|
subscribeBurstRead_2 <= subscribeBurstRead_1;
|
subscribeBurstRead_2 <= subscribeBurstRead_1;
|
currentBurstReadLen <= conv_integer(UNSIGNED(burstLen));
|
currentBurstReadLen <= conv_integer(UNSIGNED(burstLen));
|
|
|
uart_tr_state <= ST_UART_TR_WRITE_BURST;
|
uart_tr_state <= ST_UART_TR_WRITE_BURST;
|
end if;
|
end if;
|
|
|
when ST_UART_TR_WAIT_NOT_READY_TO_SEND_1 =>
|
when ST_UART_TR_WAIT_NOT_READY_TO_SEND_1 =>
|
if uart_ready_to_send = '0' then
|
if uart_ready_to_send = '0' then
|
uart_data_in_ready <= '0';
|
uart_data_in_ready <= '0';
|
uart_tr_state <= ST_UART_TR_WRITE_B1;
|
uart_tr_state <= ST_UART_TR_WRITE_B1;
|
end if;
|
end if;
|
|
|
when ST_UART_TR_WRITE_B1 =>
|
when ST_UART_TR_WRITE_B1 =>
|
if uart_ready_to_send = '1' then
|
if uart_ready_to_send = '1' then
|
uart_data_in <= gpib_data_out(15 downto 8);
|
uart_data_in <= gpib_data_out(15 downto 8);
|
uart_data_in_ready <= '1';
|
uart_data_in_ready <= '1';
|
uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_2;
|
uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_2;
|
end if;
|
end if;
|
|
|
when ST_UART_TR_WAIT_NOT_READY_TO_SEND_2 =>
|
when ST_UART_TR_WAIT_NOT_READY_TO_SEND_2 =>
|
if uart_ready_to_send = '0' then
|
if uart_ready_to_send = '0' then
|
uart_data_in_ready <= '0';
|
uart_data_in_ready <= '0';
|
uart_tr_state <= ST_UART_TR_WRITE_B2;
|
uart_tr_state <= ST_UART_TR_WRITE_B2;
|
end if;
|
end if;
|
|
|
when ST_UART_TR_WRITE_B2 =>
|
when ST_UART_TR_WRITE_B2 =>
|
if uart_ready_to_send = '1' then
|
if uart_ready_to_send = '1' then
|
t_in_strobe_read <= not t_out_strobe_read;
|
t_in_strobe_read <= not t_out_strobe_read;
|
|
|
uart_tr_state <= ST_UART_TR_IDLE;
|
uart_tr_state <= ST_UART_TR_IDLE;
|
end if;
|
end if;
|
|
|
-- burst read
|
-- burst read
|
when ST_UART_TR_WRITE_BURST =>
|
when ST_UART_TR_WRITE_BURST =>
|
if uart_ready_to_send = '1' then
|
if uart_ready_to_send = '1' then
|
uart_data_in <= gpib_data_out(7 downto 0);
|
uart_data_in <= gpib_data_out(7 downto 0);
|
uart_data_in_ready <= '1';
|
uart_data_in_ready <= '1';
|
currentBurstReadLen <= currentBurstReadLen - 1;
|
currentBurstReadLen <= currentBurstReadLen - 1;
|
|
|
led1 <= '1';
|
led1 <= '1';
|
|
|
uart_tr_state <= ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND;
|
uart_tr_state <= ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND;
|
end if;
|
end if;
|
|
|
when ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND =>
|
when ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND =>
|
if uart_ready_to_send = '0' then
|
if uart_ready_to_send = '0' then
|
uart_data_in_ready <= '0';
|
uart_data_in_ready <= '0';
|
t_in_strobe_read <= not t_out_strobe_read;
|
t_in_strobe_read <= not t_out_strobe_read;
|
|
|
uart_tr_state <= ST_UART_TR_WAIT_BURST_READY_TO_SEND;
|
uart_tr_state <= ST_UART_TR_WAIT_BURST_READY_TO_SEND;
|
end if;
|
end if;
|
|
|
when ST_UART_TR_WAIT_BURST_READY_TO_SEND =>
|
when ST_UART_TR_WAIT_BURST_READY_TO_SEND =>
|
if uart_ready_to_send = '1' then
|
if uart_ready_to_send = '1' then
|
|
|
if currentBurstReadLen > 0 then
|
if currentBurstReadLen > 0 then
|
uart_tr_state <= ST_UART_TR_WRITE_BURST;
|
uart_tr_state <= ST_UART_TR_WRITE_BURST;
|
else
|
else
|
led1 <= '0';
|
led1 <= '0';
|
uart_tr_state <= ST_UART_TR_IDLE;
|
uart_tr_state <= ST_UART_TR_IDLE;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
|
when others =>
|
when others =>
|
uart_tr_state <= ST_UART_TR_IDLE;
|
uart_tr_state <= ST_UART_TR_IDLE;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process (clk) begin
|
process (clk) begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if reset_timer < 50000000 then
|
if reset_timer < 50000000 then
|
reset_timer <= reset_timer + 1;
|
reset_timer <= reset_timer + 1;
|
reset <= '1';
|
reset <= '1';
|
else
|
else
|
reset <= '0';
|
reset <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
uart0: Uart port map(
|
uart0: Uart port map(
|
reset => uart_reset, clk => uart_clk, RX => uart_RX, TX => uart_TX,
|
reset => uart_reset, clk => uart_clk, RX => uart_RX, TX => uart_TX,
|
data_out => uart_data_out, data_out_ready => uart_data_out_ready,
|
data_out => uart_data_out, data_out_ready => uart_data_out_ready,
|
data_in => uart_data_in, data_in_ready => uart_data_in_ready,
|
data_in => uart_data_in, data_in_ready => uart_data_in_ready,
|
ready_to_send => uart_ready_to_send
|
ready_to_send => uart_ready_to_send
|
);
|
);
|
|
|
spg_strobe_write: SinglePulseGenerator generic map (WIDTH => 1) port map(
|
spg_strobe_write: SinglePulseGenerator generic map (WIDTH => 1) port map(
|
reset => reset, clk => clk,
|
reset => reset, clk => clk,
|
t_in => t_in_strobe_write, t_out => t_out_strobe_write,
|
t_in => t_in_strobe_write, t_out => t_out_strobe_write,
|
pulse => gpib_strobe_write
|
pulse => gpib_strobe_write
|
);
|
);
|
|
|
spg_strobe_read: SinglePulseGenerator generic map (WIDTH => 1) port map(
|
spg_strobe_read: SinglePulseGenerator generic map (WIDTH => 1) port map(
|
reset => reset, clk => clk,
|
reset => reset, clk => clk,
|
t_in => t_in_strobe_read, t_out => t_out_strobe_read,
|
t_in => t_in_strobe_read, t_out => t_out_strobe_read,
|
pulse => gpib_strobe_read
|
pulse => gpib_strobe_read
|
);
|
);
|
|
|
gpibSync: GpibSynchronizer port map (
|
gpibSync: GpibSynchronizer port map (
|
clk => gSync_clk,
|
clk => gSync_clk,
|
DI => gSync_DI,
|
DI => gSync_DI,
|
DO => gSync_DO,
|
DO => gSync_DO,
|
ATN_in => gSync_ATN_in,
|
ATN_in => gSync_ATN_in,
|
ATN_out => gSync_ATN_Out,
|
ATN_out => gSync_ATN_Out,
|
DAV_in => gSync_DAV_in,
|
DAV_in => gSync_DAV_in,
|
DAV_out => gSync_DAV_out,
|
DAV_out => gSync_DAV_out,
|
NRFD_in => gSync_NRFD_in,
|
NRFD_in => gSync_NRFD_in,
|
NRFD_out => gSync_NRFD_out,
|
NRFD_out => gSync_NRFD_out,
|
NDAC_in => gSync_NDAC_in,
|
NDAC_in => gSync_NDAC_in,
|
NDAC_out => gSync_NDAC_out,
|
NDAC_out => gSync_NDAC_out,
|
EOI_in => gSync_EOI_in,
|
EOI_in => gSync_EOI_in,
|
EOI_out => gSync_EOI_out,
|
EOI_out => gSync_EOI_out,
|
SRQ_in => gSync_SRQ_in,
|
SRQ_in => gSync_SRQ_in,
|
SRQ_out => gSync_SRQ_out,
|
SRQ_out => gSync_SRQ_out,
|
IFC_in => gSync_IFC_in,
|
IFC_in => gSync_IFC_in,
|
IFC_out => gSync_IFC_out,
|
IFC_out => gSync_IFC_out,
|
REN_in => gSync_REN_in,
|
REN_in => gSync_REN_in,
|
REN_out => gSync_REN_out
|
REN_out => gSync_REN_out
|
);
|
);
|
|
|
gpib0: RegsGpibFasade port map(
|
gpib0: RegsGpibFasade port map(
|
reset => gpib_reset, clk => gpib_clk,
|
reset => gpib_reset, clk => gpib_clk,
|
DI => gpib_DI, DO => gpib_DO, output_valid => gpib_output_valid,
|
DI => gpib_DI, DO => gpib_DO, output_valid => gpib_output_valid,
|
ATN_in => gpib_ATN_in, ATN_out => gpib_ATN_out,
|
ATN_in => gpib_ATN_in, ATN_out => gpib_ATN_out,
|
DAV_in => gpib_DAV_in, DAV_out => gpib_DAV_out,
|
DAV_in => gpib_DAV_in, DAV_out => gpib_DAV_out,
|
NRFD_in => gpib_NRFD_in, NRFD_out => gpib_NRFD_out,
|
NRFD_in => gpib_NRFD_in, NRFD_out => gpib_NRFD_out,
|
NDAC_in => gpib_NDAC_in, NDAC_out => gpib_NDAC_out,
|
NDAC_in => gpib_NDAC_in, NDAC_out => gpib_NDAC_out,
|
EOI_in => gpib_EOI_in, EOI_out => gpib_EOI_out,
|
EOI_in => gpib_EOI_in, EOI_out => gpib_EOI_out,
|
SRQ_in => gpib_SRQ_in, SRQ_out => gpib_SRQ_out,
|
SRQ_in => gpib_SRQ_in, SRQ_out => gpib_SRQ_out,
|
IFC_in => gpib_IFC_in, IFC_out => gpib_IFC_out,
|
IFC_in => gpib_IFC_in, IFC_out => gpib_IFC_out,
|
REN_in => gpib_REN_in, REN_out => gpib_REN_out,
|
REN_in => gpib_REN_in, REN_out => gpib_REN_out,
|
data_in => gpib_data_in, data_out => gpib_data_out,
|
data_in => gpib_data_in, data_out => gpib_data_out,
|
reg_addr => gpib_reg_addr,
|
reg_addr => gpib_reg_addr,
|
strobe_read => gpib_strobe_read,
|
strobe_read => gpib_strobe_read,
|
strobe_write => gpib_strobe_write,
|
strobe_write => gpib_strobe_write,
|
interrupt_line => gpib_interrupt_line,
|
interrupt_line => gpib_interrupt_line,
|
debug1 => debug1, debug2 => debug2
|
debug1 => debug1, debug2 => debug2
|
);
|
);
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
