--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: if_func_C
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-- Entity: if_func_C
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-- Date: 23:00:30 10/04/2011
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-- Date: 23:00:30 10/04/2011
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-- Author: apaluch
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-- Author: Andrzej Paluch
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.utilPkg.all;
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use work.utilPkg.all;
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entity if_func_C is
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entity if_func_C is
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port(
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port(
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-- device inputs
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-- device inputs
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clk : in std_logic; -- clock
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clk : in std_logic; -- clock
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pon : in std_logic; -- power on
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pon : in std_logic; -- power on
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gts : in std_logic; -- go to standby
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gts : in std_logic; -- go to standby
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rpp : in std_logic; -- request parallel poll
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rpp : in std_logic; -- request parallel poll
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tcs : in std_logic; -- take control synchronously
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tcs : in std_logic; -- take control synchronously
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tca : in std_logic; -- take control asynchronously
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tca : in std_logic; -- take control asynchronously
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sic : in std_logic; -- send interface clear
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sic : in std_logic; -- send interface clear
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rsc : in std_logic; -- request system control
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rsc : in std_logic; -- request system control
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sre : in std_logic; -- send remote enable
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sre : in std_logic; -- send remote enable
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-- state inputs
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-- state inputs
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TADS : in std_logic; -- talker addressed state (T or TE)
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TADS : in std_logic; -- talker addressed state (T or TE)
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ACDS : in std_logic; -- accept data state (AH)
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ACDS : in std_logic; -- accept data state (AH)
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ANRS : in std_logic; -- acceptor not ready state (AH)
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ANRS : in std_logic; -- acceptor not ready state (AH)
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STRS : in std_logic; -- source transfer state (SH)
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STRS : in std_logic; -- source transfer state (SH)
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SDYS : in std_logic; -- source delay state (SH)
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SDYS : in std_logic; -- source delay state (SH)
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-- command inputs
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-- command inputs
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ATN_in : in std_logic; -- attention
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ATN_in : in std_logic; -- attention
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IFC_in : in std_logic; -- interface clear
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IFC_in : in std_logic; -- interface clear
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TCT_in : in std_logic; -- take control
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TCT_in : in std_logic; -- take control
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SRQ_in : in std_logic; -- service request
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SRQ_in : in std_logic; -- service request
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-- command outputs
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-- command outputs
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ATN_out : out std_logic; -- attention
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ATN_out : out std_logic; -- attention
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IFC_out : out std_logic; -- interface clear
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IFC_out : out std_logic; -- interface clear
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TCT_out : out std_logic; -- take control
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TCT_out : out std_logic; -- take control
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IDY_out : out std_logic; -- identify
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IDY_out : out std_logic; -- identify
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REN_out : out std_logic; -- remote enable
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REN_out : out std_logic; -- remote enable
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-- reported states
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-- reported states
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CACS : out std_logic; -- controller active state
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CACS : out std_logic; -- controller active state
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CTRS : out std_logic; -- controller transfer state
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CTRS : out std_logic; -- controller transfer state
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CSBS : out std_logic; -- controller standby state
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CSBS : out std_logic; -- controller standby state
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CPPS : out std_logic; -- controller parallel poll state
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CPPS : out std_logic; -- controller parallel poll state
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CSRS : out std_logic; -- controller service requested state
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CSRS : out std_logic; -- controller service requested state
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SACS : out std_logic -- system control active state
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SACS : out std_logic -- system control active state
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);
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);
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end if_func_C;
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end if_func_C;
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architecture Behavioral of if_func_C is
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architecture Behavioral of if_func_C is
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-- states
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-- states
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type C_STATE_1 is (
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type C_STATE_1 is (
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-- controller idle state
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-- controller idle state
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ST_CIDS,
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ST_CIDS,
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-- controller addressed state
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-- controller addressed state
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ST_CADS,
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ST_CADS,
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-- controller transfer state
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-- controller transfer state
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ST_CTRS,
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ST_CTRS,
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-- controller active state
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-- controller active state
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ST_CACS,
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ST_CACS,
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-- controller standby state
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-- controller standby state
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ST_CSBS,
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ST_CSBS,
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-- controllet synchronous wait state
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-- controllet synchronous wait state
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ST_CSWS,
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ST_CSWS,
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-- controller active wait state
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-- controller active wait state
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ST_CAWS,
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ST_CAWS,
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-- controller parallel poll wait state
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-- controller parallel poll wait state
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ST_CPWS,
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ST_CPWS,
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-- controller parallel poll wait state
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-- controller parallel poll wait state
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ST_CPPS
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ST_CPPS
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);
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);
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-- states
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-- states
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type C_STATE_2 is (
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type C_STATE_2 is (
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-- controller service not requested state
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-- controller service not requested state
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ST_CSNS,
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ST_CSNS,
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-- controller service requested state
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-- controller service requested state
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ST_CSRS
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ST_CSRS
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);
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);
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-- states
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-- states
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type C_STATE_3 is (
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type C_STATE_3 is (
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-- system control interface clear idle state
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-- system control interface clear idle state
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ST_SIIS,
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ST_SIIS,
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-- system control interface clear active state
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-- system control interface clear active state
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ST_SIAS,
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ST_SIAS,
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-- system control interface clear not active state
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-- system control interface clear not active state
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ST_SINS
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ST_SINS
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);
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);
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-- states
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-- states
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type C_STATE_4 is (
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type C_STATE_4 is (
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-- system control remote enable idle state
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-- system control remote enable idle state
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ST_SRIS,
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ST_SRIS,
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-- system control remote enable active state
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-- system control remote enable active state
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ST_SRAS,
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ST_SRAS,
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-- system control remote enable not active state
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-- system control remote enable not active state
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ST_SRNS
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ST_SRNS
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);
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);
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-- states
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-- states
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type C_STATE_5 is (
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type C_STATE_5 is (
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-- system control not active state
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-- system control not active state
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ST_SNAS,
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ST_SNAS,
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-- system control active state
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-- system control active state
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ST_SACS
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ST_SACS
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);
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);
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-- current state
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-- current state
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signal current_state_1 : C_STATE_1;
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signal current_state_1 : C_STATE_1;
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signal current_state_2 : C_STATE_2;
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signal current_state_2 : C_STATE_2;
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signal current_state_3 : C_STATE_3;
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signal current_state_3 : C_STATE_3;
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signal current_state_4 : C_STATE_4;
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signal current_state_4 : C_STATE_4;
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signal current_state_5 : C_STATE_5;
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signal current_state_5 : C_STATE_5;
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-- events
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-- events
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signal event1_1, event1_2, event1_3, event1_4, event1_5,
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signal event1_1, event1_2, event1_3, event1_4, event1_5,
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event1_6, event1_7, event1_8, event1_9, event1_10,
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event1_6, event1_7, event1_8, event1_9, event1_10,
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event1_11, event1_12 : boolean;
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event1_11, event1_12 : boolean;
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signal event2_1, event2_2 : boolean;
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signal event2_1, event2_2 : boolean;
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signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;
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signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;
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signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;
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signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;
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signal event5_1, event5_2 : boolean;
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signal event5_1, event5_2 : boolean;
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-- timers
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-- timers
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constant TIMER_T6_TIMEOUT : integer := 110;
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constant TIMER_T6_TIMEOUT : integer := 110;
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constant TIMER_T7_TIMEOUT : integer := 25;
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constant TIMER_T7_TIMEOUT : integer := 25;
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constant TIMER_T9_TIMEOUT : integer := 75;
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constant TIMER_T9_TIMEOUT : integer := 75;
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constant TIMER_A_MAX : integer := 128;
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constant TIMER_A_MAX : integer := 128;
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signal timer_a : integer range 0 to TIMER_A_MAX;
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signal timer_a : integer range 0 to TIMER_A_MAX;
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signal timer_T6Expired : boolean;
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signal timer_T6Expired : boolean;
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signal timer_T7Expired : boolean;
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signal timer_T7Expired : boolean;
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signal timer_T9Expired : boolean;
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signal timer_T9Expired : boolean;
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constant TIMER_T8_TIMEOUT : integer := 5000;
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constant TIMER_T8_TIMEOUT : integer := 5000;
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constant TIMER_B_MAX : integer := 5004;
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constant TIMER_B_MAX : integer := 5004;
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signal timer_b : integer range 0 to TIMER_B_MAX;
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signal timer_b : integer range 0 to TIMER_B_MAX;
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signal timer_b_1 : integer range 0 to TIMER_B_MAX;
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signal timer_b_1 : integer range 0 to TIMER_B_MAX;
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signal timer_T8Expired : boolean;
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signal timer_T8Expired : boolean;
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signal timer_T8_1Expired : boolean;
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signal timer_T8_1Expired : boolean;
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begin
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begin
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-- state machine process - C_STATE_1
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-- state machine process - C_STATE_1
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process(pon, clk) begin
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process(pon, clk) begin
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-- async reset
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-- async reset
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if pon='1' then
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if pon='1' then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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-- timer
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-- timer
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if timer_a < TIMER_A_MAX then
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if timer_a < TIMER_A_MAX then
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timer_a <= timer_a + 1;
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timer_a <= timer_a + 1;
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end if;
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end if;
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-- state machine
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-- state machine
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case current_state_1 is
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case current_state_1 is
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------------------
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------------------
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when ST_CIDS =>
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when ST_CIDS =>
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if event1_1 then
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if event1_1 then
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-- no state change
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-- no state change
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elsif event1_2 then
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elsif event1_2 then
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current_state_1 <= ST_CADS;
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current_state_1 <= ST_CADS;
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end if;
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end if;
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------------------
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------------------
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when ST_CADS =>
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when ST_CADS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_4 then
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elsif event1_4 then
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current_state_1 <= ST_CACS;
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current_state_1 <= ST_CACS;
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end if;
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end if;
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------------------
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------------------
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when ST_CACS =>
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when ST_CACS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_5 then
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elsif event1_5 then
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current_state_1 <= ST_CTRS;
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current_state_1 <= ST_CTRS;
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elsif event1_6 then
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elsif event1_6 then
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current_state_1 <= ST_CSBS;
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current_state_1 <= ST_CSBS;
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elsif event1_7 then
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elsif event1_7 then
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timer_a <= 0;
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timer_a <= 0;
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current_state_1 <= ST_CPWS;
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current_state_1 <= ST_CPWS;
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end if;
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end if;
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------------------
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------------------
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when ST_CTRS =>
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when ST_CTRS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_3 or event1_1 then
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elsif event1_3 or event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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end if;
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end if;
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------------------
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------------------
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when ST_CSBS =>
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when ST_CSBS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_9 then
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elsif event1_9 then
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timer_a <= 0;
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timer_a <= 0;
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current_state_1 <= ST_CSWS;
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current_state_1 <= ST_CSWS;
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end if;
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end if;
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------------------
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------------------
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when ST_CSWS =>
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when ST_CSWS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_10 then
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elsif event1_10 then
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timer_a <= 0;
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timer_a <= 0;
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current_state_1 <= ST_CAWS;
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current_state_1 <= ST_CAWS;
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end if;
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end if;
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------------------
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------------------
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when ST_CAWS =>
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when ST_CAWS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_8 then
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elsif event1_8 then
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current_state_1 <= ST_CACS;
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current_state_1 <= ST_CACS;
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elsif event1_7 then
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elsif event1_7 then
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timer_a <= 0;
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timer_a <= 0;
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current_state_1 <= ST_CPWS;
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current_state_1 <= ST_CPWS;
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end if;
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end if;
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------------------
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------------------
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when ST_CPWS =>
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when ST_CPWS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_11 then
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elsif event1_11 then
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current_state_1 <= ST_CPPS;
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current_state_1 <= ST_CPPS;
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end if;
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end if;
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------------------
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------------------
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when ST_CPPS =>
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when ST_CPPS =>
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if event1_1 then
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if event1_1 then
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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elsif event1_12 then
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elsif event1_12 then
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current_state_1 <= ST_CAWS;
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current_state_1 <= ST_CAWS;
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end if;
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end if;
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------------------
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------------------
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when others =>
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when others =>
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current_state_1 <= ST_CIDS;
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current_state_1 <= ST_CIDS;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- state machine process - C_STATE_2
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-- state machine process - C_STATE_2
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process(pon, clk) begin
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process(pon, clk) begin
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-- async reset
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-- async reset
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if pon='1' then
|
if pon='1' then
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current_state_2 <= ST_CSNS;
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current_state_2 <= ST_CSNS;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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-- state machine
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-- state machine
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case current_state_2 is
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case current_state_2 is
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------------------
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------------------
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when ST_CSNS =>
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when ST_CSNS =>
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if event2_1 then
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if event2_1 then
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current_state_2 <= ST_CSRS;
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current_state_2 <= ST_CSRS;
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end if;
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end if;
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------------------
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------------------
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when ST_CSRS =>
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when ST_CSRS =>
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if event2_2 then
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if event2_2 then
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current_state_2 <= ST_CSNS;
|
current_state_2 <= ST_CSNS;
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end if;
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end if;
|
------------------
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------------------
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when others =>
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when others =>
|
current_state_2 <= ST_CSNS;
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current_state_2 <= ST_CSNS;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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|
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-- state machine process - C_STATE_3
|
-- state machine process - C_STATE_3
|
process(pon, clk) begin
|
process(pon, clk) begin
|
-- async reset
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-- async reset
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if pon='1' then
|
if pon='1' then
|
current_state_3 <= ST_SIIS;
|
current_state_3 <= ST_SIIS;
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
|
|
-- timer
|
-- timer
|
if timer_b < TIMER_B_MAX then
|
if timer_b < TIMER_B_MAX then
|
timer_b <= timer_b + 1;
|
timer_b <= timer_b + 1;
|
end if;
|
end if;
|
|
|
-- state machine
|
-- state machine
|
case current_state_3 is
|
case current_state_3 is
|
------------------
|
------------------
|
when ST_SIIS =>
|
when ST_SIIS =>
|
if event3_1 then
|
if event3_1 then
|
-- no state change
|
-- no state change
|
elsif event3_2 then
|
elsif event3_2 then
|
timer_b <= 0;
|
timer_b <= 0;
|
current_state_3 <= ST_SIAS;
|
current_state_3 <= ST_SIAS;
|
elsif event3_3 then
|
elsif event3_3 then
|
current_state_3 <= ST_SINS;
|
current_state_3 <= ST_SINS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_SIAS =>
|
when ST_SIAS =>
|
if event3_1 then
|
if event3_1 then
|
current_state_3 <= ST_SIIS;
|
current_state_3 <= ST_SIIS;
|
elsif event3_5 then
|
elsif event3_5 then
|
current_state_3 <= ST_SINS;
|
current_state_3 <= ST_SINS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_SINS =>
|
when ST_SINS =>
|
if event3_1 then
|
if event3_1 then
|
current_state_3 <= ST_SIIS;
|
current_state_3 <= ST_SIIS;
|
elsif event3_4 then
|
elsif event3_4 then
|
current_state_3 <= ST_SIAS;
|
current_state_3 <= ST_SIAS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when others =>
|
when others =>
|
current_state_3 <= ST_SIIS;
|
current_state_3 <= ST_SIIS;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- state machine process - C_STATE_4
|
-- state machine process - C_STATE_4
|
process(pon, clk) begin
|
process(pon, clk) begin
|
-- async reset
|
-- async reset
|
if pon='1' then
|
if pon='1' then
|
timer_b_1 <= 0;
|
timer_b_1 <= 0;
|
current_state_4 <= ST_SRIS;
|
current_state_4 <= ST_SRIS;
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
|
|
-- timer
|
-- timer
|
if timer_b_1 < TIMER_B_MAX then
|
if timer_b_1 < TIMER_B_MAX then
|
timer_b_1 <= timer_b_1 + 1;
|
timer_b_1 <= timer_b_1 + 1;
|
end if;
|
end if;
|
|
|
-- state machine
|
-- state machine
|
case current_state_4 is
|
case current_state_4 is
|
------------------
|
------------------
|
when ST_SRIS =>
|
when ST_SRIS =>
|
if event4_1 then
|
if event4_1 then
|
-- no state change
|
-- no state change
|
elsif event4_2 then
|
elsif event4_2 then
|
timer_b_1 <= 0;
|
timer_b_1 <= 0;
|
current_state_4 <= ST_SRAS;
|
current_state_4 <= ST_SRAS;
|
elsif event4_3 then
|
elsif event4_3 then
|
current_state_4 <= ST_SRNS;
|
current_state_4 <= ST_SRNS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_SRAS =>
|
when ST_SRAS =>
|
if event4_1 then
|
if event4_1 then
|
current_state_4 <= ST_SRIS;
|
current_state_4 <= ST_SRIS;
|
elsif event4_5 then
|
elsif event4_5 then
|
current_state_4 <= ST_SRNS;
|
current_state_4 <= ST_SRNS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_SRNS =>
|
when ST_SRNS =>
|
if event4_1 then
|
if event4_1 then
|
current_state_4 <= ST_SRIS;
|
current_state_4 <= ST_SRIS;
|
elsif event4_4 then
|
elsif event4_4 then
|
timer_b_1 <= 0;
|
timer_b_1 <= 0;
|
current_state_4 <= ST_SRAS;
|
current_state_4 <= ST_SRAS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when others =>
|
when others =>
|
current_state_4 <= ST_SRIS;
|
current_state_4 <= ST_SRIS;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- state machine process - C_STATE_5
|
-- state machine process - C_STATE_5
|
process(pon, clk) begin
|
process(pon, clk) begin
|
-- async reset
|
-- async reset
|
if pon='1' then
|
if pon='1' then
|
current_state_5 <= ST_SNAS;
|
current_state_5 <= ST_SNAS;
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
-- state machine
|
-- state machine
|
case current_state_5 is
|
case current_state_5 is
|
------------------
|
------------------
|
when ST_SNAS =>
|
when ST_SNAS =>
|
if event5_1 then
|
if event5_1 then
|
current_state_5 <= ST_SACS;
|
current_state_5 <= ST_SACS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_SACS =>
|
when ST_SACS =>
|
if event5_2 then
|
if event5_2 then
|
current_state_5 <= ST_SNAS;
|
current_state_5 <= ST_SNAS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when others =>
|
when others =>
|
current_state_5 <= ST_SNAS;
|
current_state_5 <= ST_SNAS;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- events
|
-- events
|
event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;
|
event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;
|
event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;
|
event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;
|
event1_3 <= STRS='0';
|
event1_3 <= STRS='0';
|
event1_4 <= ATN_in='0';
|
event1_4 <= ATN_in='0';
|
event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';
|
event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';
|
event1_6 <= SDYS='0' and STRS='0' and gts='1';
|
event1_6 <= SDYS='0' and STRS='0' and gts='1';
|
event1_7 <= rpp='1';
|
event1_7 <= rpp='1';
|
event1_8 <= timer_T9Expired and rpp='0';
|
event1_8 <= timer_T9Expired and rpp='0';
|
event1_9 <= (tcs='1' and ANRS='1') or tca='1';
|
event1_9 <= (tcs='1' and ANRS='1') or tca='1';
|
event1_10 <= timer_T7Expired;
|
event1_10 <= timer_T7Expired;
|
event1_11 <= timer_T6Expired;
|
event1_11 <= timer_T6Expired;
|
event1_12 <= rpp='0';
|
event1_12 <= rpp='0';
|
|
|
event2_1 <= SRQ_in='1';
|
event2_1 <= SRQ_in='1';
|
event2_2 <= SRQ_in='0';
|
event2_2 <= SRQ_in='0';
|
|
|
event3_1 <= current_state_5/=ST_SACS;
|
event3_1 <= current_state_5/=ST_SACS;
|
event3_2 <= current_state_5=ST_SACS and sic='1';
|
event3_2 <= current_state_5=ST_SACS and sic='1';
|
event3_3 <= current_state_5=ST_SACS and sic='0';
|
event3_3 <= current_state_5=ST_SACS and sic='0';
|
event3_4 <= sic='1';
|
event3_4 <= sic='1';
|
event3_5 <= sic='0' and timer_T8Expired;
|
event3_5 <= sic='0' and timer_T8Expired;
|
|
|
event4_1 <= current_state_5/=ST_SACS;
|
event4_1 <= current_state_5/=ST_SACS;
|
event4_2 <= current_state_5=ST_SACS and sre='1';
|
event4_2 <= current_state_5=ST_SACS and sre='1';
|
event4_3 <= current_state_5=ST_SACS and sre='0';
|
event4_3 <= current_state_5=ST_SACS and sre='0';
|
event4_4 <= sre='1';
|
event4_4 <= sre='1';
|
event4_5 <= sre='0' and timer_T8_1Expired;
|
event4_5 <= sre='0' and timer_T8_1Expired;
|
|
|
event5_1 <= rsc='1';
|
event5_1 <= rsc='1';
|
event5_2 <= rsc='0';
|
event5_2 <= rsc='0';
|
|
|
-- timers
|
-- timers
|
timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;
|
timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;
|
timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;
|
timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;
|
timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;
|
timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;
|
|
|
timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;
|
timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;
|
timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;
|
timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;
|
|
|
|
|
CPPS <= to_stdl(current_state_1 = ST_CPPS);
|
CPPS <= to_stdl(current_state_1 = ST_CPPS);
|
CSRS <= to_stdl(current_state_2 = ST_CSRS);
|
CSRS <= to_stdl(current_state_2 = ST_CSRS);
|
CSBS <= to_stdl(current_state_1 = ST_CSBS);
|
CSBS <= to_stdl(current_state_1 = ST_CSBS);
|
CACS <= to_stdl(current_state_1 = ST_CACS);
|
CACS <= to_stdl(current_state_1 = ST_CACS);
|
SACS <= to_stdl(current_state_5 = ST_SACS);
|
SACS <= to_stdl(current_state_5 = ST_SACS);
|
|
|
-- CTRS
|
-- CTRS
|
with current_state_1 select
|
with current_state_1 select
|
CTRS <=
|
CTRS <=
|
'1' when ST_CTRS,
|
'1' when ST_CTRS,
|
'0' when others;
|
'0' when others;
|
|
|
-- ATN
|
-- ATN
|
with current_state_1 select
|
with current_state_1 select
|
ATN_out <=
|
ATN_out <=
|
'0' when ST_CIDS,
|
'0' when ST_CIDS,
|
'0' when ST_CADS,
|
'0' when ST_CADS,
|
'0' when ST_CSBS,
|
'0' when ST_CSBS,
|
'1' when others;
|
'1' when others;
|
|
|
-- IDY_out
|
-- IDY_out
|
with current_state_1 select
|
with current_state_1 select
|
IDY_out <=
|
IDY_out <=
|
'1' when ST_CPWS,
|
'1' when ST_CPWS,
|
'1' when ST_CPPS,
|
'1' when ST_CPPS,
|
'0' when others;
|
'0' when others;
|
|
|
-- TCT
|
-- TCT
|
with current_state_1 select
|
with current_state_1 select
|
TCT_out <=
|
TCT_out <=
|
'1' when ST_CTRS,
|
'1' when ST_CTRS,
|
'0' when others;
|
'0' when others;
|
|
|
-- IFC
|
-- IFC
|
with current_state_3 select
|
with current_state_3 select
|
IFC_out <=
|
IFC_out <=
|
'1' when ST_SIAS,
|
'1' when ST_SIAS,
|
'0' when others;
|
'0' when others;
|
|
|
-- REN
|
-- REN
|
with current_state_4 select
|
with current_state_4 select
|
REN_out <=
|
REN_out <=
|
'1' when ST_SRAS,
|
'1' when ST_SRAS,
|
'0' when others;
|
'0' when others;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
