// rtl program for i2c_gpio.v
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// rtl program for i2c_gpio.v
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`define P0_P9_OP 4'b1010 //0x0A
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`define P0_P9_OP 4'b1010 //0x0A
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//`define P0_P3_OP 4'b1011 //0x0B
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//`define P0_P3_OP 4'b1011 //0x0B
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`define P0_P3_OP 4'b0111 //0x07
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`define P0_P3_OP 4'b0111 //0x07
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`define P4_P7_OP 4'b1110 //0xE0
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`define P4_P7_OP 4'b1110 //0xE0
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//`define P8_P9_OP 4'b1101 //0x0D
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//`define P8_P9_OP 4'b1101 //0x0D
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module i2c_gpio(clk, cs, sr_in, sda_out, sr_out, gpio);
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module i2c_gpio(clk, cs, sr_in, sda_out, sr_out, gpio);
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input clk,cs;
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input clk,cs;
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input sr_in;
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input sr_in;
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output sda_out;
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output sda_out;
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output sr_out;
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output sr_out;
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output [7:0] gpio;
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output [7:0] gpio;
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reg [7:0] sr;
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reg [7:0] sr;
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reg [7:0] addrreg;
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reg [7:0] addrreg;
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reg sda_out;
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reg sda_out;
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reg sr_out ;
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reg sr_out ;
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reg [7:0] gpio;
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reg [7:0] gpio;
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reg [7:0] ram;
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reg [7:0] ram;
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wire [3:0] addr;
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wire [3:0] addr;
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wire [3:0] data;
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wire [3:0] data;
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assign addr = sr[3:0];
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assign addr = sr[3:0];
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assign data = sr[7:4];
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assign data = sr[7:4];
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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if (cs == 1'b0)
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if (cs == 1'b0)
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begin
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begin
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sr_out <= sr[7];
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sr_out <= sr[7];
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sr[7:1] <= sr[6:0];
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sr[7:1] <= sr[6:0];
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sr[0] <= sr_in;
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sr[0] <= sr_in;
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end
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end
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begin
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begin
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if (addr[0] == 1'b0) // low bit zero - start bit
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if (addr[0] == 1'b0) // low bit zero - start bit
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begin
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begin
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if(addr[3:0] == 4'h0E) // 0xD is the address of the slave
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if(addr[3:0] == 4'h0E) // 0xD is the address of the slave
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begin
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begin
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sda_out = 1'b1; // high bit for Acknowledge to master
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sda_out = 1'b1; // high bit for Acknowledge to master
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if(addr[3]== 1'b1) // high bit for write
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if(addr[3]== 1'b1) // high bit for write
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begin
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begin
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case (addr[3:0]) // data[3:0] for data write
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case (addr[3:0]) // data[3:0] for data write
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// `P0_P9_OP : gpio[7:4] <= {sr[0], sr[1], sr[2], sr[3], sr[4], sr[5], sr[6], sr[7]};
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// `P0_P9_OP : gpio[7:4] <= {sr[0], sr[1], sr[2], sr[3], sr[4], sr[5], sr[6], sr[7]};
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`P0_P3_OP : gpio[3:0] <= {data[0], data[1], data[2], data[3]};
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`P0_P3_OP : gpio[3:0] <= {data[0], data[1], data[2], data[3]};
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`P4_P7_OP : gpio[3:0] <= {data[3], data[2], data[1], data[0]};
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`P4_P7_OP : gpio[3:0] <= {data[3], data[2], data[1], data[0]};
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// `P8_P9_OP : gpio[9:8] <= {sr[0], sr[0]};
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// `P8_P9_OP : gpio[9:8] <= {sr[0], sr[0]};
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// default : gpio[7:0] <= {sr[0], sr[0], sr[0], sr[0],
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// default : gpio[7:0] <= {sr[0], sr[0], sr[0], sr[0],
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// sr[0], sr[0], sr[0], sr[0]};
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// sr[0], sr[0], sr[0], sr[0]};
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endcase
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endcase
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sda_out = 1'b1; // high bit for Acknowledge master
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sda_out = 1'b1; // high bit for Acknowledge master
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end
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end
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else
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else
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begin
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begin
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sda_out = 1'bz;
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sda_out = 1'bz;
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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