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--==============================================================================
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--==============================================================================
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-- |
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-- |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- |
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-- |
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-- Module: Byte layer FSM (master mode). |
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-- Module: Byte layer FSM (master mode). |
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-- Version: |
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-- Version: |
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-- 1.0, April 29, 2016 |
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-- 1.0, April 29, 2016 |
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-- |
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-- |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- |
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-- |
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--==============================================================================
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--==============================================================================
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--==============================================================================
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--==============================================================================
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- All rights reserved. |
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-- All rights reserved. |
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-- |
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-- |
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-- Redistribution and use in source and binary forms, with or without |
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-- Redistribution and use in source and binary forms, with or without |
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-- modification, are permitted provided that the following conditions are met: |
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-- modification, are permitted provided that the following conditions are met: |
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-- |
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-- |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- this list of conditions and the following disclaimer. |
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-- this list of conditions and the following disclaimer. |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- notice, this list of conditions and the following disclaimer in the |
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-- notice, this list of conditions and the following disclaimer in the |
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-- documentation and/or other materials provided with the distribution. |
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-- documentation and/or other materials provided with the distribution. |
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-- |
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-- |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- POSSIBILITY OF SUCH DAMAGE. |
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-- POSSIBILITY OF SUCH DAMAGE. |
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--==============================================================================
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--==============================================================================
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|
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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use work.iicmb_pkg.all;
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use work.iicmb_pkg.all;
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use work.iicmb_int_pkg.all;
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use work.iicmb_int_pkg.all;
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|
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--==============================================================================
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--==============================================================================
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entity mbyte is
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entity mbyte is
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generic
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generic
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(
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(
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------------------------------------
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------------------------------------
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g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses
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g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses
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g_f_clk : real := 100000.0 -- Frequency of system clock 'clk' (in kHz)
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g_f_clk : real := 100000.0 -- Frequency of system clock 'clk' (in kHz)
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------------------------------------
|
------------------------------------
|
);
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);
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port
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port
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(
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(
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------------------------------------
|
------------------------------------
|
clk : in std_logic; -- Clock
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clk : in std_logic; -- Clock
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s_rst : in std_logic; -- Synchronous reset (active high)
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s_rst : in std_logic; -- Synchronous reset (active high)
|
------------------------------------
|
------------------------------------
|
------------------------------------
|
------------------------------------
|
captured : out std_logic := '0'; -- 'Bus is captured' indication (captured = high)
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captured : out std_logic := '0'; -- 'Bus is captured' indication (captured = high)
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busy : in std_logic; -- 'Bus is busy' indication (busy = high)
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busy : in std_logic; -- 'Bus is busy' indication (busy = high)
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bus_id : out natural range 0 to g_bus_num - 1 := 0; -- Bus selector
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bus_id : out natural range 0 to g_bus_num - 1 := 0; -- Bus selector
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fsm_state : out std_logic_vector(3 downto 0); -- FSM state
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fsm_state : out std_logic_vector(3 downto 0); -- FSM state
|
------------------------------------
|
------------------------------------
|
------------------------------------
|
------------------------------------
|
mcmd_wr : in std_logic; -- Byte command write (active high)
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mcmd_wr : in std_logic; -- Byte command write (active high)
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mcmd_id : in std_logic_vector(2 downto 0); -- Byte command ID
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mcmd_id : in std_logic_vector(2 downto 0); -- Byte command ID
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mcmd_data : in std_logic_vector(7 downto 0); -- Byte command data
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mcmd_data : in std_logic_vector(7 downto 0); -- Byte command data
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------------------------------------
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------------------------------------
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------------------------------------
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------------------------------------
|
mrsp_wr : out std_logic := '0'; -- Byte command response write (active high)
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mrsp_wr : out std_logic := '0'; -- Byte command response write (active high)
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mrsp_id : out std_logic_vector(2 downto 0) := mrsp_done; -- Byte command response control bit
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mrsp_id : out std_logic_vector(2 downto 0) := mrsp_done; -- Byte command response control bit
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mrsp_data : out std_logic_vector(7 downto 0); -- Byte command response data
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mrsp_data : out std_logic_vector(7 downto 0); -- Byte command response data
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------------------------------------
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------------------------------------
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------------------------------------
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------------------------------------
|
mbc_wr : out std_logic := '0'; -- Bit command write (active high)
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mbc_wr : out std_logic := '0'; -- Bit command write (active high)
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mbc : out mbc_type := mbc_stop; -- Bit command
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mbc : out mbc_type := mbc_stop; -- Bit command
|
------------------------------------
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------------------------------------
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------------------------------------
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------------------------------------
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mbr_wr : in std_logic; -- Bit command response write (active high)
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mbr_wr : in std_logic; -- Bit command response write (active high)
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mbr : in mbr_type -- Bit command response
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mbr : in mbr_type -- Bit command response
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------------------------------------
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------------------------------------
|
);
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);
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end entity mbyte;
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end entity mbyte;
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--==============================================================================
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--==============================================================================
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|
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--==============================================================================
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--==============================================================================
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architecture rtl of mbyte is
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architecture rtl of mbyte is
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|
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constant c_cycle_cnt_inc : integer := 1;
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constant c_cycle_cnt_inc : integer := 1;
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constant c_cycle_cnt_max : integer := integer(g_f_clk);
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constant c_cycle_cnt_max : integer := integer(g_f_clk);
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constant c_cycle_cnt_thr : integer := c_cycle_cnt_max - c_cycle_cnt_inc;
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constant c_cycle_cnt_thr : integer := c_cycle_cnt_max - c_cycle_cnt_inc;
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|
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type state_type is
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type state_type is
|
(
|
(
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s_idle, -- Idle
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s_idle, -- Idle
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s_bus_taken, -- Bus is taken
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s_bus_taken, -- Bus is taken
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s_start_pending, -- Waiting for right moment to capture bus
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s_start_pending, -- Waiting for right moment to capture bus
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s_start, -- Sending Start Condition (Capturing the bus)
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s_start, -- Sending Start Condition (Capturing the bus)
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s_stop, -- Sending Stop Condition (Releasing the bus)
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s_stop, -- Sending Stop Condition (Releasing the bus)
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s_write, -- Sending a byte
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s_write, -- Sending a byte
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s_read, -- Receiving a byte
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s_read, -- Receiving a byte
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s_wait -- Receiving a byte
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s_wait -- Receiving a byte
|
);
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);
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|
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Converting states to std_logic_vector
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-- Converting states to std_logic_vector
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function to_std_logic_vector(a : state_type) return std_logic_vector is
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function to_std_logic_vector(a : state_type) return std_logic_vector is
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begin
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begin
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case (a) is
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case (a) is
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when s_idle => return "0000";
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when s_idle => return "0000";
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when s_bus_taken => return "0001";
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when s_bus_taken => return "0001";
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when s_start_pending => return "0010";
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when s_start_pending => return "0010";
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when s_start => return "0011";
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when s_start => return "0011";
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when s_stop => return "0100";
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when s_stop => return "0100";
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when s_write => return "0101";
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when s_write => return "0101";
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when s_read => return "0110";
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when s_read => return "0110";
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when s_wait => return "0111";
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when s_wait => return "0111";
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end case;
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end case;
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end function to_std_logic_vector;
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end function to_std_logic_vector;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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|
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signal state : state_type := s_idle;
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signal state : state_type := s_idle;
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signal cnt : integer range 0 to 8 := 0;
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signal cnt : integer range 0 to 8 := 0;
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signal sbuf : std_logic_vector(7 downto 0) := (others => '0');
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signal sbuf : std_logic_vector(7 downto 0) := (others => '0');
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signal ack : std_logic := '0';
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signal ack : std_logic := '0';
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signal cycle_cnt : integer range 0 to c_cycle_cnt_max := 0;
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signal cycle_cnt : integer range 0 to c_cycle_cnt_max := 0;
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signal us_cnt : unsigned( 7 downto 0) := to_unsigned(0, 8);
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signal ms_cnt : unsigned( 7 downto 0) := to_unsigned(0, 8);
|
|
|
begin
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begin
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|
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mrsp_data <= sbuf;
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mrsp_data <= sbuf;
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fsm_state <= to_std_logic_vector(state);
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fsm_state <= to_std_logic_vector(state);
|
|
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Main FSM:
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-- Main FSM:
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main_fsm_proc:
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main_fsm_proc:
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process(clk)
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process(clk)
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---------
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---------
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procedure bit_command(a : mbc_type) is
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procedure bit_command(a : mbc_type) is
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begin
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begin
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mbc_wr <= '1';
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mbc_wr <= '1';
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mbc <= a;
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mbc <= a;
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end procedure bit_command;
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end procedure bit_command;
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---------
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---------
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---------
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---------
|
procedure bit_command(a : std_logic) is
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procedure bit_command(a : std_logic) is
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begin
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begin
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mbc_wr <= '1';
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mbc_wr <= '1';
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if (a = '0') then
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if (a = '0') then
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mbc <= mbc_write_0;
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mbc <= mbc_write_0;
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else
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else
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mbc <= mbc_write_1;
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mbc <= mbc_write_1;
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end if;
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end if;
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end procedure bit_command;
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end procedure bit_command;
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---------
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---------
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---------
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---------
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function get_bit(a : mbr_type) return std_logic is
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function get_bit(a : mbr_type) return std_logic is
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begin
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begin
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if (a = mbr_bit_0) then
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if (a = mbr_bit_0) then
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return '0';
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return '0';
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else
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else
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return '1';
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return '1';
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end if;
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end if;
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end function get_bit;
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end function get_bit;
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---------
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---------
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---------
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---------
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procedure byte_response(a : std_logic_vector(2 downto 0)) is
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procedure byte_response(a : std_logic_vector(2 downto 0)) is
|
begin
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begin
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mrsp_wr <= '1';
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mrsp_wr <= '1';
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mrsp_id <= a;
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mrsp_id <= a;
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end procedure byte_response;
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end procedure byte_response;
|
---------
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---------
|
variable v_bus_id : integer range 0 to 15;
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variable v_bus_id : integer range 0 to 15;
|
begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
|
if (s_rst = '1') then
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if (s_rst = '1') then
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state <= s_idle;
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state <= s_idle;
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cnt <= 0;
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cnt <= 0;
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sbuf <= (others => '0');
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sbuf <= (others => '0');
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ack <= '0';
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ack <= '0';
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mbc_wr <= '0';
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mbc_wr <= '0';
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mbc <= mbc_stop;
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mbc <= mbc_stop;
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mrsp_wr <= '0';
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mrsp_wr <= '0';
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mrsp_id <= mrsp_done;
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mrsp_id <= mrsp_done;
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bus_id <= 0;
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bus_id <= 0;
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captured <= '0';
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captured <= '0';
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cycle_cnt <= 0;
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cycle_cnt <= 0;
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us_cnt <= to_unsigned(0, 8);
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ms_cnt <= to_unsigned(0, 8);
|
else
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else
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-- Default:
|
-- Default:
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mbc_wr <= '0';
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mbc_wr <= '0';
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mrsp_wr <= '0';
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mrsp_wr <= '0';
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------
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------
|
|
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case (state) is
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case (state) is
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-- 'Idle' state ----------------------------------
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-- 'Idle' state ----------------------------------
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when s_idle =>
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when s_idle =>
|
if (mcmd_wr = '1') then
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if (mcmd_wr = '1') then
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case (mcmd_id) is
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case (mcmd_id) is
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when mcmd_start =>
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when mcmd_start =>
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-- Begin procedure of bus capturing
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-- Begin procedure of bus capturing
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state <= s_start_pending;
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state <= s_start_pending;
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when mcmd_set_bus =>
|
when mcmd_set_bus =>
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-- Switch to another bus
|
-- Switch to another bus
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state <= s_idle;
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state <= s_idle;
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v_bus_id := to_integer(unsigned(mcmd_data(3 downto 0)));
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v_bus_id := to_integer(unsigned(mcmd_data(3 downto 0)));
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if (v_bus_id > (g_bus_num - 1)) then
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if (v_bus_id > (g_bus_num - 1)) then
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byte_response(mrsp_error);
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byte_response(mrsp_error);
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else
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else
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bus_id <= v_bus_id;
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bus_id <= v_bus_id;
|
byte_response(mrsp_done);
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byte_response(mrsp_done);
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end if;
|
end if;
|
when mcmd_wait =>
|
when mcmd_wait =>
|
-- Wait for specified period:
|
-- Wait for specified period:
|
state <= s_wait;
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state <= s_wait;
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cycle_cnt <= 0;
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cycle_cnt <= 0;
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us_cnt <= unsigned(mcmd_data);
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ms_cnt <= unsigned(mcmd_data);
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when others =>
|
when others =>
|
-- Other commands are rejected in 'Idle' state
|
-- Other commands are rejected in 'Idle' state
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state <= s_idle;
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state <= s_idle;
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byte_response(mrsp_error);
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byte_response(mrsp_error);
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end case;
|
end case;
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cnt <= 0;
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cnt <= 0;
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end if;
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end if;
|
captured <= '0';
|
captured <= '0';
|
-- 'Idle' state ----------------------------------
|
-- 'Idle' state ----------------------------------
|
|
|
-- 'Wait' state ----------------------------------
|
-- 'Wait' state ----------------------------------
|
when s_wait =>
|
when s_wait =>
|
captured <= '0';
|
captured <= '0';
|
if (us_cnt = 0) then
|
if (ms_cnt = 0) then
|
state <= s_idle;
|
state <= s_idle;
|
byte_response(mrsp_done);
|
byte_response(mrsp_done);
|
else
|
else
|
if (cycle_cnt < c_cycle_cnt_thr) then
|
if (cycle_cnt < c_cycle_cnt_thr) then
|
cycle_cnt <= cycle_cnt + c_cycle_cnt_inc;
|
cycle_cnt <= cycle_cnt + c_cycle_cnt_inc;
|
else
|
else
|
cycle_cnt <= cycle_cnt - c_cycle_cnt_thr;
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cycle_cnt <= cycle_cnt - c_cycle_cnt_thr;
|
us_cnt <= us_cnt - 1;
|
ms_cnt <= ms_cnt - 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
-- 'Wait' state ----------------------------------
|
-- 'Wait' state ----------------------------------
|
|
|
-- 'Bus is Taken' state --------------------------
|
-- 'Bus is Taken' state --------------------------
|
when s_bus_taken =>
|
when s_bus_taken =>
|
if (mcmd_wr = '1') then
|
if (mcmd_wr = '1') then
|
case (mcmd_id) is
|
case (mcmd_id) is
|
when mcmd_start =>
|
when mcmd_start =>
|
-- Generate Repeated Start condition
|
-- Generate Repeated Start condition
|
state <= s_start;
|
state <= s_start;
|
bit_command(mbc_start);
|
bit_command(mbc_start);
|
when mcmd_read_ack =>
|
when mcmd_read_ack =>
|
-- Byte reading with acknowledge
|
-- Byte reading with acknowledge
|
state <= s_read;
|
state <= s_read;
|
ack <= '0';
|
ack <= '0';
|
bit_command(mbc_read);
|
bit_command(mbc_read);
|
when mcmd_read_nak =>
|
when mcmd_read_nak =>
|
-- Byte reading with not-acknowledge
|
-- Byte reading with not-acknowledge
|
state <= s_read;
|
state <= s_read;
|
ack <= '1';
|
ack <= '1';
|
bit_command(mbc_read);
|
bit_command(mbc_read);
|
when mcmd_stop =>
|
when mcmd_stop =>
|
-- Issue Stop condition
|
-- Issue Stop condition
|
state <= s_stop;
|
state <= s_stop;
|
bit_command(mbc_stop);
|
bit_command(mbc_stop);
|
when mcmd_write =>
|
when mcmd_write =>
|
-- Byte writing
|
-- Byte writing
|
state <= s_write;
|
state <= s_write;
|
sbuf <= mcmd_data(6 downto 0) & '0';
|
sbuf <= mcmd_data(6 downto 0) & '0';
|
bit_command(mcmd_data(7));
|
bit_command(mcmd_data(7));
|
when others =>
|
when others =>
|
-- Other commands are rejected in 'Bus Is Taken' state
|
-- Other commands are rejected in 'Bus Is Taken' state
|
state <= s_bus_taken;
|
state <= s_bus_taken;
|
byte_response(mrsp_error);
|
byte_response(mrsp_error);
|
end case;
|
end case;
|
cnt <= 0;
|
cnt <= 0;
|
end if;
|
end if;
|
captured <= '1';
|
captured <= '1';
|
-- 'Bus is Taken' state --------------------------
|
-- 'Bus is Taken' state --------------------------
|
|
|
-- 'Start is Pending' state ----------------------
|
-- 'Start is Pending' state ----------------------
|
when s_start_pending =>
|
when s_start_pending =>
|
captured <= '0';
|
captured <= '0';
|
if (busy = '0') then
|
if (busy = '0') then
|
state <= s_start;
|
state <= s_start;
|
bit_command(mbc_start);
|
bit_command(mbc_start);
|
end if;
|
end if;
|
-- 'Start is Pending' state ----------------------
|
-- 'Start is Pending' state ----------------------
|
|
|
-- 'Start' state ---------------------------------
|
-- 'Start' state ---------------------------------
|
when s_start =>
|
when s_start =>
|
if (mbr_wr = '1') then
|
if (mbr_wr = '1') then
|
if (mbr = mbr_done) then
|
if (mbr = mbr_done) then
|
state <= s_bus_taken;
|
state <= s_bus_taken;
|
captured <= '1';
|
captured <= '1';
|
byte_response(mrsp_done);
|
byte_response(mrsp_done);
|
else
|
else
|
-- (mbr = mbr_arb_lost)
|
-- (mbr = mbr_arb_lost)
|
state <= s_idle;
|
state <= s_idle;
|
captured <= '0';
|
captured <= '0';
|
byte_response(mrsp_arb_lost);
|
byte_response(mrsp_arb_lost);
|
end if;
|
end if;
|
end if;
|
end if;
|
-- 'Start' state ---------------------------------
|
-- 'Start' state ---------------------------------
|
|
|
-- 'Stop' state ----------------------------------
|
-- 'Stop' state ----------------------------------
|
when s_stop =>
|
when s_stop =>
|
captured <= '1';
|
captured <= '1';
|
if (mbr_wr = '1') then
|
if (mbr_wr = '1') then
|
state <= s_idle;
|
state <= s_idle;
|
captured <= '0';
|
captured <= '0';
|
byte_response(mrsp_done);
|
byte_response(mrsp_done);
|
end if;
|
end if;
|
-- 'Stop' state ----------------------------------
|
-- 'Stop' state ----------------------------------
|
|
|
-- 'Byte Reading' state --------------------------
|
-- 'Byte Reading' state --------------------------
|
when s_read =>
|
when s_read =>
|
captured <= '1';
|
captured <= '1';
|
if (mbr_wr = '1') then
|
if (mbr_wr = '1') then
|
case (cnt) is
|
case (cnt) is
|
when 8 =>
|
when 8 =>
|
if (mbr = mbr_done) then
|
if (mbr = mbr_done) then
|
-- Return to 'Bus Is Taken' state and
|
-- Return to 'Bus Is Taken' state and
|
-- respond with a byte of data.
|
-- respond with a byte of data.
|
state <= s_bus_taken;
|
state <= s_bus_taken;
|
byte_response(mrsp_byte);
|
byte_response(mrsp_byte);
|
else
|
else
|
-- (mbr = mbr_arb_lost)
|
-- (mbr = mbr_arb_lost)
|
state <= s_idle;
|
state <= s_idle;
|
captured <= '0';
|
captured <= '0';
|
byte_response(mrsp_arb_lost);
|
byte_response(mrsp_arb_lost);
|
end if;
|
end if;
|
when others =>
|
when others =>
|
if (mbr = mbr_error) then
|
if (mbr = mbr_error) then
|
state <= s_idle;
|
state <= s_idle;
|
captured <= '0';
|
captured <= '0';
|
byte_response(mrsp_error);
|
byte_response(mrsp_error);
|
else
|
else
|
-- (mbr = mbr_bit_0)or(mbr = mbr_bit_1)
|
-- (mbr = mbr_bit_0)or(mbr = mbr_bit_1)
|
sbuf <= sbuf(6 downto 0) & get_bit(mbr);
|
sbuf <= sbuf(6 downto 0) & get_bit(mbr);
|
cnt <= cnt + 1;
|
cnt <= cnt + 1;
|
if (cnt = 7) then
|
if (cnt = 7) then
|
-- Write Ack/Nak
|
-- Write Ack/Nak
|
bit_command(ack);
|
bit_command(ack);
|
else
|
else
|
-- Read a bit
|
-- Read a bit
|
bit_command(mbc_read);
|
bit_command(mbc_read);
|
end if;
|
end if;
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
-- 'Byte Reading' state --------------------------
|
-- 'Byte Reading' state --------------------------
|
|
|
-- 'Byte Writing' state --------------------------
|
-- 'Byte Writing' state --------------------------
|
when s_write =>
|
when s_write =>
|
captured <= '1';
|
captured <= '1';
|
if (mbr_wr = '1') then
|
if (mbr_wr = '1') then
|
case (cnt) is
|
case (cnt) is
|
when 8 =>
|
when 8 =>
|
state <= s_bus_taken;
|
state <= s_bus_taken;
|
if (mbr = mbr_error) then
|
if (mbr = mbr_error) then
|
-- Something went wrong
|
-- Something went wrong
|
state <= s_idle;
|
state <= s_idle;
|
captured <= '0';
|
captured <= '0';
|
byte_response(mrsp_error);
|
byte_response(mrsp_error);
|
elsif (mbr = mbr_bit_0) then
|
elsif (mbr = mbr_bit_0) then
|
-- Write is acknowledged
|
-- Write is acknowledged
|
byte_response(mrsp_done);
|
byte_response(mrsp_done);
|
else
|
else
|
-- Write is not acknowledged
|
-- Write is not acknowledged
|
byte_response(mrsp_nak);
|
byte_response(mrsp_nak);
|
end if;
|
end if;
|
when others =>
|
when others =>
|
if (mbr = mbr_done) then
|
if (mbr = mbr_done) then
|
sbuf <= sbuf(6 downto 0) & '0';
|
sbuf <= sbuf(6 downto 0) & '0';
|
cnt <= cnt + 1;
|
cnt <= cnt + 1;
|
if (cnt = 7) then
|
if (cnt = 7) then
|
-- Read Ack/Nak
|
-- Read Ack/Nak
|
bit_command(mbc_read);
|
bit_command(mbc_read);
|
else
|
else
|
-- Write a bit
|
-- Write a bit
|
bit_command(sbuf(7));
|
bit_command(sbuf(7));
|
end if;
|
end if;
|
else
|
else
|
-- (mbr = mbr_arb_lost)
|
-- (mbr = mbr_arb_lost)
|
state <= s_idle;
|
state <= s_idle;
|
captured <= '0';
|
captured <= '0';
|
byte_response(mrsp_arb_lost);
|
byte_response(mrsp_arb_lost);
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
-- 'Byte Writing' state --------------------------
|
-- 'Byte Writing' state --------------------------
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process main_fsm_proc;
|
end process main_fsm_proc;
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
end architecture rtl;
|
end architecture rtl;
|
--==============================================================================
|
--==============================================================================
|
|
|
|
|