/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 22:22:43 01/10/2011
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Creation date: 22:22:43 01/10/2011
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$LastChangedDate: 2011-04-17 23:31:29 +0200 (Sun, 17 Apr 2011) $
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$LastChangedDate: 2011-04-18 12:57:36 +0200 (Mon, 18 Apr 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 19 $
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$LastChangedRevision: 20 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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module Iso7816_3_t0_analyzer
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module Iso7816_3_t0_analyzer
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#(
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#(
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parameter DIVIDER_WIDTH = 1
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parameter DIVIDER_WIDTH = 1
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)
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)
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(
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(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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input wire isoSioTerm,
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input wire isoSioTerm,
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input wire isoSioCard,
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input wire isoSioCard,
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input wire useDirectionProbe,//if 1, isoSioTerm and isoSioCard must be connected to Iso7816_directionProbe outputs
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input wire useDirectionProbe,//if 1, isoSioTerm and isoSioCard must be connected to Iso7816_directionProbe outputs
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output reg [3:0] fiCode,
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output reg [3:0] fiCode,
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output reg [3:0] diCode,
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output reg [3:0] diCode,
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output wire [12:0] fi,
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output wire [12:0] fi,
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output wire [7:0] di,
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output wire [7:0] di,
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output wire [12:0] cyclesPerEtu,
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output wire [12:0] cyclesPerEtu,
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output wire [7:0] fMax,
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output wire [7:0] fMax,
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output wire isActivated,
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output wire isActivated,
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output wire tsReceived,
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output wire tsReceived,
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output wire tsError,
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output wire tsError,
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output wire useIndirectConvention,
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output wire useIndirectConvention,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output reg [3:0] atrK,//number of historical bytes
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output reg [3:0] atrK,//number of historical bytes
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output reg atrHasTck,
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output reg atrHasTck,
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output reg atrCompleted,
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output reg atrCompleted,
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output reg useT0,
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output reg useT0,
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output reg useT1,
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output reg useT1,
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output reg useT15,
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output reg useT15,
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output reg waitCardTx,
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output reg waitCardTx,
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output reg waitTermTx,
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output reg waitTermTx,
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output wire cardTx,
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output wire cardTx,
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output wire termTx,
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output wire termTx,
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output wire guardTime,
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output wire guardTime,
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output wire overrunError,
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output wire overrunError,
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output wire frameError,
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output wire frameError,
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output reg comOnGoing,
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output reg comOnGoing,
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output reg [7:0] lastByte,
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output reg [7:0] lastByte,
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output reg [31:0] bytesCnt
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output reg [31:0] bytesCnt
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);
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);
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localparam CLOCK_PER_BIT_WIDTH = 4'd13;
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localparam CLOCK_PER_BIT_WIDTH = 4'd13;
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wire isoSio = isoSioTerm & isoSioCard;
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wire isoSio = isoSioTerm & isoSioCard;
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [7:0] buffer[256+5:0];
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reg [7:0] buffer[256+5:0];
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localparam CLA_I= 8*4;
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localparam CLA_I= 8*4;
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localparam INS_I= 8*3;
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localparam INS_I= 8*3;
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localparam P1_I = 8*2;
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localparam P1_I = 8*2;
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localparam P2_I = 8*1;
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localparam P2_I = 8*1;
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localparam P3_I = 0;
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localparam P3_I = 0;
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reg [CLA_I+7:0] tpduHeader;
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reg [CLA_I+7:0] tpduHeader;
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localparam PPS0_I= CLA_I;
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localparam PPS0_I= CLA_I;
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localparam PPS1_I= INS_I;
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localparam PPS1_I= INS_I;
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localparam PPS2_I= P1_I;
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localparam PPS2_I= P1_I;
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localparam PPS3_I= P2_I;
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localparam PPS3_I= P2_I;
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//wire COM_clk=isoClk;
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//wire COM_clk=isoClk;
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//integer COM_errorCnt;
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//integer COM_errorCnt;
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//wire txPending=1'b0;
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//wire txPending=1'b0;
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//wire txRun=1'b0;
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//wire txRun=1'b0;
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign overrunErrorFlag = overrunError;
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assign overrunErrorFlag = overrunError;
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assign frameErrorFlag = frameError;
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assign frameErrorFlag = frameError;
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wire [7:0] rxData;
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wire [7:0] rxData;
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reg ackFlags;
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reg ackFlags;
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wire msbFirst = useIndirectConvention;
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wire msbFirst = useIndirectConvention;
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wire sioHighValue = ~useIndirectConvention;
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wire sioHighValue = ~useIndirectConvention;
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wire oddParity = 1'b0;
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wire oddParity = 1'b0;
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wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
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wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
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wire endOfRx;
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wire endOfRx;
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit = cyclesPerEtu-1;
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wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit = cyclesPerEtu-1;
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wire rxCore_nReset = nReset & isoVdd & isoReset;
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wire rxCore_nReset = nReset & isoVdd & isoReset;
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reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
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reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
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always @(*) comOnGoing = rxRun|rxStartBit;
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always @(*) comOnGoing = rxRun|rxStartBit;
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always @(posedge clk, negedge rxCore_nReset) begin
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always @(posedge clk, negedge rxCore_nReset) begin
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if(~rxCore_nReset) begin
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if(~rxCore_nReset) begin
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safeClocksPerBit<={CLOCK_PER_BIT_WIDTH{1'b0}};
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safeClocksPerBit<={CLOCK_PER_BIT_WIDTH{1'b0}};
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end else if(endOfRx|~comOnGoing) begin
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end else if(endOfRx|~comOnGoing) begin
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safeClocksPerBit<=clocksPerBit;
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safeClocksPerBit<=clocksPerBit;
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end
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end
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end
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end
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wire [7:0] ts;
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wire [7:0] ts;
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RxCoreSelfContained #(
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RxCoreSelfContained #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH),
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.PRECISE_STOP_BIT(1'b1))
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.PRECISE_STOP_BIT(1'b1))
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rxCore (
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rxCore (
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.dataOut(rxData),
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.dataOut(rxData),
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.overrunErrorFlag(overrunError),
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.overrunErrorFlag(overrunError),
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.dataOutReadyFlag(bufferFull),
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.dataOutReadyFlag(bufferFull),
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.frameErrorFlag(frameError),
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.frameErrorFlag(frameError),
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.run(rxRun),
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.run(rxRun),
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.startBit(rxStartBit),
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.startBit(rxStartBit),
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.stopBit(guardTime),
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.stopBit(guardTime),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clocksPerBit(safeClocksPerBit),
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.clocksPerBit(safeClocksPerBit),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.ackFlags(ackFlags),
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.ackFlags(ackFlags),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.comClk(isoClk),
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.comClk(isoClk),
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.clk(clk),
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.clk(clk),
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.nReset(rxCore_nReset)
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.nReset(rxCore_nReset)
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);
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);
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TsAnalyzer tsAnalyzer(
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TsAnalyzer tsAnalyzer(
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.nReset(nReset),
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.nReset(nReset),
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoVdd(isoVdd),
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.isoVdd(isoVdd),
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.isoSio(isoSio),
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.isoSio(isoSio),
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.rxData(rxData),
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.rxData(rxData),
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.isActivated(isActivated),
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.isActivated(isActivated),
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.tsReceived(tsReceived),
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.tsReceived(tsReceived),
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.tsError(tsError),
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.tsError(tsError),
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.atrIsEarly(atrIsEarly),
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.atrIsEarly(atrIsEarly),
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.atrIsLate(atrIsLate),
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.atrIsLate(atrIsLate),
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.useIndirectConvention(useIndirectConvention),
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.useIndirectConvention(useIndirectConvention),
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.ts(ts)
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.ts(ts)
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);
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);
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FiDiAnalyzer fiDiAnalyzer(
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FiDiAnalyzer fiDiAnalyzer(
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.fiCode(fiCode),
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.fiCode(fiCode),
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.diCode(diCode),
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.diCode(diCode),
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.fi(fi),
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.fi(fi),
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.di(di),
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.di(di),
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.cyclesPerEtu(cyclesPerEtu),
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.cyclesPerEtu(cyclesPerEtu),
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.fMax(fMax)
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.fMax(fMax)
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);
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);
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wire run = rxStartBit | rxRun;
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wire run = rxStartBit | rxRun;
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localparam ATR_T0 = 0;
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localparam ATR_T0 = 0;
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localparam ATR_TDI = 1;
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localparam ATR_TDI = 1;
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localparam ATR_HISTORICAL = 2;
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localparam ATR_HISTORICAL = 2;
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localparam ATR_TCK = 3;
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localparam ATR_TCK = 3;
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localparam T0_HEADER = 0;
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localparam T0_HEADER = 0;
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localparam T0_HEADER_TPDU = 1;
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localparam T0_HEADER_TPDU = 1;
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localparam T0_PB = 2;
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localparam T0_PB = 2;
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localparam T0_DATA = 3;
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localparam T0_DATA = 3;
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localparam T0_NACK_DATA = 4;
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localparam T0_NACK_DATA = 4;
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localparam T0_SW1 = 5;
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localparam T0_SW1 = 5;
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localparam T0_SW2 = 6;
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localparam T0_SW2 = 6;
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localparam T0_HEADER_PPS = 100;
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localparam T0_HEADER_PPS = 100;
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localparam T0_PPS_RESPONSE = 101;
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localparam T0_PPS_RESPONSE = 101;
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integer fsmState;
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integer fsmState;
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reg [11:0] tdiStruct;
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reg [11:0] tdiStruct;
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wire [3:0] tdiCnt;//i+1
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wire [3:0] tdiCnt;//i+1
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wire [7:0] tdiData;//value of TDi
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wire [7:0] tdiData;//value of TDi
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assign {tdiCnt,tdiData}=tdiStruct;
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assign {tdiCnt,tdiData}=tdiStruct;
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wire [1:0] nIfBytes;
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wire [1:0] nIfBytes;
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HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
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HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
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reg [7:0] tempBytesCnt;
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reg [7:0] tempBytesCnt;
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always @(posedge isoClk, negedge nReset) begin
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always @(posedge isoClk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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lastByte<=8'b0;
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lastByte<=8'b0;
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ackFlags<=1'b0;
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ackFlags<=1'b0;
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bytesCnt<=32'b0;
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bytesCnt<=32'b0;
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end else if(ackFlags) begin
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end else if(ackFlags) begin
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ackFlags<=1'b0;
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ackFlags<=1'b0;
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end else if(frameErrorFlag|bufferFull) begin
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end else if(frameErrorFlag|bufferFull) begin
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if(tsReceived) lastByte<=dataOut;//ts is read by tsAnalyzer
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if(tsReceived) lastByte<=dataOut;//ts is read by tsAnalyzer
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ackFlags<=1'b1;
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ackFlags<=1'b1;
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bytesCnt<=bytesCnt+1'b1;
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bytesCnt<=bytesCnt+1'b1;
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end else if((32'b1==bytesCnt) & tsReceived) begin
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end else if((32'b1==bytesCnt) & tsReceived) begin
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lastByte<=ts;
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lastByte<=ts;
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end
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end
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end
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end
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reg ppsValidSoFar;
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reg ppsValidSoFar;
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//reg ppsAccepted;
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//reg ppsAccepted;
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wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
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wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
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wire [3:0] earlyAtrK = (4'h0==tdiCnt) ? dataOut[3:0] : atrK;
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wire [3:0] earlyAtrK = (4'h0==tdiCnt) ? dataOut[3:0] : atrK;
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always @(posedge isoClk, negedge rxCore_nReset) begin
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always @(posedge isoClk, negedge rxCore_nReset) begin
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if(~rxCore_nReset) begin
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if(~rxCore_nReset) begin
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ppsValidSoFar<=1'b0;
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ppsValidSoFar<=1'b0;
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//ppsAccepted<=1'b0;
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//ppsAccepted<=1'b0;
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fiCode<=4'b0001;
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fiCode<=4'b0001;
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diCode<=4'b0001;
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diCode<=4'b0001;
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useT0<=1'b1;
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useT0<=1'b1;
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useT1<=1'b0;
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useT1<=1'b0;
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useT15<=1'b0;
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useT15<=1'b0;
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{waitCardTx,waitTermTx}<=2'b00;
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{waitCardTx,waitTermTx}<=2'b00;
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fsmState<=ATR_TDI;
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fsmState<=ATR_TDI;
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atrHasTck<=1'b0;
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atrHasTck<=1'b0;
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tempBytesCnt<=8'h0;
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tempBytesCnt<=8'h0;
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tdiStruct<={4'h0,8'h80};//0x80 as default TDi to consider T0 as a TDi
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tdiStruct<={4'h0,8'h80};//0x80 as default TDi to consider T0 as a TDi
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atrCompleted<=1'b0;
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atrCompleted<=1'b0;
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atrK<=4'b0;
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atrK<=4'b0;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(~tsReceived) begin
|
if(~tsReceived) begin
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{waitCardTx,waitTermTx}<=2'b10;
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{waitCardTx,waitTermTx}<=2'b10;
|
end else if(~atrCompleted) begin
|
end else if(~atrCompleted) begin
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//ATR analysis
|
//ATR analysis
|
case(fsmState)
|
case(fsmState)
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ATR_TDI: begin
|
ATR_TDI: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
if(tempBytesCnt+1==nIfBytes) begin //TDi bytes
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if(tempBytesCnt+1==nIfBytes) begin //TDi bytes
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if(4'h0==tdiCnt) begin//this is T0
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if(4'h0==tdiCnt) begin//this is T0
|
atrK <= dataOut[3:0];
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atrK <= dataOut[3:0];
|
end
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end
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tempBytesCnt <= 2'h0;
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tempBytesCnt <= 2'h0;
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tdiStruct <= {tdiCnt+1'b1,dataOut};
|
tdiStruct <= {tdiCnt+1'b1,dataOut};
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//if(12'h0=={dataOut,atrK}) begin
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// atrCompleted <= 1'b1;
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// {waitCardTx,waitTermTx}<=2'b01;
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//end
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if((1'b0==tdiStruct[7]) |//we just received the last interface byte
|
if((1'b0==tdiStruct[7]) |//we just received the last interface byte
|
(4'b0==dataOut[7:4])) begin //or new TDi indicate no further interface bytes
|
(4'b0==dataOut[7:4])) begin //or new TDi indicate no further interface bytes
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//fsmState <= (4'b0!=earlyAtrK) ? ATR_HISTORICAL :
|
|
// atrHasTck ? ATR_TCK : T0_HEADER;
|
|
if(4'b0!=earlyAtrK) begin
|
if(4'b0!=earlyAtrK) begin
|
fsmState <= ATR_HISTORICAL;
|
fsmState <= ATR_HISTORICAL;
|
end else if(atrHasTck) begin
|
end else if(atrHasTck) begin
|
fsmState <= ATR_TCK;
|
fsmState <= ATR_TCK;
|
end else begin
|
end else begin
|
fsmState <= T0_HEADER;
|
fsmState <= T0_HEADER;
|
atrCompleted <= 1'b1;
|
atrCompleted <= 1'b1;
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{waitCardTx,waitTermTx}<=2'b01;
|
{waitCardTx,waitTermTx}<=2'b01;
|
end
|
end
|
end else begin//TDi, i from 1 to 15
|
end else begin//TDi, i from 1 to 15
|
fsmState <= ATR_TDI;
|
fsmState <= ATR_TDI;
|
end
|
end
|
|
|
end else begin //TA, TB or TC bytes
|
end else begin //TA, TB or TC bytes
|
//TODO: get relevant info
|
//TODO: get relevant info
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
ATR_HISTORICAL: begin
|
ATR_HISTORICAL: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
if(tempBytesCnt+1==atrK) begin
|
if(tempBytesCnt+1==atrK) begin
|
tempBytesCnt <= 8'h0;
|
tempBytesCnt <= 8'h0;
|
if(atrHasTck) begin
|
if(atrHasTck) begin
|
fsmState <= ATR_TCK;
|
fsmState <= ATR_TCK;
|
end else begin
|
end else begin
|
atrCompleted <= 1'b1;
|
atrCompleted <= 1'b1;
|
{waitCardTx,waitTermTx}<=2'b10;
|
{waitCardTx,waitTermTx}<=2'b10;
|
fsmState <= T0_HEADER;
|
fsmState <= T0_HEADER;
|
end
|
end
|
end else begin
|
end else begin
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
ATR_TCK: begin
|
ATR_TCK: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
//TODO:check
|
//TODO:check
|
atrCompleted <= 1'b1;
|
atrCompleted <= 1'b1;
|
{waitCardTx,waitTermTx}<=2'b10;
|
{waitCardTx,waitTermTx}<=2'b10;
|
fsmState <= T0_HEADER;
|
fsmState <= T0_HEADER;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end else if(useT0) begin
|
end else if(useT0) begin
|
//T=0 cmd/response monitoring state machine
|
//T=0 cmd/response monitoring state machine
|
case(fsmState)
|
case(fsmState)
|
T0_HEADER: begin
|
T0_HEADER: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
tpduHeader[CLA_I+:8]<=dataOut;
|
tpduHeader[CLA_I+:8]<=dataOut;
|
tempBytesCnt <= 1;
|
tempBytesCnt <= 1;
|
if(8'hFF==dataOut)
|
if(8'hFF==dataOut)
|
fsmState <= T0_HEADER_PPS;
|
fsmState <= T0_HEADER_PPS;
|
else
|
else
|
fsmState <= T0_HEADER_TPDU;
|
fsmState <= T0_HEADER_TPDU;
|
end
|
end
|
end
|
end
|
T0_HEADER_PPS: begin
|
T0_HEADER_PPS: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
|
tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
|
if(3==tempBytesCnt) begin//support only 4 byte PPS
|
if(3==tempBytesCnt) begin//support only 4 byte PPS
|
tempBytesCnt <= 8'h0;
|
tempBytesCnt <= 8'h0;
|
fsmState <= T0_PPS_RESPONSE;
|
fsmState <= T0_PPS_RESPONSE;
|
{waitCardTx,waitTermTx}<=2'b10;
|
{waitCardTx,waitTermTx}<=2'b10;
|
ppsValidSoFar<=1'b1;
|
ppsValidSoFar<=1'b1;
|
//ppsAccepted<=1'b0;
|
//ppsAccepted<=1'b0;
|
end else begin
|
end else begin
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
T0_PPS_RESPONSE: begin
|
T0_PPS_RESPONSE: begin
|
if(3==tempBytesCnt) begin//support only 4 byte PPS
|
if(3==tempBytesCnt) begin//support only 4 byte PPS
|
if(guardTime) begin
|
if(guardTime) begin
|
if(ppsValidSoFar & ppsDataMatch) begin
|
if(ppsValidSoFar & ppsDataMatch) begin
|
{fiCode,diCode}<=tpduHeader[PPS2_I+:8];
|
{fiCode,diCode}<=tpduHeader[PPS2_I+:8];
|
end
|
end
|
end
|
end
|
end
|
end
|
if(endOfRx) begin
|
if(endOfRx) begin
|
ppsValidSoFar<=ppsValidSoFar & ppsDataMatch;
|
ppsValidSoFar<=ppsValidSoFar & ppsDataMatch;
|
if(3==tempBytesCnt) begin//support only 4 byte PPS
|
if(3==tempBytesCnt) begin//support only 4 byte PPS
|
tempBytesCnt <= 8'h0;
|
tempBytesCnt <= 8'h0;
|
fsmState <= T0_HEADER;
|
fsmState <= T0_HEADER;
|
{waitCardTx,waitTermTx}<=2'b01;
|
{waitCardTx,waitTermTx}<=2'b01;
|
case(tpduHeader[(PPS1_I-(tempBytesCnt*8))+:8])
|
case(tpduHeader[(PPS1_I-(tempBytesCnt*8))+:8])
|
8'h11: begin
|
8'h11: begin
|
useT0<=1'b0;
|
useT0<=1'b0;
|
useT1<=1'b1;
|
useT1<=1'b1;
|
useT15<=1'b0;
|
useT15<=1'b0;
|
end
|
end
|
8'h1F: begin
|
8'h1F: begin
|
useT0<=1'b0;
|
useT0<=1'b0;
|
useT1<=1'b0;
|
useT1<=1'b0;
|
useT15<=1'b1;
|
useT15<=1'b1;
|
end
|
end
|
default: begin
|
default: begin
|
useT0<=1'b1;
|
useT0<=1'b1;
|
useT1<=1'b0;
|
useT1<=1'b0;
|
useT15<=1'b0;
|
useT15<=1'b0;
|
end
|
end
|
endcase
|
endcase
|
end else begin
|
end else begin
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
T0_HEADER_TPDU: begin
|
T0_HEADER_TPDU: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
|
tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
|
if(4==tempBytesCnt) begin
|
if(4==tempBytesCnt) begin
|
tempBytesCnt <= 8'h0;
|
tempBytesCnt <= 8'h0;
|
fsmState <= T0_PB;
|
fsmState <= T0_PB;
|
{waitCardTx,waitTermTx}<=2'b10;
|
{waitCardTx,waitTermTx}<=2'b10;
|
end else begin
|
end else begin
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
T0_PB: begin
|
T0_PB: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
case(dataOut[7:4])
|
case(dataOut[7:4])
|
4'h6: begin
|
4'h6: begin
|
fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;
|
fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;
|
end
|
end
|
4'h9: begin
|
4'h9: begin
|
fsmState <= T0_SW2;
|
fsmState <= T0_SW2;
|
end
|
end
|
default: begin
|
default: begin
|
case(dataOut)
|
case(dataOut)
|
tpduHeader[INS_I+:8]: begin//ACK
|
tpduHeader[INS_I+:8]: begin//ACK
|
fsmState <= T0_DATA;
|
fsmState <= T0_DATA;
|
{waitCardTx,waitTermTx}<=2'b11;
|
{waitCardTx,waitTermTx}<=2'b11;
|
end
|
end
|
~tpduHeader[INS_I+:8]: begin//NACK
|
~tpduHeader[INS_I+:8]: begin//NACK
|
fsmState <= T0_NACK_DATA;
|
fsmState <= T0_NACK_DATA;
|
{waitCardTx,waitTermTx}<=2'b11;
|
{waitCardTx,waitTermTx}<=2'b11;
|
end
|
end
|
default: begin //invalid
|
default: begin //invalid
|
//TODO
|
//TODO
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
T0_NACK_DATA: begin
|
T0_NACK_DATA: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
fsmState <= T0_PB;
|
fsmState <= T0_PB;
|
{waitCardTx,waitTermTx}<=2'b10;
|
{waitCardTx,waitTermTx}<=2'b10;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
end
|
end
|
end
|
end
|
T0_SW1: begin
|
T0_SW1: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
//TODO:check != 60 but equal to 6x or 9x
|
//TODO:check != 60 but equal to 6x or 9x
|
fsmState <= T0_SW2;
|
fsmState <= T0_SW2;
|
{waitCardTx,waitTermTx}<=2'b10;
|
{waitCardTx,waitTermTx}<=2'b10;
|
end
|
end
|
end
|
end
|
T0_SW2: begin
|
T0_SW2: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
fsmState <= T0_HEADER;
|
fsmState <= T0_HEADER;
|
{waitCardTx,waitTermTx}<=2'b01;
|
{waitCardTx,waitTermTx}<=2'b01;
|
end
|
end
|
end
|
end
|
T0_DATA: begin
|
T0_DATA: begin
|
if(endOfRx) begin
|
if(endOfRx) begin
|
if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
|
if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
|
tempBytesCnt <= 0;
|
tempBytesCnt <= 0;
|
fsmState <= T0_SW1;
|
fsmState <= T0_SW1;
|
{waitCardTx,waitTermTx}<=2'b10;
|
{waitCardTx,waitTermTx}<=2'b10;
|
end else begin
|
end else begin
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
tempBytesCnt <= tempBytesCnt+1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
reg [1:0] txDir;
|
reg [1:0] txDir;
|
reg proto_cardTx;
|
reg proto_cardTx;
|
reg proto_termTx;
|
reg proto_termTx;
|
always @(*) begin: protoComDirectionCombiBlock
|
always @(*) begin: protoComDirectionCombiBlock
|
if(guardTime & ~isoSio)
|
if(guardTime & ~isoSio)
|
{proto_cardTx, proto_termTx}={txDir[0],txDir[1]};
|
{proto_cardTx, proto_termTx}={txDir[0],txDir[1]};
|
else
|
else
|
{proto_cardTx, proto_termTx}={txDir[1],txDir[0]};
|
{proto_cardTx, proto_termTx}={txDir[1],txDir[0]};
|
end
|
end
|
always @(posedge isoClk, negedge rxCore_nReset) begin: protoComDirectionSeqBlock
|
always @(posedge isoClk, negedge rxCore_nReset) begin: protoComDirectionSeqBlock
|
if(~rxCore_nReset | ~run) begin
|
if(~rxCore_nReset | ~run) begin
|
txDir<=2'b00;
|
txDir<=2'b00;
|
end else begin
|
end else begin
|
if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
|
if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
|
case({waitCardTx, waitTermTx})
|
case({waitCardTx, waitTermTx})
|
2'b00: txDir<=2'b00;//no one should/is sending
|
2'b00: txDir<=2'b00;//no one should/is sending
|
2'b01: txDir<=2'b01;//terminal should/is sending
|
2'b01: txDir<=2'b01;//terminal should/is sending
|
2'b10: txDir<=2'b10;//card should/is sending
|
2'b10: txDir<=2'b10;//card should/is sending
|
2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)
|
2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
reg phy_cardTx;
|
reg phy_cardTx;
|
reg phy_termTx;
|
reg phy_termTx;
|
always @(negedge isoSio, negedge rxCore_nReset) begin: phyComDirectionBlock
|
always @(negedge isoSio, negedge rxCore_nReset) begin: phyComDirectionBlock
|
if(~rxCore_nReset) begin
|
if(~rxCore_nReset) begin
|
phy_cardTx<=1'b0;
|
phy_cardTx<=1'b0;
|
phy_termTx<=1'b0;
|
phy_termTx<=1'b0;
|
end else begin
|
end else begin
|
if(~isoSioTerm) begin
|
if(~isoSioTerm) begin
|
phy_cardTx<=1'b0;
|
phy_cardTx<=1'b0;
|
phy_termTx<=1'b1;
|
phy_termTx<=1'b1;
|
end else begin
|
end else begin
|
phy_cardTx<=1'b1;
|
phy_cardTx<=1'b1;
|
phy_termTx<=1'b0;
|
phy_termTx<=1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
assign cardTx = useDirectionProbe ? phy_cardTx : proto_cardTx;
|
assign cardTx = useDirectionProbe ? phy_cardTx : proto_cardTx;
|
assign termTx = useDirectionProbe ? phy_termTx : proto_termTx;
|
assign termTx = useDirectionProbe ? phy_termTx : proto_termTx;
|
|
|
endmodule
|
endmodule
|
`default_nettype wire
|
`default_nettype wire
|
|
|
|
|
