------------------------------------------------------------------
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------------------------------------------------------------------
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-- 6502 Top module.
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-- 6502 Top module.
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--
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--
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-- Copyright Ian Chapman October 28 2010
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-- Copyright Ian Chapman October 28 2010
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--
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--
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-- This file is part of the Lattice 6502 project
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-- This file is part of the Lattice 6502 project
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-- It is used to compile with Linux ghdl not ispLeaver.
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-- It is used to compile with Linux ghdl not ispLeaver.
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-- It is the address mapping and connecting the other modules.
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-- It is the address mapping and connecting the other modules.
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-- It is replaced by Processor.vhd when running ispLeaver.
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-- It is replaced by Processor.vhd when running ispLeaver.
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--
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--
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-- To do
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-- To do
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-- This will be work in process or replaced whatever
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-- This will be work in process or replaced whatever
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-- project file is needed to control other modules.
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-- project file is needed to control other modules.
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--
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--
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-- *************************************************************
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-- *************************************************************
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-- Distributed under the GNU Lesser General Public License. *
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-- Distributed under the GNU Lesser General Public License. *
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-- This can be obtained from “www.gnu.org”. *
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-- This can be obtained from www.gnu.org. *
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-- *************************************************************
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-- *************************************************************
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>
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-- along with this program. If not, see <http://www.gnu.org/licenses/>
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--
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--
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-- ghdl_processor.vhd
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-- ghdl_processor.vhd
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--
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--
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------------------------------------------------------------------
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------------------------------------------------------------------
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library IEEE; --Use standard IEEE libs as recommended by Tristan.
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library IEEE; --Use standard IEEE libs as recommended by Tristan.
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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entity Processor is
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entity Processor is
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Port (
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Port (
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-- data_wr : inout unsigned(7 downto 0);
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-- data_wr : inout unsigned(7 downto 0);
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clk_pin : in std_logic;
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clk_pin : in std_logic;
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-- clk_out : out std_logic;
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-- clk_out : out std_logic;
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-- u802 : out std_logic;
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-- u802 : out std_logic;
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-- u702 : out std_logic;
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-- u702 : out std_logic;
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-- u602 : out std_logic;
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-- u602 : out std_logic;
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-- u1101 : out std_logic;
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-- u1101 : out std_logic;
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-- u801 : out std_logic;
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-- u801 : out std_logic;
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-- u701 : out std_logic;
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-- u701 : out std_logic;
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u601 : out std_logic;
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u601 : out std_logic;
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rst_pin : in std_logic;
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rst_pin : in std_logic;
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irq_pin : in std_logic;
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-- irq_pin : in std_logic;
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nmi_pin : in std_logic;
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-- nmi_pin : in std_logic;
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RX_pin : in std_logic;
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RX_pin : in std_logic;
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-- PG_pin : in std_logic;
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-- PG_pin : in std_logic;
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TX_pin : out std_logic;
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TX_pin : out std_logic;
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Pwr_on_pin : out std_logic
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Pwr_on_pin : out std_logic
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);
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);
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end Processor;
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end Processor;
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architecture structure of Processor is
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architecture structure of Processor is
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-- COMPONENT DECLARATIONS
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-- COMPONENT DECLARATIONS
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component P65C02
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component P65C02
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port(
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port(
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data_rd: in unsigned(7 downto 0);
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data_rd: in unsigned(7 downto 0);
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data_wr: out unsigned(7 downto 0);
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data_wr: out unsigned(7 downto 0);
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-- cycle_mark : out std_logic; --Used to signal the cycle usually cycle 0.
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-- cycle_mark : out std_logic; --Used to signal the cycle usually cycle 0.
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address: inout unsigned(15 downto 0);
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address: inout unsigned(15 downto 0);
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proc_write : inout std_logic;
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proc_write : inout std_logic;
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reset, clock : in std_logic;
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reset, clock : in std_logic;
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irq : in std_logic;
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irq : in std_logic;
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nmi : in std_logic);
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nmi : in std_logic);
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end component;
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end component;
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component UART_RX is
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component UART_RX is
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port(
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port(
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PG, OSC_10MHz,RX, csr_usart :in std_logic;
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PG, OSC_10MHz,RX, csr_usart :in std_logic;
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RX_rdy : out std_logic;
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RX_rdy : out std_logic;
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rx_reg : out unsigned(7 downto 0)
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rx_reg : out unsigned(7 downto 0)
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);
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);
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end component;
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end component;
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component UART_TX is
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component UART_TX is
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port(
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port(
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OSC_10MHz, PG, csw_usart :in std_logic;
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OSC_10MHz, PG, csw_usart :in std_logic;
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tx_dat : in unsigned(7 downto 0);
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tx_dat : in unsigned(7 downto 0);
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TX ,tx_rdy : out std_logic
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TX ,tx_rdy : out std_logic
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);
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);
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end component;
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end component;
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--component Lattice_rom
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--component Lattice_rom
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--port (
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--port (
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-- OutClock: in std_logic;
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-- OutClock: in std_logic;
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-- OutClockEn: in std_logic;
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-- OutClockEn: in std_logic;
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-- Reset: in std_logic;
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-- Reset: in std_logic;
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-- Address: in std_logic_vector(9 downto 0);
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-- Address: in std_logic_vector(9 downto 0);
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-- Q: out std_logic_vector(7 downto 0));
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-- Q: out std_logic_vector(7 downto 0));
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--end component;
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--end component;
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--component Lattice_ram
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--component Lattice_ram
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--port (
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--port (
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-- Clock: in std_logic;
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-- Clock: in std_logic;
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-- ClockEn: in std_logic;
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-- ClockEn: in std_logic;
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-- Reset: in std_logic;
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-- Reset: in std_logic;
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-- WE: in std_logic;
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-- WE: in std_logic;
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-- Address: in std_logic_vector(9 downto 0);
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-- Address: in std_logic_vector(9 downto 0);
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-- Data: in std_logic_vector(7 downto 0);
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-- Data: in std_logic_vector(7 downto 0);
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-- Q: out std_logic_vector(7 downto 0));
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-- Q: out std_logic_vector(7 downto 0));
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--end component;
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--end component;
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component ghdl_rom
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component ghdl_rom
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port (
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port (
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rom_dat: out unsigned(7 downto 0);
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rom_dat: out unsigned(7 downto 0);
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wr, clk, rst: in std_logic;
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wr, clk, rst: in std_logic;
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address: in unsigned(15 downto 0)
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address: in unsigned(15 downto 0)
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);
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);
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end component;
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end component;
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component ghdl_ram
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component ghdl_ram
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port (
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port (
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ram_dat: out unsigned(7 downto 0);
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ram_dat: out unsigned(7 downto 0);
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data_wr : in unsigned(7 downto 0);
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data_wr : in unsigned(7 downto 0);
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clk, wr, rst: in std_logic;
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clk, wr, rst: in std_logic;
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address: in unsigned(15 downto 0)
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address: in unsigned(15 downto 0)
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);
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);
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end component;
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end component;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Signal Declarations
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-- Signal Declarations
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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signal address : unsigned(15 downto 0);
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signal address : unsigned(15 downto 0);
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signal add : unsigned(15 downto 0);
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signal add : unsigned(15 downto 0);
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signal proc_rd_dat, rom_dat, ram_dat, data_wr : unsigned(7 downto 0);
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signal proc_rd_dat, rom_dat, ram_dat, data_wr : unsigned(7 downto 0);
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signal rx_dat : unsigned(7 downto 0);
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signal rx_dat : unsigned(7 downto 0);
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signal proc_write : std_logic;
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signal proc_write : std_logic;
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signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic;
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signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic;
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-- signal cycle_mark : std_logic
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signal rst_bar : std_logic;
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signal rst_bar : std_logic;
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signal ram_write : std_logic;
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signal ram_write : std_logic;
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--signal clk : std_logic;
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--signal clk_pin : std_logic;
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signal counter : unsigned(3 downto 0);
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signal counter : unsigned(3 downto 0);
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signal nmi_pin, irq_pin : std_logic;
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-- I/O ports
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-- I/O ports
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constant led_port : unsigned (15 downto 0) := x"4007";
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constant led_port : unsigned (15 downto 0) := x"4007";
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constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
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constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
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constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
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constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
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constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
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constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
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constant Kirq : unsigned (15 downto 0) := X"4002"; --interrpt testing only
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constant Knmi : unsigned (15 downto 0) := x"4003";
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begin
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begin
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U1 : P65C02 port map(
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U1 : P65C02 port map(
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reset => rst_pin,
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reset => rst_pin,
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Clock => clk_pin,
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Clock => clk_pin,
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data_rd => proc_rd_dat,
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data_rd => proc_rd_dat,
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data_wr => data_wr,
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data_wr => data_wr,
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address => address,
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address => address,
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proc_write => proc_write,
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proc_write => proc_write,
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irq => irq_pin,
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irq => irq_pin,
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nmi => nmi_pin);
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nmi => nmi_pin);
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-- cycle_mark => cycle_mark);
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-- cycle_mark => cycle_mark);
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U2 : UART_RX port map (
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U2 : UART_RX port map (
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PG => rst_pin,
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PG => rst_pin,
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OSC_10MHz => clk_pin,
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OSC_10MHz => clk_pin,
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RX => RX_pin,
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RX => RX_pin,
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rx_reg => rx_dat,
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rx_reg => rx_dat,
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csr_usart => csr_usart,
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csr_usart => csr_usart,
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RX_rdy => RX_rdy);
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RX_rdy => RX_rdy);
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U3 : UART_TX port map (
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U3 : UART_TX port map (
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PG => rst_pin,
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PG => rst_pin,
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TX => TX_pin,
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TX => TX_pin,
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tx_rdy => tx_rdy,
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tx_rdy => tx_rdy,
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OSC_10MHz => clk_pin,
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OSC_10MHz => clk_pin,
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tx_dat => data_wr,
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tx_dat => data_wr,
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csw_usart => csw_usart);
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csw_usart => csw_usart);
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R1 : ghdl_rom port map(
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R1 : ghdl_rom port map(
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rom_dat=>rom_dat,
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rom_dat=>rom_dat,
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address=>address,
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address=>address,
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wr=>proc_write,
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wr=>proc_write,
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clk=>clk_pin,
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clk=>clk_pin,
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rst=>rst_pin);
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rst=>rst_pin);
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R2 : ghdl_ram port map(
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R2 : ghdl_ram port map(
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clk=>clk_pin,
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clk=>clk_pin,
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rst=>rst_pin,
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rst=>rst_pin,
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ram_dat=>ram_dat,
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ram_dat=>ram_dat,
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data_wr=>data_wr,
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data_wr=>data_wr,
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address=>address,
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address=>address,
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wr=>ram_write);
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wr=>ram_write);
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--R3 : Lattice_rom port map(
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--R3 : Lattice_rom port map(
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-- Reset => rst_bar,
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-- Reset => rst_bar,
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-- OutClock => clk_pin,
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-- OutClock => clk_pin,
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-- (address(9 downto 0)) => std_logic_vector(Address(9 downto 0)),
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-- (address(9 downto 0)) => std_logic_vector(Address(9 downto 0)),
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-- unsigned(Q) => rom_dat,
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-- unsigned(Q) => rom_dat,
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-- OutClockEn => one);
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-- OutClockEn => one);
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--R4 : Lattice_ram port map(
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--R4 : Lattice_ram port map(
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-- Reset => rst_bar,
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-- Reset => rst_bar,
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-- Clock => clk_pin,
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-- Clock => clk_pin,
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-- WE => ram_write,
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-- WE => ram_write,
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-- address(9 downto 0) => std_logic_vector(Address(9 downto 0)),
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-- address(9 downto 0) => std_logic_vector(Address(9 downto 0)),
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-- Data => std_logic_vector(data_wr),
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-- Data => std_logic_vector(data_wr),
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-- unsigned(Q) => ram_dat, ClockEn => one);
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-- unsigned(Q) => ram_dat
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-- ClockEn => one);
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one <= '1';
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one <= '1';
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rst_bar <= not rst_pin;
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rst_bar <= not rst_pin;
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one <= '1';
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ram_write <= proc_write and not address(15) and not address(14);
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--one <= '1';
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--u601 <= cycle_mark;
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--u601 <= cycle_mark;
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mux_add : process(rst_pin, clk_pin)
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mux_add : process(rst_pin, clk_pin)
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begin
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begin
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if rst_pin = '0' then
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if rst_pin = '0' then
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add <= (others => '0');
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add <= (others => '0');
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elsif rising_edge(clk_pin) then
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elsif rising_edge(clk_pin) then
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add <= address;
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add <= address;
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end if;
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end if;
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end process;
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end process;
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ram_address : process (proc_write, address(15 downto 14))
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--ram_address : process (proc_write, address(15 downto 14))
|
begin
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--begin
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if proc_write = '1' and address(15 downto 14) = "00" then
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-- if proc_write = '1' and address(15 downto 14) = "00" then
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ram_write <= '1';
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-- ram_write <= '1';
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else
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-- else
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ram_write <= '0';
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-- ram_write <= '0';
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end if;
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-- end if;
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end process;
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--end process;
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-- ===================================================================
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-- ===================================================================
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-- Updated muxer process
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-- Updated muxer process
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muxer : process (add(15 downto 14), rom_dat, ram_dat, rx_dat, tx_rdy, rx_rdy)
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muxer : process (add(15 downto 14), rom_dat, ram_dat, rx_dat, tx_rdy, rx_rdy)
|
begin
|
begin
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if add(15 downto 14) = "11" then
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if add(15 downto 14) = "11" then
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proc_rd_dat <= rom_dat;
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proc_rd_dat <= rom_dat;
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end if;
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end if;
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if add(15 downto 14) = "00" then
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if add(15 downto 14) = "00" then
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proc_rd_dat <= ram_dat;
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proc_rd_dat <= ram_dat;
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end if;
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end if;
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if add(15 downto 0) = rs232_dat then
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if add(15 downto 0) = rs232_dat then
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proc_rd_dat <= rx_dat;
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proc_rd_dat <= rx_dat;
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end if;
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end if;
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if add(15 downto 0) = uart_stat then
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if add(15 downto 0) = uart_stat then
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proc_rd_dat <= tx_rdy & rx_rdy & "000000";
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proc_rd_dat <= tx_rdy & rx_rdy & "000000";
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end if;
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end if;
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end process;
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end process;
|
-- ===================================================================
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-- ===================================================================
|
|
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rs232_cs : process (rst_pin, clk_pin, address, proc_write)
|
rs232_cs : process (rst_pin, clk_pin, address, proc_write)
|
begin
|
begin
|
if proc_write = '0' and address = uart then
|
if proc_write = '0' and address = uart then
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csr_usart <= '1';
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csr_usart <= '1';
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else
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else
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csr_usart <= '0';
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csr_usart <= '0';
|
end if;
|
end if;
|
|
|
if proc_write = '1' and address = uart then
|
if proc_write = '1' and address = uart then
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csw_usart <= '1';
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csw_usart <= '1';
|
else
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else
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csw_usart <= '0';
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csw_usart <= '0';
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
|
|
relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
|
--relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
|
begin
|
--begin
|
if rst_pin = '0' then
|
--if rst_pin = '0' then
|
Pwr_on_pin <= '0';
|
-- Pwr_on_pin <= '0';
|
elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
|
-- elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
|
Pwr_on_pin <= data_wr(7);
|
-- Pwr_on_pin <= data_wr(7);
|
end if;
|
--end if;
|
end process;
|
--end process;
|
|
|
|
--irq : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
|
|
--begin
|
|
--if rst_pin = '0' then
|
|
-- irq_pin <= '1';
|
|
-- elsif rising_edge(clk_pin) then
|
|
-- if address = Kirq and proc_write = '1' then
|
|
-- irq_pin <= data_wr(0); --set and hold bit 0
|
|
-- end if;
|
|
--end if;
|
|
--end process;
|
|
|
|
--nmi : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
|
|
--begin
|
|
--if rst_pin = '0' then
|
|
-- nmi_pin <= '1';
|
|
-- elsif rising_edge(clk_pin) then
|
|
--
|
|
-- if address = Knmi and proc_write = '1' then
|
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-- nmi_pin <= data_wr(0); --set and hold bit 0
|
|
-- end if;
|
|
--end if;
|
|
--end process;
|
|
|
end structure;
|
end structure;
|
|
|
