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------------------------------------------------------------------

------------------------------------------------------------------

--      6502 principal module.

--      6502 principal module.

--

--

--      Copyright Ian Chapman October 28 2010

--      Copyright Ian Chapman October 28 2010

--

--

--      This file is part of the Lattice 6502 project

--      This file is part of the Lattice 6502 project

--      It is used to compile with Linux ghdl and ispLeaver.

--      It is used to compile with Linux ghdl and ispLeaver.

--

--

--      To do

--      To do

--              Detailed test of all instructions.

--              Detailed test of all instructions.

--

--

--      *************************************************************

--      *************************************************************

--      Distributed under the GNU Lesser General Public License.    *

--      Distributed under the GNU Lesser General Public License.    *

--      This can be obtained from www.gnu.org.                    *

--      This can be obtained from www.gnu.org.                      *

--      *************************************************************

--      *************************************************************

--      This program is free software: you can redistribute it and/or modify

--      This program is free software: you can redistribute it and/or modify

--      it under the terms of the GNU General Public License as published by

--      it under the terms of the GNU General Public License as published by

--      the Free Software Foundation, either version 3 of the License, or

--      the Free Software Foundation, either version 3 of the License, or

--      (at your option) any later version.

--      (at your option) any later version.

--

--

--      This program is distributed in the hope that it will be useful,

--      This program is distributed in the hope that it will be useful,

--      but WITHOUT ANY WARRANTY; without even the implied warranty of

--      but WITHOUT ANY WARRANTY; without even the implied warranty of

--      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--      GNU General Public License for more details.

--      GNU General Public License for more details.

--

--

--      You should have received a copy of the GNU General Public License

--      You should have received a copy of the GNU General Public License

--      along with this program.  If not, see <http://www.gnu.org/licenses/>

--      along with this program.  If not, see <http://www.gnu.org/licenses/>

--

--

--      65C02.vhd

--      65C02.vhd

---  Purpose to test and exercise my VHLD skills

---  Purpose to test and exercise my VHLD skills

---- I've decided not to support 65C02 instructions

---- I've decided not to support 65C02 instructions

---- nor BCD arithmetic.

---- nor BCD arithmetic.

---- I will make it run as fast as I can.  Timing not per a real 6502

---- I will make it run as fast as I can.  Timing not per a real 6502

---- Lattice EBI has clocked address inputs, so as not to add a cycle

---- Lattice EBI has clocked address inputs, so as not to add a cycle

---- 6502 address outputs are not latched.  The data output of the EBI ROM and

---- 6502 address outputs are not latched.  The data output of the EBI ROM and

---- RAM is not clocked.

---- RAM is not clocked.

---- To maintain speed the 6502 address to ROM/RAM is not clocked and the data

---- To maintain speed the 6502 address to ROM/RAM is not clocked and the data

---- returned is not clocked by ROM/RAM.  Structures of form address <= address + "1";

---- returned is not clocked by ROM/RAM.  Structures of form address <= address + "1";

---- cause a race condition.  I had to store the address from the  mux for

---- cause a race condition.  I had to store the address from the  mux for

---- INC type instructions ie read then write.

---- INC type instructions ie read then write.

----

----

---- One boob I've just noticed jsr and pha in the 6502 work opposite to 

---- One boob I've just noticed jsr and pha in the 6502 work opposite to 

---- what I expected ie jsr decrements the stack and I inc it.  I guess

---- what I expected ie jsr decrements the stack and I inc it.  I guess

---- that was the way my first computer the SDS sigma 2 did it.  I'll keep

---- that was the way my first computer the SDS sigma 2 did it.  I'll keep

---- like that for now in case a bigger stack is needed.  Oh no a sigma 2

---- like that for now in case a bigger stack is needed.  Oh no a sigma 2

---- did not have a stack only L link register.

---- did not have a stack only L link register.

----

----

--      I used this to set the hold timing default "-exp parHoldLimit=999"

--      I used this to set the hold timing default "-exp parHoldLimit=999"

--      Also path based placement on

--      Also path based placement on

--      When generating a Lattice ROM/RAM untick latche outputs and use

--      When generating a Lattice ROM/RAM untick latche outputs and use

--      the *.mem file generated with my asm2rom.pl script.

--      the *.mem file generated with my asm2rom.pl script.

------------------------------------------------------------------------------------

------------------------------------------------------------------------------------

--                      TO Do

--                      TO Do

--      1       DONE Update all address modes of cmp, cpx and cpy per #mode

--      1       DONE Update all address modes of cmp, cpx and cpy per #mode

--      2       DONE Add rol, ror, asl, lsr,  per inc and dec

--      2       DONE Add rol, ror, asl, lsr,  per inc and dec

--      3       DONE Correct flags in all modes of item 2

--      3       DONE Correct flags in all modes of item 2

--      5       Continue testing

--      5       Continue testing

--      6       DONE Get a kernel up to test each and every instruction

--      6       DONE Get a kernel up to test each and every instruction

--      7       Test all instructions

--      7       Test all instructions

--      7       Add the 65C02 stuff.  I think the most needed is phx, phy, plx

--      7       Add the 65C02 stuff.  I think the most needed is phx, phy, plx

--              and ply are the most useful.

--              and ply are the most useful.

------------------------------------------------------------------------------------

------------------------------------------------------------------------------------

--      Revision history

--      Revision history

--      Nov 4, 2010

--      Nov 4, 2010

--      Rationalized all flavours of cmp, cpy and cpx.

--      Rationalized all flavours of cmp, cpy and cpx.

--      Changed jsr to combine out_dat1 and out_dat2 into out_dat.

--      Changed jsr to combine out_dat1 and out_dat2 into out_dat.

--      Changed wr_ctr to wr_fg.

--      Changed wr_ctr to wr_fg.

--      This saved 43 slices, 69% of slices are used.

--      This saved 43 slices, 69% of slices are used.

--      Removed many redundant comment lines.

--      Removed many redundant comment lines.

--      ******************************************************************

--      ******************************************************************

--      Nov 1, 2010

--      Nov 1, 2010

--      Double quotes inside a comment line rejected by ghdl

--      Double quotes inside a comment line rejected by ghdl

--      cmp carry not set when equal

--      cmp carry not set when equal

--      php not saving flags, had to add a cycle for flags to prop in cycle 0

--      php not saving flags, had to add a cycle for flags to prop in cycle 0

--

--

--      ******************************************************************************

--      ******************************************************************************

library IEEE;                   --Use standard IEEE libs as recommended by Tristan.

library IEEE;                   --Use standard IEEE libs as recommended by Tristan.

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.numeric_std.all;

use IEEE.numeric_std.all;

entity P65C02 is

entity P65C02 is

Port (

Port (

        clock: in std_logic;

        clock: in std_logic;

        reset : in std_logic;

        reset : in std_logic;

        data_wr: out unsigned(7 downto 0);

        data_wr: out unsigned(7 downto 0);

        data_rd: in unsigned(7 downto 0);

        data_rd: in unsigned(7 downto 0);

        proc_write:  inout std_logic;

        proc_write:  inout std_logic;

        irq: in std_logic;              --Active 0

        irq: in std_logic;              --Active 0

        nmi: in std_logic;              --Neg transition.

        nmi: in std_logic;              --Neg transition.

        address: inout unsigned(15 downto 0)

        address: inout unsigned(15 downto 0)

    );

    );

end P65C02;

end P65C02;

architecture P65C02_architecture of P65C02 is

architecture P65C02_architecture of P65C02 is

------------------------------------------------------------------------

------------------------------------------------------------------------

-- Signal Declarations

-- Signal Declarations

------------------------------------------------------------------------

------------------------------------------------------------------------

signal reg_pc : unsigned(15 downto 0);

signal reg_pc : unsigned(15 downto 0);

signal add_hold : unsigned(15 downto 0);

signal add_hold : unsigned(15 downto 0);

signal reg_a  : unsigned(8 downto 0);

signal reg_a  : unsigned(8 downto 0);

signal reg_x, reg_y, reg_s, reg_sp : unsigned(7 downto 0);

signal reg_x, reg_y, reg_s, reg_sp : unsigned(7 downto 0);

signal Instruction_in, dat_in1, dat_in2, dat_out : unsigned(7 downto 0);

signal Instruction_in, dat_in1, dat_in2, dat_out : unsigned(7 downto 0);

signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff, wr_fg : std_logic;

signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff, wr_fg : std_logic;

signal cycle_ctr, add_fg : unsigned(3 downto 0);

signal cycle_ctr, add_fg : unsigned(3 downto 0);

signal flags_fg : unsigned(1 downto 0);

signal flags_fg : unsigned(1 downto 0);

signal pc_dec_fg, dat2pc_fg : std_logic;

signal pc_dec_fg, dat2pc_fg : std_logic;

--      End of signal declarations

--      End of signal declarations

begin   --architecture

begin   --architecture

--      =======================================================

--      =======================================================

read_mem:process (clock, reset)

read_mem:process (clock, reset)

begin

begin

if reset = '0' then

if reset = '0' then

        dat_in1 <= (others => '0');

        dat_in1 <= (others => '0');

        dat_in2 <= (others => '0');

        dat_in2 <= (others => '0');

        instruction_in <= (others => '0');

        instruction_in <= (others => '0');

        elsif rising_edge(clock) then

        elsif rising_edge(clock) then

                dat_in2 <= dat_in1;

                dat_in2 <= dat_in1;

                dat_in1 <= data_rd;

                dat_in1 <= data_rd;

                if cycle_ctr = x"0" then

                if cycle_ctr = x"0" then

                                Instruction_in <= x"00";

                                Instruction_in <= x"00";

                        else

                        else

                                Instruction_in <= data_rd;

                                Instruction_in <= data_rd;

                        end if;

                        end if;

                end if;

                end if;

end if;

end if;

end process read_mem;

end process read_mem;

--      =======================================================

--      =======================================================

Prog_ptr:process (clock, reset, pc_dec_fg)

Prog_ptr:process (clock, reset, pc_dec_fg)

begin

begin

if reset = '0' then

if reset = '0' then

        reg_pc <= x"FFFC";

        reg_pc <= x"FFFC";

        elsif rising_edge(clock) then

        elsif rising_edge(clock) then

                if dat2pc_fg = '1' then

                if dat2pc_fg = '1' then

                        reg_pc(15 downto 8) <= data_rd;

                        reg_pc(15 downto 8) <= data_rd;

                        reg_pc(7 downto 0) <= dat_in1;

                        reg_pc(7 downto 0) <= dat_in1;

                        reg_pc <= reg_pc + x"0001";

                        reg_pc <= reg_pc + x"0001";

                elsif pc_dec_fg = '1' then

                elsif pc_dec_fg = '1' then

                        reg_pc <= reg_pc - x"0001";

                        reg_pc <= reg_pc - x"0001";

--              elsif cycle_ctr = x"0" and irq = '0' and i_fg = '0' then

--              elsif cycle_ctr = x"0" and irq = '0' and i_fg = '0' then

--                      reg_pc <= reg_pc - x"0001";

--                      reg_pc <= reg_pc - x"0001";

                elsif branch_fg = '1' then

                elsif branch_fg = '1' then

                        reg_pc <= reg_pc + (dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) &  dat_in1);

                        reg_pc <= reg_pc + (dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) &  dat_in1);

                end if;

                end if;

end if;

end if;

end process Prog_ptr;

end process Prog_ptr;

begin

begin

if reset = '0' then

if reset = '0' then

address <= reg_pc;

address <= reg_pc;

        else

        else

                Case add_fg is

                Case add_fg is

                when x"0" =>

                when x"0" =>

                        address <= reg_pc;

                        address <= reg_pc;

                when x"1" =>                    --Zero page

                when x"1" =>                    --Zero page

                        if proc_write = '0' then

                        if proc_write = '0' then

                                address(7 downto 0) <= data_rd;

                                address(7 downto 0) <= data_rd;

                        else

                        else

                                address(7 downto 0) <= dat_in1;

                                address(7 downto 0) <= dat_in1;

                        end if;

                        end if;

                        address(15 downto 8) <= x"00";

                        address(15 downto 8) <= x"00";

                when x"2" =>                    --Zero page, x

                when x"2" =>                    --Zero page, x

                        if proc_write = '0' then

                        if proc_write = '0' then

                                address(7 downto 0) <= data_rd + reg_x;

                                address(7 downto 0) <= data_rd + reg_x;

                        else

                        else

                                address(7 downto 0) <= dat_in1 + reg_x;

                                address(7 downto 0) <= dat_in1 + reg_x;

                        end if;

                        end if;

                        address(15 downto 8) <= x"00";

                        address(15 downto 8) <= x"00";

                when x"3" =>                    --Zero page, y

                when x"3" =>                    --Zero page, y

                        if proc_write = '0' then

                        if proc_write = '0' then

                                address(7 downto 0) <= data_rd + reg_y;

                                address(7 downto 0) <= data_rd + reg_y;

                        else

                        else

                                address(7 downto 0) <= dat_in1 + reg_y;

                                address(7 downto 0) <= dat_in1 + reg_y;

                        end if;

                        end if;

                        address(15 downto 8) <= x"00";

                        address(15 downto 8) <= x"00";

                when x"4" =>                    --Absolute Return sub etc

                when x"4" =>                    --Absolute Return sub etc

                        if proc_write = '0' then

                        if proc_write = '0' then

                                address <= data_rd & dat_in1;

                                address <= data_rd & dat_in1;

                        else

                        else

                                address <= dat_in1 & dat_in2;

                                address <= dat_in1 & dat_in2;

                        end if;

                        end if;

                when x"5" =>                    --Absolute, x

                when x"5" =>                    --Absolute, x

                        if proc_write = '0' then

                        if proc_write = '0' then

                                address <= data_rd & dat_in1 + reg_x;

                                address <= data_rd & dat_in1 + reg_x;

                        else

                        else

                                address <= dat_in1 & dat_in2 + reg_x;

                                address <= dat_in1 & dat_in2 + reg_x;

                        end if;

                        end if;

                when x"6" =>                    --Absolute, y

                when x"6" =>                    --Absolute, y

                        if proc_write = '0' then

                        if proc_write = '0' then

                                address <= data_rd & dat_in1 + reg_y;

                                address <= data_rd & dat_in1 + reg_y;

                        else

                        else

                                address <= dat_in1 & dat_in2 + reg_y;

                                address <= dat_in1 & dat_in2 + reg_y;

                        end if;

                        end if;

                when x"7" =>                    --Stack pointer

                when x"7" =>                    --Stack pointer

                        address <= x"01" & reg_sp;              --msb should be hex 01

                        address <= x"01" & reg_sp;              --msb should be hex 01

                when x"8" =>                    --Reset 1st byte

                when x"8" =>                    --Reset 1st byte

                        address <= x"FFFC";

                        address <= x"FFFC";

                when x"9" =>                    --IRQ and Break 1st byte

                when x"9" =>                    --IRQ and Break 1st byte

                        address <= x"FFFE";

                        address <= x"FFFE";

                when x"A" =>                    --NMI and Break 1st byte

                when x"A" =>                    --NMI and Break 1st byte

                        address <= x"FFFA";

                        address <= x"FFFA";

                when x"B" =>                    --address + 1

                when x"B" =>                    --address + 1

                        address <= add_hold + "1";

                        address <= add_hold + "1";

                when x"C" =>                    --(zero),y

                when x"C" =>                    --(zero),y

                        address(7 downto 0) <= dat_in1 + "1";

                        address(7 downto 0) <= dat_in1 + "1";

                        address(15 downto 8) <= x"00";

                        address(15 downto 8) <= x"00";

                when x"D" =>                    --(zero,x)

                when x"D" =>                    --(zero,x)

                        address(7 downto 0) <= dat_in1 + reg_x + "1";

                        address(7 downto 0) <= dat_in1 + reg_x + "1";

                        address(15 downto 8) <= x"00";

                        address(15 downto 8) <= x"00";

                        address <= add_hold;

                        address <= add_hold;

                when others =>

                when others =>

                        address <= reg_pc;

                        address <= reg_pc;

        end case;

        end case;

end if;

end if;

end process addressing;

end process addressing;

hold_address:process(clock, reset, address)

hold_address:process(clock, reset, address)

begin                   --hold address bus for inc type instructions.

begin                   --hold address bus for inc type instructions.

if reset = '0' then

if reset = '0' then

        add_hold <= (others => '0');

        add_hold <= (others => '0');

elsif rising_edge(clock) then

elsif rising_edge(clock) then

        add_hold <= address;

        add_hold <= address;

end if;

end if;

end process hold_address;

end process hold_address;

memory_proc_write:process(clock, reset, wr_fg)

memory_proc_write:process(clock, reset, wr_fg)

begin

begin

if reset = '0' then

if reset = '0' then

        data_wr <= (others => '0');

        data_wr <= (others => '0');

        proc_write <= '0';

        proc_write <= '0';

elsif rising_edge(clock) then

elsif rising_edge(clock) then

        proc_write <= wr_fg;

        proc_write <= wr_fg;

                data_wr <= dat_out;

                data_wr <= dat_out;

end if;

end if;

end process memory_proc_write;

end process memory_proc_write;

instruction_decode:process (clock, reset, irq, nmi)

instruction_decode:process (clock, reset, irq, nmi)

begin

begin

if reset = '0' then

if reset = '0' then

        cycle_ctr <= (others => '0');

        cycle_ctr <= (others => '0');

        pc_inc_fg <= '0';

        pc_inc_fg <= '0';

        pc_dec_fg <= '0';

        pc_dec_fg <= '0';

        dat2pc_fg <= '0';

        dat2pc_fg <= '0';

        add_fg <= (others => '0');

        add_fg <= (others => '0');

        branch_fg <= '0';

        branch_fg <= '0';

        flags_fg <= (others => '0');

        flags_fg <= (others => '0');

        wr_fg <= '0';

        wr_fg <= '0';

        reg_a <= (others => '0');

        reg_a <= (others => '0');

        reg_x <= (others => '0');

        reg_x <= (others => '0');

        reg_y <= (others => '0');

        reg_y <= (others => '0');

        n_fg <= '0';

        n_fg <= '0';

        v_fg <= '0';

        v_fg <= '0';

        b_fg <= '0';

        b_fg <= '0';

        d_fg <= '0';

        d_fg <= '0';

        z_fg <= '0';

        z_fg <= '0';

        reset_fg <= '0';

        reset_fg <= '0';

        start_fg <= '0';

        start_fg <= '0';

        v_ff <= '0';

        v_ff <= '0';

        nmi_fg <= '0';

        nmi_fg <= '0';

        irq_fg <= '0';

        irq_fg <= '0';

        dat_out <= (others => '0');

        dat_out <= (others => '0');

elsif rising_edge(clock) then

elsif rising_edge(clock) then

        reset_fg <= reset;

        reset_fg <= reset;

--      This section is to get started

--      This section is to get started

                if reset = '1' and reset_fg = '0' then

                if reset = '1' and reset_fg = '0' then

                        start_fg <= '1';

                        start_fg <= '1';

                        wr_fg <= '0';

                        wr_fg <= '0';

                        add_fg <= x"8";         --get start up vectors FFFC FFFD

                        add_fg <= x"8";         --get start up vectors FFFC FFFD

--              end if;

--              end if;

        else

        else

        case cycle_ctr is               --cycle counter case

        case cycle_ctr is               --cycle counter case

                when x"0" =>

                when x"0" =>

                        if  reset_fg = '1' and reset = '1' then

                        if  reset_fg = '1' and reset = '1' then

                                if flags_fg /= "00" then

                                if flags_fg /= "00" then

                                        n_fg <= dat_out(7);

                                        n_fg <= dat_out(7);

                                        if dat_out = x"00" then

                                        if dat_out = x"00" then

                                                z_fg <= '1';

                                                z_fg <= '1';

                                        else

                                        else

                                                z_fg <= '0';

                                                z_fg <= '0';

                                        end if;

                                        end if;

                                end if;

                                end if;

                                if flags_fg = "10" then

                                if flags_fg = "10" then

                                        start_fg <= '0';

                                        start_fg <= '0';

                                        v_fg <= reg_a(7) xnor v_ff;     --Add V_ff true overflow possible

                                        v_fg <= reg_a(7) xnor v_ff;     --Add V_ff true overflow possible

--                                                                      --Sub V_ff false underflow possible

--                                                                      --Sub V_ff false underflow possible

                                end if;

                                end if;

                        flags_fg <= "00";

                        flags_fg <= "00";

                        end if;

                        end if;

                        if irq = '0' and i_fg = '0' then

                        if irq = '0' and i_fg = '0' then

                                irq_fg <= '1';

                                irq_fg <= '1';

                                pc_dec_fg <= '1';

                                pc_dec_fg <= '1';

                                cycle_ctr <= cycle_ctr + x"1";

                                cycle_ctr <= cycle_ctr + x"1";

                                nmi_fg <= '1';

                                nmi_fg <= '1';

                                pc_dec_fg <= '1';

                                pc_dec_fg <= '1';

                                cycle_ctr <= cycle_ctr + x"1";

                                cycle_ctr <= cycle_ctr + x"1";

                        else

                        else

                        case data_rd is

                        case data_rd is

--      ===========================================================================================

--      ===========================================================================================

                                when x"48" =>                   --PHA 1st part accumulator onto stack

                                when x"48" =>                   --PHA 1st part accumulator onto stack

                                        wr_fg <= '1';

                                        wr_fg <= '1';

                                        dat_out <= reg_a(7 downto 0);

                                        dat_out <= reg_a(7 downto 0);

                                        pc_dec_fg <= '1';

                                        pc_dec_fg <= '1';

                                        cycle_ctr <= cycle_ctr + x"1";

                                        cycle_ctr <= cycle_ctr + x"1";

                                when x"08" =>                   --PHP 1st part status onto stack

                                when x"08" =>                   --PHP 1st part status onto stack

                                        cycle_ctr <= cycle_ctr + x"1";

                                        cycle_ctr <= cycle_ctr + x"1";

                                when x"68" =>                   --PLA  1st part Pull Accumulator from Stack

                                when x"68" =>                   --PLA  1st part Pull Accumulator from Stack

                                        pc_dec_fg <= '1';

                                        pc_dec_fg <= '1';

                                        cycle_ctr <= cycle_ctr + x"1";

                                        cycle_ctr <= cycle_ctr + x"1";

                                when x"28" =>                   --PLP 1st part pull old status from stack

                                when x"28" =>                   --PLP 1st part pull old status from stack

                                        pc_dec_fg <= '1';

                                        pc_dec_fg <= '1';

                                        cycle_ctr <= cycle_ctr + x"1";

                                        cycle_ctr <= cycle_ctr + x"1";

                                when x"18" =>                   --CLC clear carry

                                when x"18" =>                   --CLC clear carry

                                        reg_a(8) <= '0';

                                        reg_a(8) <= '0';

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"38" =>                   --SEC set carry

                                when x"38" =>                   --SEC set carry

                                        reg_a(8) <= '1';

                                        reg_a(8) <= '1';

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"58" =>                   --CLI  Clear interrupt Disable Bit

                                when x"58" =>                   --CLI  Clear interrupt Disable Bit

                                        i_fg <= '0';

                                        i_fg <= '0';

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"78" =>                   --SEI  Set interrupt Disable Status

                                when x"78" =>                   --SEI  Set interrupt Disable Status

                                        i_fg <= '1';

                                        i_fg <= '1';

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"88" =>                   --DEY Decrement y reg

                                when x"88" =>                   --DEY Decrement y reg

                                        reg_y <= reg_y - "1";

                                        reg_y <= reg_y - "1";

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_y - "1";

                                        dat_out <= reg_y - "1";

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"98" =>                   --TYA transfer Y to A

                                when x"98" =>                   --TYA transfer Y to A

                                        reg_a(7 downto 0) <= reg_y;

                                        reg_a(7 downto 0) <= reg_y;

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_y;

                                        dat_out <= reg_y;

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"A8" =>                   --TAY transfer A to Y

                                when x"A8" =>                   --TAY transfer A to Y

                                        reg_y <= reg_a(7 downto 0);

                                        reg_y <= reg_a(7 downto 0);

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_a(7 downto 0);

                                        dat_out <= reg_a(7 downto 0);

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"B8" =>                   --CLV clear overflow flag

                                when x"B8" =>                   --CLV clear overflow flag

                                        v_fg <= '0';

                                        v_fg <= '0';

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"C8" =>                   --INY increment Y reg

                                when x"C8" =>                   --INY increment Y reg

                                        reg_y <= reg_y + x"1";

                                        reg_y <= reg_y + x"1";

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_y + x"1";

                                        dat_out <= reg_y + x"1";

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"D8" =>                   --CLD Clear decimnal flag

                                when x"D8" =>                   --CLD Clear decimnal flag

                                        d_fg <= '0';

                                        d_fg <= '0';

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"E8" =>                   --INX increment X reg

                                when x"E8" =>                   --INX increment X reg

                                        reg_x <= reg_x + x"1";

                                        reg_x <= reg_x + x"1";

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_x + x"1";

                                        dat_out <= reg_x + x"1";

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"F8" =>                   --SLD Set decimnal flag

                                when x"F8" =>                   --SLD Set decimnal flag

                                        d_fg <= '1';

                                        d_fg <= '1';

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"2A" =>                   --ROL A Rotate Left one bit 1st part.

                                when x"2A" =>                   --ROL A Rotate Left one bit 1st part.

                                        reg_a(8 downto 1) <= reg_a(7 downto 0);

                                        reg_a(8 downto 1) <= reg_a(7 downto 0);

                                        reg_a(0) <= reg_a(8);

                                        reg_a(0) <= reg_a(8);

                                        dat_out(7 downto 1) <= reg_a(6 downto 0);

                                        dat_out(7 downto 1) <= reg_a(6 downto 0);

                                        dat_out(0) <= reg_a(8);

                                        dat_out(0) <= reg_a(8);

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        cycle_ctr <=  x"0";

                                        cycle_ctr <=  x"0";

                                when x"6A" =>                   --ROR A Rotateft right one bit 1st part.

                                when x"6A" =>                   --ROR A Rotateft right one bit 1st part.

                                        reg_a(7 downto 0) <= reg_a(8 downto 1);

                                        reg_a(7 downto 0) <= reg_a(8 downto 1);

                                        reg_a(8) <= reg_a(0);

                                        reg_a(8) <= reg_a(0);

                                        dat_out <= reg_a(8 downto 1);

                                        dat_out <= reg_a(8 downto 1);

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        cycle_ctr <=  x"0";

                                        cycle_ctr <=  x"0";

                                when x"0A" =>                   --ASL A Shift Left one bit 1st part.

                                when x"0A" =>                   --ASL A Shift Left one bit 1st part.

                                        reg_a <= reg_a(7 downto 0) & '0';

                                        reg_a <= reg_a(7 downto 0) & '0';

                                        dat_out <= reg_a(6 downto 0) & '0';

                                        dat_out <= reg_a(6 downto 0) & '0';

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        cycle_ctr <=  x"0";

                                        cycle_ctr <=  x"0";

                                when x"4A" =>                   --LSR A Logical Shift Right one bit 1st part.

                                when x"4A" =>                   --LSR A Logical Shift Right one bit 1st part.

                                        reg_a(7 downto 0) <= '0' & reg_a(7 downto 1);

                                        reg_a(7 downto 0) <= '0' & reg_a(7 downto 1);

                                        reg_a(8) <= reg_a(0);

                                        reg_a(8) <= reg_a(0);

                                        dat_out <= '0' & reg_a(7 downto 1);

                                        dat_out <= '0' & reg_a(7 downto 1);

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        cycle_ctr <=  x"0";

                                        cycle_ctr <=  x"0";

                                when x"9A" =>                   --TXS

                                when x"9A" =>                   --TXS

                                        reg_sp <= reg_x;

                                        reg_sp <= reg_x;

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"AA" =>                   --TAX

                                when x"AA" =>                   --TAX

                                        reg_x <= reg_a(7 downto 0);

                                        reg_x <= reg_a(7 downto 0);

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_a(7 downto 0);

                                        dat_out <= reg_a(7 downto 0);

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"8A" =>                   --TXA

                                when x"8A" =>                   --TXA

                                        reg_a(7 downto 0) <= reg_x;

                                        reg_a(7 downto 0) <= reg_x;

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_a(7 downto 0);

                                        dat_out <= reg_a(7 downto 0);

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"BA" =>                   --TSX

                                when x"BA" =>                   --TSX

                                        reg_x <= reg_sp;

                                        reg_x <= reg_sp;

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_sp;

                                        dat_out <= reg_sp;

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

                                when x"CA" =>                   --DEX

                                when x"CA" =>                   --DEX

                                        reg_x <= reg_X - X"01";

                                        reg_x <= reg_X - X"01";

                                        flags_fg <= "01";

                                        flags_fg <= "01";

                                        dat_out <= reg_x - X"01";

                                        dat_out <= reg_x - X"01";

                                        cycle_ctr <= x"0";

                                        cycle_ctr <= x"0";

--      =============================================================================================

--      =============================================================================================

                                when x"F0" =>                   --BEQ branch true 1st part.

                                when x"F0" =>                   --BEQ branch true 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

                                when x"D0" =>                   --BNE branch true 1st part.

                                when x"D0" =>                   --BNE branch true 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

                                when x"10" =>                   --BPL plus true 1st part.

                                when x"10" =>                   --BPL plus true 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

                                when x"30" =>                   --BM1 negative true 1st part.

                                when x"30" =>                   --BM1 negative true 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

                                when x"50" =>                   --BVC overflow false 1st part.

                                when x"50" =>                   --BVC overflow false 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

                                when x"70" =>                   --BVS overflow true 1st part.

                                when x"70" =>                   --BVS overflow true 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

                                when x"90" =>                   --BCC carry false 1st part.

                                when x"90" =>                   --BCC carry false 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

                                when x"B0" =>                   --BCS carry true 1st part.

                                when x"B0" =>                   --BCS carry true 1st part.

                                                cycle_ctr <= cycle_ctr + "1";

                                                cycle_ctr <= cycle_ctr + "1";

--      =============================================================================================

--      =============================================================================================

                                when x"A2" =>                   --LDX #.  1st partProto imediate instruction

                                when x"A2" =>                   --LDX #.  1st partProto imediate instruction

                                        pc_inc_fg <= '1';

                                        pc_inc_fg <= '1';

                                        cycle_ctr <= cycle_ctr + "1";