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/**************************************
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Author: J.W Tang
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Email: jaytang1987@hotmail.com
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Module: feature_accumulator
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Date: 2016-04-24
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Copyright (C) 2016 J.W. Tang
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----------------------------
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This file is part of LinkRunCCA.
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LinkRunCCA is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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LinkRunCCA is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with LinkRunCCA. If not, see <http://www.gnu.org/licenses/>.
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By using LinkRunCCA in any or associated publication,
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you agree to cite it as:
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Tang, J. W., et al. "A linked list run-length-based single-pass
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connected component analysis for real-time embedded hardware."
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Journal of Real-Time Image Processing: 1-19. 2016.
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doi:10.1007/s11554-016-0590-2.
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***************************************/
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module feature_accumulator(
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module feature_accumulator(
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clk,rst,datavalid,DAC,DMG,CLR,dp,d
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clk,rst,datavalid,DAC,DMG,CLR,dp,d
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);
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);
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parameter imwidth=512;
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parameter imwidth=512;
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parameter imheight=512;
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parameter imheight=512;
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parameter x_bit=9;
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parameter x_bit=9;
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parameter y_bit=9;
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parameter y_bit=9;
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parameter address_bit=8;
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parameter address_bit=8;
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parameter data_bit=38;
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parameter data_bit=38;
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parameter latency=3; //latency to offset counter x, 3 if holes filling, else 1
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parameter latency=3; //latency to offset counter x, 3 if holes filling, else 1
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parameter rstx=imwidth-latency;
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parameter rstx=imwidth-latency;
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parameter rsty=imheight-1;
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parameter rsty=imheight-1;
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parameter compx=imwidth-1;
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parameter compx=imwidth-1;
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input clk,rst,datavalid,DAC,DMG,CLR;
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input clk,rst,datavalid,DAC,DMG,CLR;
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input [data_bit-1:0]dp;
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input [data_bit-1:0]dp;
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output reg[data_bit-1:0]d;
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output reg[data_bit-1:0]d;
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////coordinate counter
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////coordinate counter
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reg [x_bit-1:0]x;
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reg [x_bit-1:0]x;
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reg [y_bit-1:0]y;
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reg [y_bit-1:0]y;
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always@(posedge clk or posedge rst)
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always@(posedge clk or posedge rst)
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if(rst)begin
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if(rst)begin
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x<=rstx[x_bit-1:0];y<=rsty[y_bit-1:0];
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x<=rstx[x_bit-1:0];y<=rsty[y_bit-1:0];
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end
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end
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else if(datavalid)begin
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else if(datavalid)begin
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if(x==compx[x_bit-1:0])begin
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if(x==compx[x_bit-1:0])begin
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x<=0;
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x<=0;
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if(y==rsty[y_bit-1:0])
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if(y==rsty[y_bit-1:0])
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y<=0;
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y<=0;
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else y<=y+1;
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else y<=y+1;
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end
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end
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else x<=x+1;
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else x<=x+1;
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end
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end
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/////register d
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/////register d
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wire [x_bit-1:0]minx,maxx,minx1,maxx1;
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wire [x_bit-1:0]minx,maxx,minx1,maxx1;
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wire [y_bit-1:0]miny,maxy,miny1,maxy1;
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wire [y_bit-1:0]miny,maxy,miny1,maxy1;
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//data accumulate
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//data accumulate
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assign minx1=(DAC&(x<d[data_bit-1:data_bit-x_bit]))?x:d[data_bit-1:data_bit-x_bit];
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assign minx1=(DAC&(x<d[data_bit-1:data_bit-x_bit]))?x:d[data_bit-1:data_bit-x_bit];
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assign maxx1=(DAC&(x>d[data_bit-x_bit-1:2*y_bit]))?x:d[data_bit-x_bit-1:2*y_bit];
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assign maxx1=(DAC&(x>d[data_bit-x_bit-1:2*y_bit]))?x:d[data_bit-x_bit-1:2*y_bit];
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assign miny1=(DAC&(y<d[2*y_bit-1:y_bit]))?y:d[2*y_bit-1:y_bit];
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assign miny1=(DAC&(y<d[2*y_bit-1:y_bit]))?y:d[2*y_bit-1:y_bit];
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assign maxy1=(DAC&(y>d[y_bit-1:0]))?y:d[y_bit-1:0];
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assign maxy1=(DAC&(y>d[y_bit-1:0]))?y:d[y_bit-1:0];
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//data merge
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//data merge
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assign minx=(DMG&(dp[data_bit-1:data_bit-x_bit]<minx1))?dp[data_bit-1:data_bit-x_bit]:minx1;
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assign minx=(DMG&(dp[data_bit-1:data_bit-x_bit]<minx1))?dp[data_bit-1:data_bit-x_bit]:minx1;
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assign maxx=(DMG&(dp[data_bit-x_bit-1:2*y_bit]>maxx1))?dp[data_bit-x_bit-1:2*y_bit]:maxx1;
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assign maxx=(DMG&(dp[data_bit-x_bit-1:2*y_bit]>maxx1))?dp[data_bit-x_bit-1:2*y_bit]:maxx1;
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assign miny=(DMG&(dp[2*y_bit-1:y_bit]<miny1))?dp[2*y_bit-1:y_bit]:miny1;
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assign miny=(DMG&(dp[2*y_bit-1:y_bit]<miny1))?dp[2*y_bit-1:y_bit]:miny1;
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assign maxy=(DMG&(dp[y_bit-1:0]>maxy1))?dp[y_bit-1:0]:maxy1;
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assign maxy=(DMG&(dp[y_bit-1:0]>maxy1))?dp[y_bit-1:0]:maxy1;
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always@(posedge clk or posedge rst)
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always@(posedge clk or posedge rst)
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if(rst)
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if(rst)
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d<={{x_bit{1'b1}},{x_bit{1'b0}},{y_bit{1'b1}},{y_bit{1'b0}}};
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d<={{x_bit{1'b1}},{x_bit{1'b0}},{y_bit{1'b1}},{y_bit{1'b0}}};
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else if(datavalid)
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else if(datavalid)
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if(CLR)
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if(CLR)
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d<={{x_bit{1'b1}},{x_bit{1'b0}},{y_bit{1'b1}},{y_bit{1'b0}}}; //CLR
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d<={{x_bit{1'b1}},{x_bit{1'b0}},{y_bit{1'b1}},{y_bit{1'b0}}}; //CLR
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else d<={minx,maxx,miny,maxy};
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else d<={minx,maxx,miny,maxy};
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endmodule
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endmodule
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