---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Instruction decoder
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-- Instruction decoder
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- The second stage of the LXP32 pipeline.
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-- The second stage of the LXP32 pipeline.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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entity lxp32_decode is
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entity lxp32_decode is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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|
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word_i: in std_logic_vector(31 downto 0);
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word_i: in std_logic_vector(31 downto 0);
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next_ip_i: in std_logic_vector(29 downto 0);
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next_ip_i: in std_logic_vector(29 downto 0);
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current_ip_i: in std_logic_vector(29 downto 0);
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current_ip_i: in std_logic_vector(29 downto 0);
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valid_i: in std_logic;
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valid_i: in std_logic;
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jump_valid_i: in std_logic;
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jump_valid_i: in std_logic;
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ready_o: out std_logic;
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ready_o: out std_logic;
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interrupt_valid_i: in std_logic;
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interrupt_valid_i: in std_logic;
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interrupt_vector_i: in std_logic_vector(2 downto 0);
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interrupt_vector_i: in std_logic_vector(2 downto 0);
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interrupt_ready_o: out std_logic;
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interrupt_ready_o: out std_logic;
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wakeup_i: in std_logic;
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sp_raddr1_o: out std_logic_vector(7 downto 0);
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sp_raddr1_o: out std_logic_vector(7 downto 0);
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sp_rdata1_i: in std_logic_vector(31 downto 0);
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sp_rdata1_i: in std_logic_vector(31 downto 0);
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sp_raddr2_o: out std_logic_vector(7 downto 0);
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sp_raddr2_o: out std_logic_vector(7 downto 0);
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sp_rdata2_i: in std_logic_vector(31 downto 0);
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sp_rdata2_i: in std_logic_vector(31 downto 0);
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ready_i: in std_logic;
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ready_i: in std_logic;
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valid_o: out std_logic;
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valid_o: out std_logic;
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cmd_loadop3_o: out std_logic;
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cmd_loadop3_o: out std_logic;
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cmd_signed_o: out std_logic;
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cmd_signed_o: out std_logic;
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cmd_dbus_o: out std_logic;
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cmd_dbus_o: out std_logic;
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cmd_dbus_store_o: out std_logic;
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cmd_dbus_store_o: out std_logic;
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cmd_dbus_byte_o: out std_logic;
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cmd_dbus_byte_o: out std_logic;
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cmd_addsub_o: out std_logic;
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cmd_addsub_o: out std_logic;
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cmd_mul_o: out std_logic;
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cmd_mul_o: out std_logic;
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cmd_div_o: out std_logic;
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cmd_div_o: out std_logic;
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cmd_div_mod_o: out std_logic;
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cmd_div_mod_o: out std_logic;
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cmd_cmp_o: out std_logic;
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cmd_cmp_o: out std_logic;
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cmd_jump_o: out std_logic;
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cmd_jump_o: out std_logic;
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cmd_negate_op2_o: out std_logic;
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cmd_negate_op2_o: out std_logic;
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cmd_and_o: out std_logic;
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cmd_and_o: out std_logic;
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cmd_xor_o: out std_logic;
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cmd_xor_o: out std_logic;
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cmd_shift_o: out std_logic;
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cmd_shift_o: out std_logic;
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cmd_shift_right_o: out std_logic;
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cmd_shift_right_o: out std_logic;
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jump_type_o: out std_logic_vector(3 downto 0);
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jump_type_o: out std_logic_vector(3 downto 0);
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op1_o: out std_logic_vector(31 downto 0);
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op1_o: out std_logic_vector(31 downto 0);
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op2_o: out std_logic_vector(31 downto 0);
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op2_o: out std_logic_vector(31 downto 0);
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op3_o: out std_logic_vector(31 downto 0);
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op3_o: out std_logic_vector(31 downto 0);
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dst_o: out std_logic_vector(7 downto 0)
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dst_o: out std_logic_vector(7 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_decode is
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architecture rtl of lxp32_decode is
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|
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-- Decoder FSM state
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-- Decoder FSM state
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type DecoderState is (Regular,ContinueLc,ContinueCjmp,ContinueInterrupt,Halt);
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type DecoderState is (Regular,ContinueLc,ContinueCjmp,ContinueInterrupt,Halt);
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signal state: DecoderState:=Regular;
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signal state: DecoderState:=Regular;
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-- Input instruction portions
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-- Input instruction portions
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signal opcode: std_logic_vector(5 downto 0);
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signal opcode: std_logic_vector(5 downto 0);
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signal t1: std_logic;
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signal t1: std_logic;
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signal t2: std_logic;
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signal t2: std_logic;
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signal destination: std_logic_vector(7 downto 0);
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signal destination: std_logic_vector(7 downto 0);
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signal rd1: std_logic_vector(7 downto 0);
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signal rd1: std_logic_vector(7 downto 0);
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signal rd2: std_logic_vector(7 downto 0);
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signal rd2: std_logic_vector(7 downto 0);
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-- Signals related to pipeline control
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-- Signals related to pipeline control
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signal downstream_busy: std_logic;
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signal downstream_busy: std_logic;
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signal self_busy: std_logic:='0';
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signal self_busy: std_logic:='0';
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signal busy: std_logic;
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signal busy: std_logic;
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signal valid_out: std_logic:='0';
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signal valid_out: std_logic:='0';
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|
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signal dst_out: std_logic_vector(7 downto 0);
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signal dst_out: std_logic_vector(7 downto 0);
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-- Signals related to RD operand decoding
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-- Signals related to RD operand decoding
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signal rd1_reg: std_logic_vector(7 downto 0);
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signal rd1_reg: std_logic_vector(7 downto 0);
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signal rd2_reg: std_logic_vector(7 downto 0);
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signal rd2_reg: std_logic_vector(7 downto 0);
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|
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signal rd1_select: std_logic;
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signal rd1_select: std_logic;
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signal rd1_direct: std_logic_vector(31 downto 0);
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signal rd1_direct: std_logic_vector(31 downto 0);
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signal rd2_select: std_logic;
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signal rd2_select: std_logic;
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signal rd2_direct: std_logic_vector(31 downto 0);
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signal rd2_direct: std_logic_vector(31 downto 0);
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-- Signals related to interrupt handling
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-- Signals related to interrupt handling
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signal interrupt_ready: std_logic:='0';
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signal interrupt_ready: std_logic:='0';
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signal wakeup_reg: std_logic:='0';
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begin
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begin
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-- Dissect input word
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-- Dissect input word
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opcode<=word_i(31 downto 26);
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opcode<=word_i(31 downto 26);
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t1<=word_i(25);
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t1<=word_i(25);
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t2<=word_i(24);
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t2<=word_i(24);
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destination<=word_i(23 downto 16);
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destination<=word_i(23 downto 16);
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rd1<=word_i(15 downto 8);
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rd1<=word_i(15 downto 8);
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rd2<=word_i(7 downto 0);
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rd2<=word_i(7 downto 0);
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-- Pipeline control
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-- Pipeline control
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downstream_busy<=valid_out and not ready_i;
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downstream_busy<=valid_out and not ready_i;
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busy<=downstream_busy or self_busy;
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busy<=downstream_busy or self_busy;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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valid_out<='0';
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valid_out<='0';
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self_busy<='0';
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self_busy<='0';
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state<=Regular;
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state<=Regular;
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interrupt_ready<='0';
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interrupt_ready<='0';
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cmd_loadop3_o<='-';
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cmd_loadop3_o<='-';
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cmd_signed_o<='-';
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cmd_signed_o<='-';
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cmd_dbus_o<='-';
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cmd_dbus_o<='-';
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cmd_dbus_store_o<='-';
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cmd_dbus_store_o<='-';
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cmd_dbus_byte_o<='-';
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cmd_dbus_byte_o<='-';
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cmd_addsub_o<='-';
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cmd_addsub_o<='-';
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cmd_negate_op2_o<='-';
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cmd_negate_op2_o<='-';
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cmd_mul_o<='-';
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cmd_mul_o<='-';
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cmd_div_o<='-';
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cmd_div_o<='-';
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cmd_div_mod_o<='-';
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cmd_div_mod_o<='-';
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cmd_cmp_o<='-';
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cmd_cmp_o<='-';
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cmd_jump_o<='-';
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cmd_jump_o<='-';
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cmd_and_o<='-';
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cmd_and_o<='-';
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cmd_xor_o<='-';
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cmd_xor_o<='-';
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cmd_shift_o<='-';
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cmd_shift_o<='-';
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cmd_shift_right_o<='-';
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cmd_shift_right_o<='-';
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rd1_select<='-';
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rd1_select<='-';
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rd1_direct<=(others=>'-');
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rd1_direct<=(others=>'-');
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rd2_select<='-';
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rd2_select<='-';
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rd2_direct<=(others=>'-');
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rd2_direct<=(others=>'-');
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op3_o<=(others=>'-');
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op3_o<=(others=>'-');
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jump_type_o<=(others=>'-');
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jump_type_o<=(others=>'-');
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dst_out<=(others=>'-');
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dst_out<=(others=>'-');
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wakeup_reg<='0';
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else
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else
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interrupt_ready<='0';
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interrupt_ready<='0';
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wakeup_reg<=wakeup_reg or wakeup_i;
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if jump_valid_i='1' then
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if jump_valid_i='1' then
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valid_out<='0';
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valid_out<='0';
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self_busy<='0';
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self_busy<='0';
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state<=Regular;
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state<=Regular;
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elsif downstream_busy='0' then
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elsif downstream_busy='0' then
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op3_o<=(others=>'-');
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op3_o<=(others=>'-');
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rd1_direct<=std_logic_vector(resize(signed(rd1),rd1_direct'length));
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rd1_direct<=std_logic_vector(resize(signed(rd1),rd1_direct'length));
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rd2_direct<=std_logic_vector(resize(signed(rd2),rd2_direct'length));
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rd2_direct<=std_logic_vector(resize(signed(rd2),rd2_direct'length));
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cmd_signed_o<=opcode(0);
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cmd_signed_o<=opcode(0);
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cmd_div_mod_o<=opcode(1);
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cmd_div_mod_o<=opcode(1);
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cmd_shift_right_o<=opcode(1);
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cmd_shift_right_o<=opcode(1);
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cmd_dbus_byte_o<=opcode(1);
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cmd_dbus_byte_o<=opcode(1);
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cmd_dbus_store_o<=opcode(2);
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cmd_dbus_store_o<=opcode(2);
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case state is
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case state is
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when Regular =>
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when Regular =>
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cmd_loadop3_o<='0';
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cmd_loadop3_o<='0';
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cmd_dbus_o<='0';
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cmd_dbus_o<='0';
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cmd_addsub_o<='0';
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cmd_addsub_o<='0';
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cmd_negate_op2_o<='0';
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cmd_negate_op2_o<='0';
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cmd_mul_o<='0';
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cmd_mul_o<='0';
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cmd_div_o<='0';
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cmd_div_o<='0';
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cmd_cmp_o<='0';
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cmd_cmp_o<='0';
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cmd_jump_o<='0';
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cmd_jump_o<='0';
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cmd_and_o<='0';
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cmd_and_o<='0';
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cmd_xor_o<='0';
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cmd_xor_o<='0';
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cmd_shift_o<='0';
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cmd_shift_o<='0';
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jump_type_o<=opcode(3 downto 0);
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jump_type_o<=opcode(3 downto 0);
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|
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if interrupt_valid_i='1' and valid_i='1' then
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if interrupt_valid_i='1' and valid_i='1' then
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cmd_jump_o<='1';
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cmd_jump_o<='1';
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cmd_loadop3_o<='1';
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cmd_loadop3_o<='1';
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op3_o<=current_ip_i&"01"; -- LSB indicates interrupt return
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op3_o<=current_ip_i&"01"; -- LSB indicates interrupt return
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dst_out<=X"FD"; -- interrupt return pointer
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dst_out<=X"FD"; -- interrupt return pointer
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rd1_select<='1';
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rd1_select<='1';
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rd2_select<='0';
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rd2_select<='0';
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valid_out<='1';
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valid_out<='1';
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interrupt_ready<='1';
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interrupt_ready<='1';
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self_busy<='1';
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self_busy<='1';
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state<=ContinueInterrupt;
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state<=ContinueInterrupt;
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else
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else
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if opcode(5 downto 3)="101" or opcode="000001" then -- lc or lcs
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if opcode(5 downto 3)="101" or opcode="000001" then -- lc or lcs
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cmd_loadop3_o<='1';
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cmd_loadop3_o<='1';
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-- Setting op3_o here only affects the lcs instruction
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-- Setting op3_o here only affects the lcs instruction
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op3_o<=std_logic_vector(resize(signed(opcode(2 downto 0)&
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op3_o<=std_logic_vector(resize(signed(opcode(2 downto 0)&
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t1&t2&rd1&rd2),op3_o'length));
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t1&t2&rd1&rd2),op3_o'length));
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end if;
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end if;
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|
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if opcode(5 downto 3)="001" then
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if opcode(5 downto 3)="001" then
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cmd_dbus_o<='1';
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cmd_dbus_o<='1';
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end if;
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end if;
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|
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if opcode(5 downto 1)="01000" then
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if opcode(5 downto 1)="01000" then
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cmd_addsub_o<='1';
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cmd_addsub_o<='1';
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end if;
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end if;
|
|
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cmd_negate_op2_o<=opcode(0);
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cmd_negate_op2_o<=opcode(0);
|
|
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if opcode="010010" then
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if opcode="010010" then
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cmd_mul_o<='1';
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cmd_mul_o<='1';
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end if;
|
end if;
|
|
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if opcode(5 downto 2)="0101" then
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if opcode(5 downto 2)="0101" then
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cmd_div_o<='1';
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cmd_div_o<='1';
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end if;
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end if;
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|
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if opcode(5 downto 3)="100" then -- jump or call
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if opcode(5 downto 3)="100" then -- jump or call
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cmd_jump_o<='1';
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cmd_jump_o<='1';
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cmd_loadop3_o<=opcode(0);
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cmd_loadop3_o<=opcode(0);
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-- Setting op3_o here only affects the call instruction
|
-- Setting op3_o here only affects the call instruction
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op3_o<=next_ip_i&"00";
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op3_o<=next_ip_i&"00";
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end if;
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end if;
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|
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-- Note: (a or b) = (a and b) or (a xor b)
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-- Note: (a or b) = (a and b) or (a xor b)
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|
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if opcode(5 downto 1)="01100" then
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if opcode(5 downto 1)="01100" then
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cmd_and_o<='1';
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cmd_and_o<='1';
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end if;
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end if;
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|
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if opcode="011010" or opcode="011001" then
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if opcode="011010" or opcode="011001" then
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cmd_xor_o<='1';
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cmd_xor_o<='1';
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end if;
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end if;
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|
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if opcode(5 downto 2)="0111" then
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if opcode(5 downto 2)="0111" then
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cmd_shift_o<='1';
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cmd_shift_o<='1';
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end if;
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end if;
|
|
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if opcode(5 downto 4)="11" then
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if opcode(5 downto 4)="11" then
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cmd_cmp_o<='1';
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cmd_cmp_o<='1';
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cmd_negate_op2_o<='1';
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cmd_negate_op2_o<='1';
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end if;
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end if;
|
|
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rd1_select<=t1;
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rd1_select<=t1;
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rd2_select<=t2;
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rd2_select<=t2;
|
|
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dst_out<=destination;
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dst_out<=destination;
|
|
|
if valid_i='1' then
|
if valid_i='1' then
|
if opcode="000001" then
|
if opcode="000001" then
|
valid_out<='0';
|
valid_out<='0';
|
self_busy<='0';
|
self_busy<='0';
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state<=ContinueLc;
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state<=ContinueLc;
|
elsif opcode="000010" then
|
elsif opcode="000010" then
|
valid_out<='0';
|
valid_out<='0';
|
self_busy<='1';
|
self_busy<='1';
|
|
wakeup_reg<='0';
|
state<=Halt;
|
state<=Halt;
|
elsif opcode(5 downto 4)="11" then
|
elsif opcode(5 downto 4)="11" then
|
valid_out<='1';
|
valid_out<='1';
|
self_busy<='1';
|
self_busy<='1';
|
state<=ContinueCjmp;
|
state<=ContinueCjmp;
|
else
|
else
|
valid_out<='1';
|
valid_out<='1';
|
end if;
|
end if;
|
else
|
else
|
valid_out<='0';
|
valid_out<='0';
|
end if;
|
end if;
|
end if;
|
end if;
|
when ContinueLc =>
|
when ContinueLc =>
|
if valid_i='1' then
|
if valid_i='1' then
|
valid_out<='1';
|
valid_out<='1';
|
op3_o<=word_i;
|
op3_o<=word_i;
|
self_busy<='0';
|
self_busy<='0';
|
state<=Regular;
|
state<=Regular;
|
end if;
|
end if;
|
when ContinueCjmp =>
|
when ContinueCjmp =>
|
valid_out<='1';
|
valid_out<='1';
|
cmd_jump_o<='1';
|
cmd_jump_o<='1';
|
rd1_select<='1';
|
rd1_select<='1';
|
self_busy<='0';
|
self_busy<='0';
|
state<=Regular;
|
state<=Regular;
|
when ContinueInterrupt =>
|
when ContinueInterrupt =>
|
valid_out<='0';
|
valid_out<='0';
|
when Halt =>
|
when Halt =>
|
if interrupt_valid_i='1' then
|
if interrupt_valid_i='1' or wakeup_i='1' or wakeup_reg='1' then
|
self_busy<='0';
|
self_busy<='0';
|
state<=Regular;
|
state<=Regular;
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
valid_o<=valid_out;
|
valid_o<=valid_out;
|
dst_o<=dst_out;
|
dst_o<=dst_out;
|
|
|
ready_o<=not busy;
|
ready_o<=not busy;
|
|
|
interrupt_ready_o<=interrupt_ready;
|
interrupt_ready_o<=interrupt_ready;
|
|
|
-- Decode RD (register/direct) operands
|
-- Decode RD (register/direct) operands
|
|
|
process (clk_i) is
|
process (clk_i) is
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if busy='0' then
|
if busy='0' then
|
rd1_reg<=rd1;
|
rd1_reg<=rd1;
|
rd2_reg<=rd2;
|
rd2_reg<=rd2;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
sp_raddr1_o<="11110"&interrupt_vector_i when (state=Regular and interrupt_valid_i='1' and downstream_busy='0') or state=ContinueInterrupt else
|
sp_raddr1_o<="11110"&interrupt_vector_i when (state=Regular and interrupt_valid_i='1' and downstream_busy='0') or state=ContinueInterrupt else
|
dst_out when (state=ContinueCjmp and downstream_busy='0') else
|
dst_out when (state=ContinueCjmp and downstream_busy='0') else
|
rd1_reg when busy='1' else
|
rd1_reg when busy='1' else
|
rd1;
|
rd1;
|
|
|
sp_raddr2_o<=rd2_reg when busy='1' else rd2;
|
sp_raddr2_o<=rd2_reg when busy='1' else rd2;
|
|
|
op1_o<=sp_rdata1_i when rd1_select='1' else rd1_direct;
|
op1_o<=sp_rdata1_i when rd1_select='1' else rd1_direct;
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op2_o<=sp_rdata2_i when rd2_select='1' else rd2_direct;
|
op2_o<=sp_rdata2_i when rd2_select='1' else rd2_direct;
|
|
|
end architecture;
|
end architecture;
|
|
|
