////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright 2013 by Michael A. Morris, dba M. A. Morris & Associates
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// Copyright 2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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//
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// All rights reserved. The source code contained herein is publicly released
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// All rights reserved. The source code contained herein is publicly released
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// this source code may be reproduced or transmitted in any form or by any
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// this source code may be reproduced or transmitted in any form or by any
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// means, electronic or mechanical, including photocopying, recording, or any
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// means, electronic or mechanical, including photocopying, recording, or any
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// information storage and retrieval system in violation of the license under
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// information storage and retrieval system in violation of the license under
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// which the source code is released.
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// which the source code is released.
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//
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//
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// The source code contained herein is free; it may be redistributed and/or
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// The source code contained herein is free; it may be redistributed and/or
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// modified in accordance with the terms of the GNU Lesser General Public
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// modified in accordance with the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either version 2.1 of
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// License as published by the Free Software Foundation; either version 2.1 of
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// the GNU Lesser General Public License, or any later version.
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// the GNU Lesser General Public License, or any later version.
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//
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//
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// more details.)
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// more details.)
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//
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//
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// A copy of the GNU Lesser General Public License should have been received
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// A copy of the GNU Lesser General Public License should have been received
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// along with the source code contained herein; if not, a copy can be obtained
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// along with the source code contained herein; if not, a copy can be obtained
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// by writing to:
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// by writing to:
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//
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//
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// Free Software Foundation, Inc.
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// Free Software Foundation, Inc.
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// 51 Franklin Street, Fifth Floor
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// 51 Franklin Street, Fifth Floor
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// Boston, MA 02110-1301 USA
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// Boston, MA 02110-1301 USA
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//
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//
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// Further, no use of this source code is permitted in any form or means
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// Further, no use of this source code is permitted in any form or means
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// without inclusion of this banner prominently in any derived works.
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// without inclusion of this banner prominently in any derived works.
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//
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//
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// Michael A. Morris
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// Michael A. Morris
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// Huntsville, AL
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// Huntsville, AL
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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// Engineer: Michael A. Morris
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//
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//
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// Create Date: 12:06:18 08/18/2013
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// Create Date: 12:06:18 08/18/2013
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// Design Name: M65C02 -
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// Design Name: WDC W65C02 Microprocessor Re-Implementation
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// Module Name: M65C02_IntHndlr.v
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// Module Name: M65C02_IntHndlr.v
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// Project Name: C:\XProjects\ISE10.1i\M65C02
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// Project Name: C:\XProjects\ISE10.1i\M65C02
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// Target Devices: SRAM-based FPGAs: XC3S50A-xVQ100I, XC3S200A-xVQ100I
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// Target Devices: SRAM-based FPGAs: XC3S50A-xVQ100I, XC3S200A-xVQ100I
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// Tool versions: Xilinx ISE 10.1i SP3
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// Tool versions: Xilinx ISE 10.1i SP3
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//
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//
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// Description:
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// Description:
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//
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//
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// This module implements a simple interrupt handler for the M65C02 soft-core
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// This module implements a simple interrupt handler for the M65C02 soft-core
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// microprocessor. It accepts external active low inputs for Non-Maskable
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// microprocessor. It accepts external active low inputs for Non-Maskable
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// Interrupt request (nNMI) and maskable Interrupt ReQuest (nIRQ). It synchro-
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// Interrupt request (nNMI) and maskable Interrupt ReQuest (nIRQ). It synchro-
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// nizes both inputs to the internal system clock (Clk), and generates internal
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// nizes both inputs to the internal system clock (Clk), and generates internal
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// signals NMI and IRQ. NMI is falling edge sensitive, and IRQ is active low
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// signals NMI and IRQ. NMI is falling edge sensitive, and IRQ is active low
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// level sensitive. The module also accepts the core's mode output (Mode) and
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// level sensitive. The module also accepts the core's mode output (Mode) and
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// generates an internal BReaK software trap request (BRK).
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// generates an internal BReaK software trap request (BRK).
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//
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//
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// The non-maskable interrupt request, nNMI, has priority, followed by BRK, and
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// The non-maskable interrupt request, nNMI, has priority, followed by BRK, and
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// finally nIRQ. The core, from the I bit in the processor register, provides a
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// finally nIRQ. The core, from the I bit in the processor register, provides a
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// mask that prevents the generation of the internal IRQ signal.
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// mask that prevents the generation of the internal IRQ signal.
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//
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//
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// Vectors for each of the four interrupt/trap sources are set using para-
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// Vectors for each of the four interrupt/trap sources are set using para-
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// meters. The current implementation aims to maintain compatibility with the
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// meters. The current implementation aims to maintain compatibility with the
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// WDC W65C02S processor, so IRQ and BRK share the same vector. A quick edit
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// WDC W65C02S processor, so IRQ and BRK share the same vector. A quick edit
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// of the parameters allows an independent vector location to be added for BRK.
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// of the parameters allows an independent vector location to be added for BRK.
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// Similarly, the vectors for any of the interrupt/trap sources can be moved
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// Similarly, the vectors for any of the interrupt/trap sources can be moved
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// to any location in the memory space, if W65C02S compatibility is not desired
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// to any location in the memory space, if W65C02S compatibility is not desired
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// or required.
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// or required.
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//
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//
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// Dependencies: fedet.v
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// Dependencies: fedet.v
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//
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//
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// Revision:
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// Revision:
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//
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//
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// 0.01 13H18 MAM File Created
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// 0.01 13H18 MAM File Created
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//
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//
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// Additional Comments:
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// Additional Comments:
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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module M65C02_IntHndlr #(
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module M65C02_IntHndlr #(
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parameter pIRQ_Vector = 16'hFFFE,
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parameter pIRQ_Vector = 16'hFFFE,
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parameter pBRK_Vector = 16'hFFFE,
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parameter pBRK_Vector = 16'hFFFE,
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parameter pRST_Vector = 16'hFFFC,
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parameter pRST_Vector = 16'hFFFC,
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parameter pNMI_Vector = 16'hFFFA,
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parameter pNMI_Vector = 16'hFFFA,
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parameter pBRK = 3'b010
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parameter pBRK = 3'b010
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)(
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)(
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input Rst,
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input Rst,
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input Clk,
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input Clk,
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input nNMI,
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input nNMI,
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input nIRQ,
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input nIRQ,
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input [2:0] Mode,
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input [2:0] Mode,
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input IRQ_Msk,
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input IRQ_Msk,
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input IntSvc,
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input IntSvc,
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output reg Int,
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output reg Int,
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output reg [15:0] Vector,
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output reg [15:0] Vector,
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output reg NMI,
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output reg NMI,
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output reg IRQ,
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output reg IRQ,
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output reg Brk
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output reg Brk
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);
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);
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Local Declarations
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// Local Declarations
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//
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//
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wire RE_NMI;
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wire RE_NMI;
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wire CE_NMI;
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wire CE_NMI;
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reg nIRQ_IFD;
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reg nIRQ_IFD;
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// Perform falling edge detection on the external non-maskable interrupt input
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// Perform falling edge detection on the external non-maskable interrupt input
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fedet FE3 (
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fedet FE3 (
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.rst(Rst),
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.rst(Rst),
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.clk(Clk),
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.clk(Clk),
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.din(nNMI),
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.din(nNMI),
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.pls(RE_NMI)
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.pls(RE_NMI)
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);
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);
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// Capture and hold the rising edge pulse for NMI in NMI FF until serviced by
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// Capture and hold the rising edge pulse for NMI in NMI FF until serviced by
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// the processor.
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// the processor.
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assign CE_NMI = (Rst | IntSvc | RE_NMI);
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assign CE_NMI = (Rst | IntSvc | RE_NMI);
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always @(posedge Clk) NMI <= #1 ((CE_NMI) ? RE_NMI : 0);
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always @(posedge Clk) NMI <= #1 ((CE_NMI) ? RE_NMI : 0);
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// Synchronize external IRQ input to Clk
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// Synchronize external IRQ input to Clk
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always @(posedge Clk or posedge Rst)
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always @(posedge Clk or posedge Rst)
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begin
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begin
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if(Rst) begin
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if(Rst) begin
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nIRQ_IFD <= #1 1;
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nIRQ_IFD <= #1 1;
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IRQ <= #1 0;
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IRQ <= #1 0;
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end else begin
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end else begin
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nIRQ_IFD <= #1 nIRQ;
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nIRQ_IFD <= #1 nIRQ;
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IRQ <= #1 ~nIRQ_IFD;
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IRQ <= #1 ~nIRQ_IFD;
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end
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end
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end
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end
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//assign Brk = (Mode == pBRK);
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//assign Brk = (Mode == pBRK);
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//assign Int = (NMI | (~IRQ_Msk & IRQ));
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//assign Int = (NMI | (~IRQ_Msk & IRQ));
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//
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//
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//always @(*) Vector = ((Int) ? ((NMI) ? pNMI_Vector
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//always @(*) Vector = ((Int) ? ((NMI) ? pNMI_Vector
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// : pIRQ_Vector)
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// : pIRQ_Vector)
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// : ((Brk) ? pBRK_Vector
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// : ((Brk) ? pBRK_Vector
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// : pRST_Vector));
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// : pRST_Vector));
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always @(posedge Clk or posedge Rst)
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always @(posedge Clk or posedge Rst)
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begin
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begin
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if(Rst) begin
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if(Rst) begin
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Brk <= #1 0;
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Brk <= #1 0;
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Int <= #1 0;
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Int <= #1 0;
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Vector <= #1 pRST_Vector;
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Vector <= #1 pRST_Vector;
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end else begin
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end else begin
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Brk <= #1 (Mode == pBRK);
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Brk <= #1 (Mode == pBRK);
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Int <= #1 (NMI | (~IRQ_Msk & IRQ));
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Int <= #1 (NMI | (~IRQ_Msk & IRQ));
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Vector <= #1 ((Int) ? ((NMI) ? pNMI_Vector
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Vector <= #1 ((Int) ? ((NMI) ? pNMI_Vector
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: pIRQ_Vector)
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: pIRQ_Vector)
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: ((Brk) ? pBRK_Vector
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: ((Brk) ? pBRK_Vector
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: pRST_Vector));
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: pRST_Vector));
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end
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end
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end
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end
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endmodule
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endmodule
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