-- ------------------------------------------------------------------------
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-- ------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif Endro Nugroho
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-- Copyright (C) 2005 Arif Endro Nugroho
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- are met:
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--
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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-- 3. The name of Arif Endro Nugroho may not be used to endorse or promote
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-- products derived from this software without specific prior written
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-- permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- End Of License.
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-- End Of License.
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-- ------------------------------------------------------------------------
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-- ------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity modelsim_bench is
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entity modelsim_bench is
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end modelsim_bench;
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end modelsim_bench;
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architecture structural of modelsim_bench is
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architecture structural of modelsim_bench is
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component mini_aes
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component mini_aes
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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load_i : in std_logic;
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load_i : in std_logic;
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enc : in std_logic;
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enc : in std_logic;
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key_i : in std_logic_vector (007 downto 000);
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key_i : in std_logic_vector (007 downto 000);
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data_i : in std_logic_vector (007 downto 000);
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data_i : in std_logic_vector (007 downto 000);
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data_o : out std_logic_vector (007 downto 000);
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data_o : out std_logic_vector (007 downto 000);
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done_o : out std_logic
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done_o : out std_logic
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);
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);
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end component;
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end component;
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--
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--
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component input
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component input
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port (
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port (
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clock : out std_logic;
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clock : out std_logic;
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load : out std_logic;
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load : out std_logic;
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done : in std_logic;
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done : in std_logic;
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test_iteration : out integer;
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test_iteration : out integer;
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key_i_byte : out std_logic_vector (007 downto 000);
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key_i_byte : out std_logic_vector (007 downto 000);
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data_i_byte : out std_logic_vector (007 downto 000);
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data_i_byte : out std_logic_vector (007 downto 000);
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cipher_o_byte : out std_logic_vector (007 downto 000)
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cipher_o_byte : out std_logic_vector (007 downto 000)
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);
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);
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end component;
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end component;
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--
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--
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component output
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component output
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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load : in std_logic;
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load : in std_logic;
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enc : in std_logic;
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enc : in std_logic;
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done : in std_logic;
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done : in std_logic;
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test_iteration : in integer;
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test_iteration : in integer;
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verifier : in std_logic_vector (007 downto 000);
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verifier : in std_logic_vector (007 downto 000);
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data_o : in std_logic_vector (007 downto 000)
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data_o : in std_logic_vector (007 downto 000)
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);
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);
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end component;
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end component;
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signal load_enc : std_logic;
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signal load_enc : std_logic;
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signal load_dec : std_logic;
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signal load_dec : std_logic;
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signal clock_enc : std_logic;
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signal clock_enc : std_logic;
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signal clock_dec : std_logic;
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signal clock_dec : std_logic;
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signal done_dec : std_logic;
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signal done_dec : std_logic;
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signal done_enc : std_logic;
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signal done_enc : std_logic;
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signal test_iteration_enc : integer;
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signal test_iteration_enc : integer;
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signal test_iteration_dec : integer;
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signal test_iteration_dec : integer;
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signal cipher_o_enc : std_logic_vector (007 downto 000);
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signal cipher_o_enc : std_logic_vector (007 downto 000);
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signal cipher_o_dec : std_logic_vector (007 downto 000);
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signal cipher_o_dec : std_logic_vector (007 downto 000);
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signal data_i_enc : std_logic_vector (007 downto 000);
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signal data_i_enc : std_logic_vector (007 downto 000);
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signal data_i_dec : std_logic_vector (007 downto 000);
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signal data_i_dec : std_logic_vector (007 downto 000);
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signal data_o_enc : std_logic_vector (007 downto 000);
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signal data_o_enc : std_logic_vector (007 downto 000);
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signal data_o_dec : std_logic_vector (007 downto 000);
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signal data_o_dec : std_logic_vector (007 downto 000);
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signal key_i_enc : std_logic_vector (007 downto 000);
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signal key_i_enc : std_logic_vector (007 downto 000);
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signal key_i_dec : std_logic_vector (007 downto 000);
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signal key_i_dec : std_logic_vector (007 downto 000);
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begin
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begin
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my_aes_enc : mini_aes
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my_aes_enc : mini_aes
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port map (
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port map (
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clock => clock_enc,
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clock => clock_enc,
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clear => '0',
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clear => '0',
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load_i => load_enc,
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load_i => load_enc,
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enc => '0',
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enc => '0',
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key_i => key_i_enc,
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key_i => key_i_enc,
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data_i => data_i_enc,
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data_i => data_i_enc,
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data_o => data_o_enc,
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data_o => data_o_enc,
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done_o => done_enc
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done_o => done_enc
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);
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);
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--
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--
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my_aes_dec : mini_aes
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my_aes_dec : mini_aes
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port map (
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port map (
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clock => clock_dec,
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clock => clock_dec,
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clear => '0',
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clear => '0',
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load_i => load_dec,
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load_i => load_dec,
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enc => '1',
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enc => '1',
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key_i => key_i_dec,
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key_i => key_i_dec,
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data_i => cipher_o_dec,
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data_i => cipher_o_dec,
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data_o => data_o_dec,
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data_o => data_o_dec,
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done_o => done_dec
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done_o => done_dec
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);
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);
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--
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--
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my_input_enc : input
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my_input_enc : input
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port map (
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port map (
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clock => clock_enc,
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clock => clock_enc,
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load => load_enc,
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load => load_enc,
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done => done_enc,
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done => done_enc,
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test_iteration => test_iteration_enc,
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test_iteration => test_iteration_enc,
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key_i_byte => key_i_enc,
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key_i_byte => key_i_enc,
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data_i_byte => data_i_enc,
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data_i_byte => data_i_enc,
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cipher_o_byte => cipher_o_enc
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cipher_o_byte => cipher_o_enc
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);
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);
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my_input_dec : input
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my_input_dec : input
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port map (
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port map (
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clock => clock_dec,
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clock => clock_dec,
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load => load_dec,
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load => load_dec,
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done => done_dec,
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done => done_dec,
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test_iteration => test_iteration_dec,
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test_iteration => test_iteration_dec,
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data_i_byte => data_i_dec,
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data_i_byte => data_i_dec,
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cipher_o_byte => cipher_o_dec,
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cipher_o_byte => cipher_o_dec,
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key_i_byte => key_i_dec
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key_i_byte => key_i_dec
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);
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);
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--
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--
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my_output_enc : output
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my_output_enc : output
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port map (
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port map (
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clock => clock_enc,
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clock => clock_enc,
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clear => '0',
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clear => '0',
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load => load_enc,
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load => load_enc,
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enc => '0',
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enc => '0',
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done => done_enc,
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done => done_enc,
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test_iteration => test_iteration_enc,
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test_iteration => test_iteration_enc,
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verifier => cipher_o_enc,
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verifier => cipher_o_enc,
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data_o => data_o_enc
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data_o => data_o_enc
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);
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);
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--
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--
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my_output_dec : output
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my_output_dec : output
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port map (
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port map (
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clock => clock_dec,
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clock => clock_dec,
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clear => '0',
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clear => '0',
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load => load_dec,
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load => load_dec,
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enc => '1',
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enc => '1',
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done => done_dec,
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done => done_dec,
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test_iteration => test_iteration_dec,
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test_iteration => test_iteration_dec,
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verifier => data_i_dec,
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verifier => data_i_dec,
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data_o => data_o_dec
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data_o => data_o_dec
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);
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);
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end structural;
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end structural;
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