------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Two shift registers are used, when nr1 is full and nr2 is empty
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-- Two shift registers are used, when nr1 is full and nr2 is empty
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-- they are nr1 is mapped on nr2 in a reverse-zigzag order. Additionally
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-- they are nr1 is mapped on nr2 in a reverse-zigzag order. Additionally
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-- the "matrix" is transposed to compensate transponation of successional
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-- the "matrix" is transposed to compensate transponation of successional
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-- the idct-core.
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-- the idct-core.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity jpeg_dezigzag is
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entity jpeg_dezigzag is
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port(
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port(
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Clk : in std_logic;
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Clk : in std_logic;
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context_i: in std_logic_vector(3 downto 0);
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context_i: in std_logic_vector(3 downto 0);
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data_i : in std_logic_vector(11 downto 0);
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data_i : in std_logic_vector(11 downto 0);
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reset_i : in std_logic;
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reset_i : in std_logic;
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context_o: out std_logic_vector(3 downto 0);
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context_o: out std_logic_vector(3 downto 0);
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data_o : out std_logic_vector(11 downto 0);
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data_o : out std_logic_vector(11 downto 0);
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-- flow control
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-- flow control
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datavalid_i : in std_logic;
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datavalid_i : in std_logic;
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datavalid_o : out std_logic;
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datavalid_o : out std_logic;
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ready_i : in std_logic;
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ready_i : in std_logic;
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ready_o : out std_logic
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ready_o : out std_logic
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);
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);
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end entity jpeg_dezigzag;
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end entity jpeg_dezigzag;
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architecture IMP of jpeg_dezigzag is
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architecture IMP of jpeg_dezigzag is
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type sr is array (0 to 63) of std_logic_vector(11 downto 0);
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type sr is array (0 to 63) of std_logic_vector(11 downto 0);
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signal sr_in, sr_out : sr := (others=>X"000");
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signal sr_in, sr_out : sr := (others=>X"000");
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signal ce_in, ce_out : std_logic :='0';
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signal ce_in, ce_out : std_logic :='0';
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signal counter_in : std_logic_vector(5 downto 0) :=(others=>'0');
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signal counter_in : std_logic_vector(5 downto 0) :=(others=>'0');
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signal counter_out : std_logic_vector(5 downto 0) :=(others=>'0');
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signal counter_out : std_logic_vector(5 downto 0) :=(others=>'0');
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signal do_copy, do_copy_D : std_logic :='0';
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signal do_copy, do_copy_D : std_logic :='0';
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signal stop_in, stop_in_D : std_logic :='0';
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signal stop_in, stop_in_D : std_logic :='0';
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signal stop_out, stop_out_D : std_logic :='1';
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signal stop_out, stop_out_D : std_logic :='1';
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signal stop_eoi_out, stop_eoi_out_D : std_logic := '1';
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signal stop_eoi_out, stop_eoi_out_D : std_logic := '1';
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signal context, context_D : std_logic_vector(3 downto 0) :=(others=>'0');
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signal context, context_D : std_logic_vector(3 downto 0) :=(others=>'0');
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signal eoi, eoi_D : std_logic :='0';
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signal eoi, eoi_D : std_logic :='0';
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signal eoi_hold, eoi_hold_D : std_logic :='0';
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signal eoi_hold, eoi_hold_D : std_logic :='0';
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signal ready, ready_D : std_logic :='1';
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signal ready, ready_D : std_logic :='1';
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begin
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begin
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ready_o <= ready;
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ready_o <= ready;
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datavalid_o <= (ce_out and not do_copy);
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datavalid_o <= (ce_out and not do_copy);
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data_o <= sr_out(0);
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data_o <= sr_out(0);
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context_o <= context;
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context_o <= context;
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process(ready, counter_in, do_copy)
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process(ready, counter_in, do_copy)
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begin
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begin
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ready_D <= ready;
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ready_D <= ready;
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if (counter_in=63) then
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if (counter_in=63) then
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ready_D <='0';
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ready_D <='0';
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elsif(do_copy='1') then
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elsif(do_copy='1') then
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ready_D<='1';
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ready_D<='1';
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end if;
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end if;
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end process;
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end process;
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process(Clk)
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process(Clk)
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begin
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begin
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if rising_edge(Clk) then
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if rising_edge(Clk) then
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if(reset_i='1') then
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if(reset_i='1') then
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ready <='1';
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ready <='1';
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elsif ce_in='1' then
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elsif ce_in='1' then
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ready <= ready_D;
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ready <= ready_D;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(stop_eoi_out, counter_in, do_copy)
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process(stop_eoi_out, counter_in, do_copy)
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begin
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begin
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stop_eoi_out_D <= stop_eoi_out;
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stop_eoi_out_D <= stop_eoi_out;
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if (counter_in=1) then
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if (counter_in=1) then
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stop_eoi_out_D <='1';
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stop_eoi_out_D <='1';
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elsif(do_copy='1') then
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elsif(do_copy='1') then
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stop_eoi_out_D<='0';
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stop_eoi_out_D<='0';
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end if;
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end if;
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end process;
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end process;
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process(Clk)
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process(Clk)
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begin
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begin
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if rising_edge(Clk) then
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if rising_edge(Clk) then
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if(reset_i='1') then
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if(reset_i='1') then
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stop_eoi_out <='1';
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stop_eoi_out <='1';
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elsif ce_in='1' then
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elsif ce_in='1' then
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stop_eoi_out <= stop_eoi_out_D;
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stop_eoi_out <= stop_eoi_out_D;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- handle the context
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-- handle the context
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process(eoi, eoi_hold, context_i, counter_out, do_copy, stop_eoi_out)
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process(eoi, eoi_hold, context_i, counter_out, do_copy, stop_eoi_out)
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begin
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begin
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eoi_D <= eoi;
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eoi_D <= eoi;
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eoi_hold_D <= eoi_hold;
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eoi_hold_D <= eoi_hold;
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if (context_i(3)='1' and do_copy='0' and stop_eoi_out='1') then
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if (context_i(3)='1' and do_copy='0' and stop_eoi_out='1') then
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eoi_hold_D <= '1';
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eoi_hold_D <= '1';
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elsif(context_i(3)='1' and (do_copy='1' and stop_eoi_out='1')) then
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elsif(context_i(3)='1' and (do_copy='1' and stop_eoi_out='1')) then
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eoi_D <= '1';
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eoi_D <= '1';
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eoi_hold_D <= '0';
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eoi_hold_D <= '0';
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elsif(context_i(3)='1' and stop_eoi_out='0') then
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elsif(context_i(3)='1' and stop_eoi_out='0') then
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eoi_D <= '1';
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eoi_D <= '1';
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eoi_hold_D <= '0';
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eoi_hold_D <= '0';
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elsif(eoi_hold='1' and do_copy='1') then
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elsif(eoi_hold='1' and do_copy='1') then
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eoi_D <= '1';
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eoi_D <= '1';
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eoi_hold_D <= '0';
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eoi_hold_D <= '0';
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end if;
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end if;
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if (counter_out=63 and eoi='1') then
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if (counter_out=63 and eoi='1') then
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eoi_D <= '0';
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eoi_D <= '0';
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eoi_hold_D <= '0';
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eoi_hold_D <= '0';
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end if;
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end if;
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end process;
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end process;
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process(Clk)
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process(Clk)
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begin
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begin
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if rising_edge(Clk) then
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if rising_edge(Clk) then
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eoi <= eoi_D;
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eoi <= eoi_D;
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eoi_hold <= eoi_hold_D;
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eoi_hold <= eoi_hold_D;
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context <= '0' & '0' & context(1 downto 0);
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context <= '0' & '0' & context(1 downto 0);
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if counter_in=60 then
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if counter_in=60 then
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context_D <= context_i;
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context_D <= context_i;
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end if;
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end if;
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if do_copy='1' then
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if do_copy='1' then
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context <= context_D;
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context <= context_D;
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end if;
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end if;
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if reset_i='1' then
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if reset_i='1' then
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context <= (others=>'0');
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context <= (others=>'0');
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eoi <='0';
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eoi <='0';
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eoi_hold <='0';
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eoi_hold <='0';
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elsif counter_out=63 and ce_out='1' then
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elsif counter_out=63 and ce_out='1' then
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context(3) <= eoi;
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context(3) <= eoi;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- SHIFT_IN
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-- SHIFT_IN
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process(Clk)
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process(Clk)
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begin
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begin
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if rising_edge(Clk) then
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if rising_edge(Clk) then
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if reset_i='1' then
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if reset_i='1' then
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sr_in <= (others=>X"000");
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sr_in <= (others=>X"000");
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counter_in <= (others=>'0');
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counter_in <= (others=>'0');
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elsif ce_in='1' and do_copy='0' then
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elsif ce_in='1' and do_copy='0' then
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sr_in <= sr_in(1 to 63) & data_i;
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sr_in <= sr_in(1 to 63) & data_i;
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counter_in <= counter_in+1;
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counter_in <= counter_in+1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(datavalid_i, stop_in, do_copy)
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process(datavalid_i, stop_in, do_copy)
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begin
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begin
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if datavalid_i='1' and stop_in='0' then
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if datavalid_i='1' and stop_in='0' then
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ce_in <='1';
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ce_in <='1';
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elsif(do_copy='1') then
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elsif(do_copy='1') then
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ce_in <= '1';
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ce_in <= '1';
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else
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else
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ce_in <='0';
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ce_in <='0';
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end if;
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end if;
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end process;
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end process;
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process(counter_in, do_copy, ce_in)
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process(counter_in, do_copy, ce_in)
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begin
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begin
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stop_in_D <= stop_in;
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stop_in_D <= stop_in;
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if(do_copy='1') then
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if(do_copy='1') then
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stop_in_D <= '0';
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stop_in_D <= '0';
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elsif counter_in="111111" and ce_in='1' then
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elsif counter_in="111111" and ce_in='1' then
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stop_in_D <= '1';
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stop_in_D <= '1';
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end if;
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end if;
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end process;
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end process;
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process(Clk)
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process(Clk)
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begin
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begin
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if rising_edge(Clk) then
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if rising_edge(Clk) then
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if reset_i='1' then
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if reset_i='1' then
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stop_in <= '0';
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stop_in <= '0';
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else
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else
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stop_in <= stop_in_D;
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stop_in <= stop_in_D;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- DO_COPY
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-- DO_COPY
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process(stop_in, stop_out)
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process(stop_in, stop_out)
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begin
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begin
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if stop_in ='1' and stop_out='1' then
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if stop_in ='1' and stop_out='1' then
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do_copy_D <= '1';
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do_copy_D <= '1';
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else
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else
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do_copy_D <= '0';
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do_copy_D <= '0';
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end if;
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end if;
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end process;
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end process;
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process(Clk)
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process(Clk)
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begin
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begin
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if rising_edge(Clk) then
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if rising_edge(Clk) then
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if(reset_i='1') then
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if(reset_i='1') then
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do_copy <='0';
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do_copy <='0';
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else
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else
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do_copy <= do_copy_D;
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do_copy <= do_copy_D;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- SHIFT_OUT
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-- SHIFT_OUT
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process(Clk)
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process(Clk)
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begin
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begin
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if rising_edge(Clk) then
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if rising_edge(Clk) then
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if reset_i='1' then
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if reset_i='1' then
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sr_out <= (others=>X"000");
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sr_out <= (others=>X"000");
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counter_out <= (others=>'0');
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counter_out <= (others=>'0');
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elsif do_copy='1' then
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elsif do_copy='1' then
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-- -- do the Zig-Zag Mapping
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-- -- do the Zig-Zag Mapping
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-- sr_out(00) <= sr_in(00);
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-- sr_out(00) <= sr_in(00);
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-- sr_out(01) <= sr_in(01);
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-- sr_out(01) <= sr_in(01);
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-- sr_out(02) <= sr_in(05);
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-- sr_out(02) <= sr_in(05);
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-- sr_out(03) <= sr_in(06);
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-- sr_out(03) <= sr_in(06);
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-- sr_out(04) <= sr_in(14);
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-- sr_out(04) <= sr_in(14);
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-- sr_out(05) <= sr_in(17);
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-- sr_out(05) <= sr_in(15);
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-- sr_out(06) <= sr_in(27);
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-- sr_out(06) <= sr_in(27);
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-- sr_out(07) <= sr_in(28);
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-- sr_out(07) <= sr_in(28);
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-- sr_out(08) <= sr_in(02);
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-- sr_out(08) <= sr_in(02);
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-- sr_out(09) <= sr_in(04);
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-- sr_out(09) <= sr_in(04);
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-- sr_out(10) <= sr_in(07);
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-- sr_out(10) <= sr_in(07);
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-- sr_out(11) <= sr_in(13);
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-- sr_out(11) <= sr_in(13);
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-- sr_out(12) <= sr_in(16);
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-- sr_out(12) <= sr_in(16);
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-- sr_out(13) <= sr_in(26);
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-- sr_out(13) <= sr_in(26);
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-- sr_out(14) <= sr_in(29);
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-- sr_out(14) <= sr_in(29);
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-- sr_out(15) <= sr_in(42);
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-- sr_out(15) <= sr_in(42);
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-- sr_out(16) <= sr_in(03);
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-- sr_out(16) <= sr_in(03);
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-- sr_out(17) <= sr_in(08);
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-- sr_out(17) <= sr_in(08);
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-- sr_out(18) <= sr_in(12);
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-- sr_out(18) <= sr_in(12);
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-- sr_out(19) <= sr_in(17);
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-- sr_out(19) <= sr_in(17);
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-- sr_out(20) <= sr_in(25);
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-- sr_out(20) <= sr_in(25);
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-- sr_out(21) <= sr_in(30);
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-- sr_out(21) <= sr_in(30);
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-- sr_out(22) <= sr_in(41);
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-- sr_out(22) <= sr_in(41);
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-- sr_out(23) <= sr_in(43);
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-- sr_out(23) <= sr_in(43);
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-- sr_out(24) <= sr_in(09);
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-- sr_out(24) <= sr_in(09);
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-- sr_out(25) <= sr_in(11);
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-- sr_out(25) <= sr_in(11);
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-- sr_out(26) <= sr_in(18);
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-- sr_out(26) <= sr_in(18);
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-- sr_out(27) <= sr_in(24);
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-- sr_out(27) <= sr_in(24);
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-- sr_out(28) <= sr_in(31);
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-- sr_out(28) <= sr_in(31);
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-- sr_out(29) <= sr_in(40);
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-- sr_out(29) <= sr_in(40);
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-- sr_out(30) <= sr_in(44);
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-- sr_out(30) <= sr_in(44);
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-- sr_out(31) <= sr_in(53);
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-- sr_out(31) <= sr_in(53);
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-- sr_out(32) <= sr_in(10);
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-- sr_out(32) <= sr_in(10);
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-- sr_out(33) <= sr_in(19);
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-- sr_out(33) <= sr_in(19);
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-- sr_out(34) <= sr_in(23);
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-- sr_out(34) <= sr_in(23);
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-- sr_out(35) <= sr_in(32);
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-- sr_out(35) <= sr_in(32);
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-- sr_out(36) <= sr_in(39);
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-- sr_out(36) <= sr_in(39);
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-- sr_out(37) <= sr_in(45);
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-- sr_out(37) <= sr_in(45);
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-- sr_out(38) <= sr_in(52);
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-- sr_out(38) <= sr_in(52);
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-- sr_out(39) <= sr_in(54);
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-- sr_out(39) <= sr_in(54);
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-- sr_out(40) <= sr_in(20);
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-- sr_out(40) <= sr_in(20);
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-- sr_out(41) <= sr_in(22);
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-- sr_out(41) <= sr_in(22);
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-- sr_out(42) <= sr_in(33);
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-- sr_out(42) <= sr_in(33);
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-- sr_out(43) <= sr_in(38);
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-- sr_out(43) <= sr_in(38);
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-- sr_out(44) <= sr_in(46);
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-- sr_out(44) <= sr_in(46);
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-- sr_out(45) <= sr_in(51);
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-- sr_out(45) <= sr_in(51);
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-- sr_out(46) <= sr_in(55);
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-- sr_out(46) <= sr_in(55);
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-- sr_out(47) <= sr_in(60);
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-- sr_out(47) <= sr_in(60);
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-- sr_out(48) <= sr_in(21);
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-- sr_out(48) <= sr_in(21);
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-- sr_out(49) <= sr_in(34);
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-- sr_out(49) <= sr_in(34);
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-- sr_out(50) <= sr_in(37);
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-- sr_out(50) <= sr_in(37);
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-- sr_out(51) <= sr_in(47);
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-- sr_out(51) <= sr_in(47);
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-- sr_out(52) <= sr_in(50);
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-- sr_out(52) <= sr_in(50);
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-- sr_out(53) <= sr_in(56);
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-- sr_out(53) <= sr_in(56);
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-- sr_out(54) <= sr_in(59);
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-- sr_out(54) <= sr_in(59);
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-- sr_out(55) <= sr_in(61);
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-- sr_out(55) <= sr_in(61);
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-- sr_out(56) <= sr_in(35);
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-- sr_out(56) <= sr_in(35);
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-- sr_out(57) <= sr_in(36);
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-- sr_out(57) <= sr_in(36);
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-- sr_out(58) <= sr_in(48);
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-- sr_out(58) <= sr_in(48);
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-- sr_out(59) <= sr_in(49);
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-- sr_out(59) <= sr_in(49);
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-- sr_out(60) <= sr_in(57);
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-- sr_out(60) <= sr_in(57);
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-- sr_out(61) <= sr_in(58);
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-- sr_out(61) <= sr_in(58);
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-- sr_out(62) <= sr_in(62);
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-- sr_out(62) <= sr_in(62);
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-- sr_out(63) <= sr_in(63);
|
-- sr_out(63) <= sr_in(63);
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-- additionally transpose the inputx matrix
|
-- additionally transpose the inputx matrix
|
-- to compensate the column-wise output of the successional idct-entity
|
-- to compensate the column-wise output of the successional idct-entity
|
sr_out(00) <= sr_in(00);
|
sr_out(00) <= sr_in(00);
|
sr_out(08) <= sr_in(01);
|
sr_out(08) <= sr_in(01);
|
sr_out(16) <= sr_in(05);
|
sr_out(16) <= sr_in(05);
|
sr_out(24) <= sr_in(06);
|
sr_out(24) <= sr_in(06);
|
sr_out(32) <= sr_in(14);
|
sr_out(32) <= sr_in(14);
|
sr_out(40) <= sr_in(17);
|
sr_out(40) <= sr_in(15);
|
sr_out(48) <= sr_in(27);
|
sr_out(48) <= sr_in(27);
|
sr_out(56) <= sr_in(28);
|
sr_out(56) <= sr_in(28);
|
sr_out(01) <= sr_in(02);
|
sr_out(01) <= sr_in(02);
|
sr_out(09) <= sr_in(04);
|
sr_out(09) <= sr_in(04);
|
sr_out(17) <= sr_in(07);
|
sr_out(17) <= sr_in(07);
|
sr_out(25) <= sr_in(13);
|
sr_out(25) <= sr_in(13);
|
sr_out(33) <= sr_in(16);
|
sr_out(33) <= sr_in(16);
|
sr_out(41) <= sr_in(26);
|
sr_out(41) <= sr_in(26);
|
sr_out(49) <= sr_in(29);
|
sr_out(49) <= sr_in(29);
|
sr_out(57) <= sr_in(42);
|
sr_out(57) <= sr_in(42);
|
sr_out(02) <= sr_in(03);
|
sr_out(02) <= sr_in(03);
|
sr_out(10) <= sr_in(08);
|
sr_out(10) <= sr_in(08);
|
sr_out(18) <= sr_in(12);
|
sr_out(18) <= sr_in(12);
|
sr_out(26) <= sr_in(17);
|
sr_out(26) <= sr_in(17);
|
sr_out(34) <= sr_in(25);
|
sr_out(34) <= sr_in(25);
|
sr_out(42) <= sr_in(30);
|
sr_out(42) <= sr_in(30);
|
sr_out(50) <= sr_in(41);
|
sr_out(50) <= sr_in(41);
|
sr_out(58) <= sr_in(43);
|
sr_out(58) <= sr_in(43);
|
sr_out(03) <= sr_in(09);
|
sr_out(03) <= sr_in(09);
|
sr_out(11) <= sr_in(11);
|
sr_out(11) <= sr_in(11);
|
sr_out(19) <= sr_in(18);
|
sr_out(19) <= sr_in(18);
|
sr_out(27) <= sr_in(24);
|
sr_out(27) <= sr_in(24);
|
sr_out(35) <= sr_in(31);
|
sr_out(35) <= sr_in(31);
|
sr_out(43) <= sr_in(40);
|
sr_out(43) <= sr_in(40);
|
sr_out(51) <= sr_in(44);
|
sr_out(51) <= sr_in(44);
|
sr_out(59) <= sr_in(53);
|
sr_out(59) <= sr_in(53);
|
sr_out(04) <= sr_in(10);
|
sr_out(04) <= sr_in(10);
|
sr_out(12) <= sr_in(19);
|
sr_out(12) <= sr_in(19);
|
sr_out(20) <= sr_in(23);
|
sr_out(20) <= sr_in(23);
|
sr_out(28) <= sr_in(32);
|
sr_out(28) <= sr_in(32);
|
sr_out(36) <= sr_in(39);
|
sr_out(36) <= sr_in(39);
|
sr_out(44) <= sr_in(45);
|
sr_out(44) <= sr_in(45);
|
sr_out(51) <= sr_in(52);
|
sr_out(51) <= sr_in(52);
|
sr_out(60) <= sr_in(54);
|
sr_out(60) <= sr_in(54);
|
sr_out(05) <= sr_in(20);
|
sr_out(05) <= sr_in(20);
|
sr_out(13) <= sr_in(22);
|
sr_out(13) <= sr_in(22);
|
sr_out(21) <= sr_in(33);
|
sr_out(21) <= sr_in(33);
|
sr_out(29) <= sr_in(38);
|
sr_out(29) <= sr_in(38);
|
sr_out(37) <= sr_in(46);
|
sr_out(37) <= sr_in(46);
|
sr_out(45) <= sr_in(51);
|
sr_out(45) <= sr_in(51);
|
sr_out(53) <= sr_in(55);
|
sr_out(53) <= sr_in(55);
|
sr_out(61) <= sr_in(60);
|
sr_out(61) <= sr_in(60);
|
sr_out(06) <= sr_in(21);
|
sr_out(06) <= sr_in(21);
|
sr_out(14) <= sr_in(34);
|
sr_out(14) <= sr_in(34);
|
sr_out(22) <= sr_in(37);
|
sr_out(22) <= sr_in(37);
|
sr_out(30) <= sr_in(47);
|
sr_out(30) <= sr_in(47);
|
sr_out(38) <= sr_in(50);
|
sr_out(38) <= sr_in(50);
|
sr_out(46) <= sr_in(56);
|
sr_out(46) <= sr_in(56);
|
sr_out(54) <= sr_in(59);
|
sr_out(54) <= sr_in(59);
|
sr_out(62) <= sr_in(61);
|
sr_out(62) <= sr_in(61);
|
sr_out(07) <= sr_in(35);
|
sr_out(07) <= sr_in(35);
|
sr_out(15) <= sr_in(36);
|
sr_out(15) <= sr_in(36);
|
sr_out(23) <= sr_in(48);
|
sr_out(23) <= sr_in(48);
|
sr_out(31) <= sr_in(49);
|
sr_out(31) <= sr_in(49);
|
sr_out(39) <= sr_in(57);
|
sr_out(39) <= sr_in(57);
|
sr_out(47) <= sr_in(58);
|
sr_out(47) <= sr_in(58);
|
sr_out(55) <= sr_in(62);
|
sr_out(55) <= sr_in(62);
|
sr_out(63) <= sr_in(63);
|
sr_out(63) <= sr_in(63);
|
elsif ce_out='1' and do_copy='0' then
|
elsif ce_out='1' and do_copy='0' then
|
sr_out <= sr_out(1 to 63) & X"000";
|
sr_out <= sr_out(1 to 63) & X"000";
|
counter_out <= counter_out+1;
|
counter_out <= counter_out+1;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
process(ready_i, stop_out, do_copy)
|
process(ready_i, stop_out, do_copy)
|
begin
|
begin
|
if ready_i='1' and stop_out='0' then
|
if ready_i='1' and stop_out='0' then
|
ce_out <='1';
|
ce_out <='1';
|
elsif(do_copy='1') then
|
elsif(do_copy='1') then
|
ce_out <= '1';
|
ce_out <= '1';
|
else
|
else
|
ce_out <='0';
|
ce_out <='0';
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
process(counter_out, do_copy, ce_out)
|
process(counter_out, do_copy, ce_out)
|
begin
|
begin
|
stop_out_D <= stop_out;
|
stop_out_D <= stop_out;
|
if(do_copy='1') then
|
if(do_copy='1') then
|
stop_out_D <= '0';
|
stop_out_D <= '0';
|
elsif counter_out="111111" and ce_out='1' then
|
elsif counter_out="111111" and ce_out='1' then
|
stop_out_D <= '1';
|
stop_out_D <= '1';
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
process(Clk)
|
process(Clk)
|
begin
|
begin
|
if rising_edge(Clk) then
|
if rising_edge(Clk) then
|
if reset_i='1' then
|
if reset_i='1' then
|
stop_out <= '1';
|
stop_out <= '1';
|
else
|
else
|
stop_out <= stop_out_D;
|
stop_out <= stop_out_D;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
end IMP;
|
end IMP;
|
|
|
