ac97/ 0000755 0001750 0001750 00000000000 11411201677 012005 5 ustar lekernel lekernel ac97/rtl/ 0000755 0001750 0001750 00000000000 11411201677 012606 5 ustar lekernel lekernel ac97/rtl/ac97_framer.v 0000644 0001750 0001750 00000011346 11411201677 015101 0 ustar lekernel lekernel /*
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ac97/ 0000755 0001750 0001750 00000000000 11411201677 012005 5 ustar lekernel lekernel ac97/rtl/ 0000755 0001750 0001750 00000000000 11411201677 012606 5 ustar lekernel lekernel ac97/rtl/ac97_framer.v 0000644 0001750 0001750 00000011346 11411201677 015101 0 ustar lekernel lekernel /*
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* Milkymist VJ SoC
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* Milkymist VJ SoC
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* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
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* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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* the Free Software Foundation, version 3 of the License.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see .
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* along with this program. If not, see .
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*/
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*/
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module ac97_framer(
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module ac97_framer(
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input sys_clk,
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input sys_clk,
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input sys_rst,
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input sys_rst,
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/* to transceiver */
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/* to transceiver */
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input down_ready,
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input down_ready,
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output down_stb,
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output down_stb,
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output reg down_sync,
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output reg down_sync,
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output reg down_data,
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output reg down_data,
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/* frame data */
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/* frame data */
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input en,
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input en,
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output reg next_frame,
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output reg next_frame,
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input addr_valid,
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input addr_valid,
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input [19:0] addr,
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input [19:0] addr,
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input data_valid,
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input data_valid,
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input [19:0] data,
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input [19:0] data,
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input pcmleft_valid,
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input pcmleft_valid,
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input [19:0] pcmleft,
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input [19:0] pcmleft,
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input pcmright_valid,
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input pcmright_valid,
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input [19:0] pcmright
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input [19:0] pcmright
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);
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);
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reg [7:0] bitcounter;
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reg [7:0] bitcounter;
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reg slot_bit;
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reg slot_bit;
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always @(*) begin
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always @(*) begin
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case(bitcounter)
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case(bitcounter)
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8'd16: slot_bit = addr[19];
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8'd16: slot_bit = addr[19];
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8'd17: slot_bit = addr[18];
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8'd17: slot_bit = addr[18];
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8'd18: slot_bit = addr[17];
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8'd18: slot_bit = addr[17];
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8'd19: slot_bit = addr[16];
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8'd19: slot_bit = addr[16];
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8'd20: slot_bit = addr[15];
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8'd20: slot_bit = addr[15];
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8'd21: slot_bit = addr[14];
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8'd21: slot_bit = addr[14];
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8'd22: slot_bit = addr[13];
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8'd22: slot_bit = addr[13];
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8'd23: slot_bit = addr[12];
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8'd23: slot_bit = addr[12];
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8'd24: slot_bit = addr[11];
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8'd24: slot_bit = addr[11];
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8'd25: slot_bit = addr[10];
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8'd25: slot_bit = addr[10];
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8'd26: slot_bit = addr[9];
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8'd26: slot_bit = addr[9];
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8'd27: slot_bit = addr[8];
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8'd27: slot_bit = addr[8];
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8'd28: slot_bit = addr[7];
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8'd28: slot_bit = addr[7];
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8'd29: slot_bit = addr[6];
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8'd29: slot_bit = addr[6];
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8'd30: slot_bit = addr[5];
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8'd30: slot_bit = addr[5];
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8'd31: slot_bit = addr[4];
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8'd31: slot_bit = addr[4];
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8'd32: slot_bit = addr[3];
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8'd32: slot_bit = addr[3];
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8'd33: slot_bit = addr[2];
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8'd33: slot_bit = addr[2];
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8'd34: slot_bit = addr[1];
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8'd34: slot_bit = addr[1];
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8'd35: slot_bit = addr[0];
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8'd35: slot_bit = addr[0];
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8'd36: slot_bit = data[19];
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8'd36: slot_bit = data[19];
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8'd37: slot_bit = data[18];
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8'd37: slot_bit = data[18];
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8'd38: slot_bit = data[17];
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8'd38: slot_bit = data[17];
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8'd39: slot_bit = data[16];
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8'd39: slot_bit = data[16];
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8'd40: slot_bit = data[15];
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8'd40: slot_bit = data[15];
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8'd41: slot_bit = data[14];
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8'd41: slot_bit = data[14];
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8'd42: slot_bit = data[13];
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8'd42: slot_bit = data[13];
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8'd43: slot_bit = data[12];
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8'd43: slot_bit = data[12];
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8'd44: slot_bit = data[11];
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8'd44: slot_bit = data[11];
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8'd45: slot_bit = data[10];
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8'd45: slot_bit = data[10];
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8'd46: slot_bit = data[9];
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8'd46: slot_bit = data[9];
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8'd47: slot_bit = data[8];
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8'd47: slot_bit = data[8];
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8'd48: slot_bit = data[7];
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8'd48: slot_bit = data[7];
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8'd49: slot_bit = data[6];
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8'd49: slot_bit = data[6];
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8'd50: slot_bit = data[5];
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8'd50: slot_bit = data[5];
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8'd51: slot_bit = data[4];
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8'd51: slot_bit = data[4];
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8'd52: slot_bit = data[3];
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8'd52: slot_bit = data[3];
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8'd53: slot_bit = data[2];
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8'd53: slot_bit = data[2];
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8'd54: slot_bit = data[1];
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8'd54: slot_bit = data[1];
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8'd55: slot_bit = data[0];
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8'd55: slot_bit = data[0];
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8'd56: slot_bit = pcmleft[19];
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8'd56: slot_bit = pcmleft[19];
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8'd57: slot_bit = pcmleft[18];
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8'd57: slot_bit = pcmleft[18];
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8'd58: slot_bit = pcmleft[17];
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8'd58: slot_bit = pcmleft[17];
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8'd59: slot_bit = pcmleft[16];
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8'd59: slot_bit = pcmleft[16];
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8'd60: slot_bit = pcmleft[15];
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8'd60: slot_bit = pcmleft[15];
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8'd61: slot_bit = pcmleft[14];
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8'd61: slot_bit = pcmleft[14];
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8'd62: slot_bit = pcmleft[13];
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8'd62: slot_bit = pcmleft[13];
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8'd63: slot_bit = pcmleft[12];
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8'd63: slot_bit = pcmleft[12];
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8'd64: slot_bit = pcmleft[11];
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8'd64: slot_bit = pcmleft[11];
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8'd65: slot_bit = pcmleft[10];
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8'd65: slot_bit = pcmleft[10];
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8'd66: slot_bit = pcmleft[9];
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8'd66: slot_bit = pcmleft[9];
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8'd67: slot_bit = pcmleft[8];
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8'd67: slot_bit = pcmleft[8];
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8'd68: slot_bit = pcmleft[7];
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8'd68: slot_bit = pcmleft[7];
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8'd69: slot_bit = pcmleft[6];
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8'd69: slot_bit = pcmleft[6];
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8'd70: slot_bit = pcmleft[5];
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8'd70: slot_bit = pcmleft[5];
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8'd71: slot_bit = pcmleft[4];
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8'd71: slot_bit = pcmleft[4];
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8'd72: slot_bit = pcmleft[3];
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8'd72: slot_bit = pcmleft[3];
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8'd73: slot_bit = pcmleft[2];
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8'd73: slot_bit = pcmleft[2];
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8'd74: slot_bit = pcmleft[1];
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8'd74: slot_bit = pcmleft[1];
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8'd75: slot_bit = pcmleft[0];
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8'd75: slot_bit = pcmleft[0];
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8'd76: slot_bit = pcmright[19];
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8'd76: slot_bit = pcmright[19];
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8'd77: slot_bit = pcmright[18];
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8'd77: slot_bit = pcmright[18];
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8'd78: slot_bit = pcmright[17];
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8'd78: slot_bit = pcmright[17];
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8'd79: slot_bit = pcmright[16];
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8'd79: slot_bit = pcmright[16];
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8'd80: slot_bit = pcmright[15];
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8'd80: slot_bit = pcmright[15];
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8'd81: slot_bit = pcmright[14];
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8'd81: slot_bit = pcmright[14];
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8'd82: slot_bit = pcmright[13];
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8'd82: slot_bit = pcmright[13];
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8'd83: slot_bit = pcmright[12];
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8'd83: slot_bit = pcmright[12];
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8'd84: slot_bit = pcmright[11];
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8'd84: slot_bit = pcmright[11];
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8'd85: slot_bit = pcmright[10];
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8'd85: slot_bit = pcmright[10];
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8'd86: slot_bit = pcmright[9];
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8'd86: slot_bit = pcmright[9];
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8'd87: slot_bit = pcmright[8];
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8'd87: slot_bit = pcmright[8];
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8'd88: slot_bit = pcmright[7];
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8'd88: slot_bit = pcmright[7];
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8'd89: slot_bit = pcmright[6];
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8'd89: slot_bit = pcmright[6];
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8'd90: slot_bit = pcmright[5];
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8'd90: slot_bit = pcmright[5];
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8'd91: slot_bit = pcmright[4];
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8'd91: slot_bit = pcmright[4];
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8'd92: slot_bit = pcmright[3];
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8'd92: slot_bit = pcmright[3];
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8'd93: slot_bit = pcmright[2];
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8'd93: slot_bit = pcmright[2];
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8'd94: slot_bit = pcmright[1];
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8'd94: slot_bit = pcmright[1];
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8'd95: slot_bit = pcmright[0];
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8'd95: slot_bit = pcmright[0];
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default: slot_bit = 1'bx;
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default: slot_bit = 1'bx;
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endcase
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endcase
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end
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end
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reg in_slot;
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reg in_slot;
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always @(posedge sys_clk) begin
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always @(posedge sys_clk) begin
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if(sys_rst) begin
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if(sys_rst) begin
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bitcounter <= 8'd0;
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bitcounter <= 8'd0;
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down_sync <= 1'b0;
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down_sync <= 1'b0;
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down_data <= 1'b0;
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down_data <= 1'b0;
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in_slot <= 1'b0;
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in_slot <= 1'b0;
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end else begin
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end else begin
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if(en)
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if(en)
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next_frame <= 1'b0;
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next_frame <= 1'b0;
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if(down_ready & en) begin
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if(down_ready & en) begin
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if(bitcounter == 8'd255)
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if(bitcounter == 8'd255)
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next_frame <= 1'b1;
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next_frame <= 1'b1;
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if(bitcounter == 8'd255)
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if(bitcounter == 8'd255)
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down_sync <= 1'b1;
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down_sync <= 1'b1;
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if(bitcounter == 8'd15)
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if(bitcounter == 8'd15)
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down_sync <= 1'b0;
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down_sync <= 1'b0;
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if(bitcounter == 8'd15)
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if(bitcounter == 8'd15)
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in_slot <= 1'b1;
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in_slot <= 1'b1;
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if(bitcounter == 8'd95)
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if(bitcounter == 8'd95)
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in_slot <= 1'b0;
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in_slot <= 1'b0;
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case({down_sync, in_slot})
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case({down_sync, in_slot})
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2'b10: begin
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2'b10: begin
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/* Tag */
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/* Tag */
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case(bitcounter[3:0])
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case(bitcounter[3:0])
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4'h0: down_data <= 1'b1; // Frame valid
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4'h0: down_data <= 1'b1; // Frame valid
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4'h1: down_data <= addr_valid; // Slot 1 valid
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4'h1: down_data <= addr_valid; // Slot 1 valid
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4'h2: down_data <= data_valid; // Slot 2 valid
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4'h2: down_data <= data_valid; // Slot 2 valid
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4'h3: down_data <= pcmleft_valid; // Slot 3 valid
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4'h3: down_data <= pcmleft_valid; // Slot 3 valid
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4'h4: down_data <= pcmright_valid; // Slot 4 valid
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4'h4: down_data <= pcmright_valid; // Slot 4 valid
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default: down_data <= 1'b0;
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default: down_data <= 1'b0;
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endcase
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endcase
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//$display("PCMRIGHT_V: %b", pcmright_valid);
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//$display("PCMRIGHT_V: %b", pcmright_valid);
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end
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end
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2'b01:
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2'b01:
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/* Active slot */
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/* Active slot */
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down_data <= slot_bit;
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down_data <= slot_bit;
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default: down_data <= 1'b0;
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default: down_data <= 1'b0;
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endcase
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endcase
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bitcounter <= bitcounter + 8'd1;
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bitcounter <= bitcounter + 8'd1;
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end
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end
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end
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end
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end
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end
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assign down_stb = en;
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assign down_stb = en;
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endmodule
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endmodule
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