# -*- coding: utf-8 -*-
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# -*- coding: utf-8 -*-
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"""
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"""
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core.py
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core.py
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=======
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=======
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MyBlaze Core, top level entity
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MyBlaze Core, top level entity
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:copyright: Copyright (c) 2010 Jian Luo
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:copyright: Copyright (c) 2010 Jian Luo
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:author-email: jian.luo.cn(at_)gmail.com
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:author-email: jian.luo.cn(at_)gmail.com
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:license: LGPL, see LICENSE for details
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:license: LGPL, see LICENSE for details
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:revision: $Id: core.py 5 2010-11-21 10:59:30Z rockee $
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:revision: $Id: core.py 6 2010-11-21 23:18:44Z rockee $
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"""
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"""
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from myhdl import *
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from myhdl import *
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from defines import *
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from defines import *
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from functions import *
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from functions import *
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from fetch import *
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from fetch import *
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from decoder import *
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from decoder import *
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from execute import *
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from execute import *
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from memory import *
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from memory import *
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def MyBlazeCore(
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def MyBlazeCore(
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clock,
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clock,
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reset,
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reset,
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dmem_ena_in,
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dmem_ena_in,
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dmem_data_in,
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dmem_data_in,
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dmem_data_out,
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dmem_data_out,
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dmem_sel_out,
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dmem_sel_out,
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dmem_we_out,
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dmem_we_out,
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dmem_addr_out,
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dmem_addr_out,
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dmem_ena_out,
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dmem_ena_out,
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imem_data_in,
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imem_data_in,
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imem_addr_out,
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imem_addr_out,
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imem_ena_out,
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imem_ena_out,
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# if __debug__:
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# Ports only for debug
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#debug_if_program_counter,
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debug_if_program_counter=0,
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#debug_of_alu_op,
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debug_of_alu_op=0,
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#debug_of_alu_src_a,
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debug_of_alu_src_a=0,
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#debug_of_alu_src_b,
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debug_of_alu_src_b=0,
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#debug_of_branch_cond,
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debug_of_branch_cond=0,
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#debug_of_carry,
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debug_of_carry=0,
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#debug_of_carry_keep,
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debug_of_carry_keep=0,
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#debug_of_delay,
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debug_of_delay=0,
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#debug_of_hazard,
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debug_of_hazard=0,
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#debug_of_immediate,
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debug_of_immediate=0,
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#debug_of_instruction,
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debug_of_instruction=0,
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#debug_of_mem_read,
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debug_of_mem_read=0,
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#debug_of_mem_write,
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debug_of_mem_write=0,
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#debug_of_operation,
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debug_of_operation=0,
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#debug_of_program_counter,
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debug_of_program_counter=0,
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#debug_of_reg_a,
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debug_of_reg_a=0,
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#debug_of_reg_b,
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debug_of_reg_b=0,
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#debug_of_reg_d,
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debug_of_reg_d=0,
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#debug_of_reg_write,
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debug_of_reg_write=0,
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#debug_of_transfer_size,
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debug_of_transfer_size=0,
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#debug_of_fwd_mem_result,
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debug_of_fwd_mem_result=0,
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#debug_of_fwd_reg_d,
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debug_of_fwd_reg_d=0,
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#debug_of_fwd_reg_write,
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debug_of_fwd_reg_write=0,
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#debug_gprf_dat_a,
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debug_gprf_dat_a=0,
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#debug_gprf_dat_b,
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debug_gprf_dat_b=0,
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#debug_gprf_dat_d,
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debug_gprf_dat_d=0,
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#debug_ex_alu_result,
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debug_ex_alu_result=0,
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#debug_ex_reg_d,
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debug_ex_reg_d=0,
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#debug_ex_reg_write,
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debug_ex_reg_write=0,
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#debug_ex_branch,
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debug_ex_branch=0,
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#debug_ex_dat_d,
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debug_ex_dat_d=0,
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#debug_ex_flush_id,
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debug_ex_flush_id=0,
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#debug_ex_mem_read,
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debug_ex_mem_read=0,
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#debug_ex_mem_write,
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debug_ex_mem_write=0,
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#debug_ex_program_counter,
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debug_ex_program_counter=0,
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#debug_ex_transfer_size,
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debug_ex_transfer_size=0,
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#debug_ex_dat_a,
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debug_ex_dat_a=0,
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#debug_ex_dat_b,
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debug_ex_dat_b=0,
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#debug_ex_instruction,
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debug_ex_instruction=0,
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#debug_ex_reg_a,
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debug_ex_reg_a=0,
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#debug_ex_reg_b,
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debug_ex_reg_b=0,
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#debug_mm_alu_result,
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debug_mm_alu_result=0,
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#debug_mm_mem_read,
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debug_mm_mem_read=0,
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#debug_mm_reg_d,
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debug_mm_reg_d=0,
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#debug_mm_reg_write,
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debug_mm_reg_write=0,
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#debug_mm_transfer_size,
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debug_mm_transfer_size=0,
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DEBUG=True,
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):
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):
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"""
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"""
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"""
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"""
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#of_instruction = Signal(False)
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# Ports only for debug
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#if __debug__:
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of_instruction = 0
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#of_instruction = Signal(intbv(0)[CFG_IMEM_WIDTH:])
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if __debug__:
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of_instruction = Signal(intbv(0)[CFG_IMEM_WIDTH:])
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# End Ports only for debug
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if_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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if_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_alu_op = Signal(alu_operation.ALU_ADD)
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of_alu_op = Signal(alu_operation.ALU_ADD)
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of_alu_src_a = Signal(src_type_a.REGA)
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of_alu_src_a = Signal(src_type_a.REGA)
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of_alu_src_b = Signal(src_type_b.REGB)
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of_alu_src_b = Signal(src_type_b.REGB)
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of_branch_cond = Signal(branch_condition.NOP)
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of_branch_cond = Signal(branch_condition.NOP)
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of_carry = Signal(carry_type.C_ZERO)
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of_carry = Signal(carry_type.C_ZERO)
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of_carry_keep = Signal(False)
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of_carry_keep = Signal(False)
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of_delay = Signal(False)
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of_delay = Signal(False)
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of_hazard = Signal(False)
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of_hazard = Signal(False)
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of_immediate = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_immediate = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_mem_read = Signal(False)
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of_mem_read = Signal(False)
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of_mem_write = Signal(False)
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of_mem_write = Signal(False)
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of_operation = Signal(False)
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of_operation = Signal(False)
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of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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of_reg_a = Signal(intbv(0)[5:])
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of_reg_a = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_b = Signal(intbv(0)[5:])
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of_reg_b = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_d = Signal(intbv(0)[5:])
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of_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_reg_write = Signal(False)
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of_reg_write = Signal(False)
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of_transfer_size = Signal(transfer_size_type.WORD)
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of_transfer_size = Signal(transfer_size_type.WORD)
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# Write back stage forwards
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# Write back stage forwards
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of_fwd_mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_fwd_mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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of_fwd_reg_d = Signal(intbv(0)[5:])
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of_fwd_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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of_fwd_reg_write = Signal(False)
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of_fwd_reg_write = Signal(False)
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ex_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_reg_d = Signal(intbv(0)[5:])
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ex_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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ex_reg_write = Signal(False)
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ex_reg_write = Signal(False)
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ex_branch = Signal(False)
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ex_branch = Signal(False)
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ex_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_flush_id = Signal(False)
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ex_flush_id = Signal(False)
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ex_mem_read = Signal(False)
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ex_mem_read = Signal(False)
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ex_mem_write = Signal(False)
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ex_mem_write = Signal(False)
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ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
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ex_transfer_size = Signal(transfer_size_type.WORD)
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ex_transfer_size = Signal(transfer_size_type.WORD)
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# if __debug__:
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# Ports only for debug
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#ex_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_dat_a = 0
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#ex_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_dat_b = 0
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#ex_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_instruction = 0
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#ex_reg_a = Signal(intbv(0)[5:])
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ex_reg_a = 0
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#ex_reg_b = Signal(intbv(0)[5:])
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ex_reg_b = 0
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if __debug__:
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ex_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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ex_reg_a = Signal(intbv(0)[CFG_GPRF_SIZE:])
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ex_reg_b = Signal(intbv(0)[CFG_GPRF_SIZE:])
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# End Ports only for debug
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mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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mm_mem_read = Signal(False)
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mm_mem_read = Signal(False)
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mm_reg_d = Signal(intbv(0)[5:])
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mm_reg_d = Signal(intbv(0)[CFG_GPRF_SIZE:])
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mm_reg_write = Signal(False)
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mm_reg_write = Signal(False)
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mm_transfer_size = Signal(transfer_size_type.WORD)
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mm_transfer_size = Signal(transfer_size_type.WORD)
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ftch = FetchUnit(
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ftch = FetchUnit(
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clock=clock,
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clock=clock,
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reset=reset,
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reset=reset,
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enable=dmem_ena_in,
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enable=dmem_ena_in,
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of_hazard=of_hazard,
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of_hazard=of_hazard,
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ex_alu_result=ex_alu_result,
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ex_alu_result=ex_alu_result,
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ex_branch=ex_branch,
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ex_branch=ex_branch,
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if_program_counter=if_program_counter,
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if_program_counter=if_program_counter,
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imem_addr_out=imem_addr_out,
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imem_addr_out=imem_addr_out,
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imem_ena_out=imem_ena_out,
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imem_ena_out=imem_ena_out,
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)
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)
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deco = Decoder(
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deco = Decoder(
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clock=clock,
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clock=clock,
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reset=reset,
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reset=reset,
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enable=dmem_ena_in,
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enable=dmem_ena_in,
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dmem_data_in=dmem_data_in,
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dmem_data_in=dmem_data_in,
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imem_data_in=imem_data_in,
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imem_data_in=imem_data_in,
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if_program_counter=if_program_counter,
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if_program_counter=if_program_counter,
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ex_flush_id=ex_flush_id,
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ex_flush_id=ex_flush_id,
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mm_alu_result=mm_alu_result,
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mm_alu_result=mm_alu_result,
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mm_mem_read=mm_mem_read,
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mm_mem_read=mm_mem_read,
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mm_reg_d=mm_reg_d,
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mm_reg_d=mm_reg_d,
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mm_reg_write=mm_reg_write,
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mm_reg_write=mm_reg_write,
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mm_transfer_size=mm_transfer_size,
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mm_transfer_size=mm_transfer_size,
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gprf_dat_a=gprf_dat_a,
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gprf_dat_a=gprf_dat_a,
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gprf_dat_b=gprf_dat_b,
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gprf_dat_b=gprf_dat_b,
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gprf_dat_d=gprf_dat_d,
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gprf_dat_d=gprf_dat_d,
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of_alu_op=of_alu_op,
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of_alu_op=of_alu_op,
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of_alu_src_a=of_alu_src_a,
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of_alu_src_a=of_alu_src_a,
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of_alu_src_b=of_alu_src_b,
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of_alu_src_b=of_alu_src_b,
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of_branch_cond=of_branch_cond,
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of_branch_cond=of_branch_cond,
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of_carry=of_carry,
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of_carry=of_carry,
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of_carry_keep=of_carry_keep,
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of_carry_keep=of_carry_keep,
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of_delay=of_delay,
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of_delay=of_delay,
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of_hazard=of_hazard,
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of_hazard=of_hazard,
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of_immediate=of_immediate,
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of_immediate=of_immediate,
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of_mem_read=of_mem_read,
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of_mem_read=of_mem_read,
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of_mem_write=of_mem_write,
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of_mem_write=of_mem_write,
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of_operation=of_operation,
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of_operation=of_operation,
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of_program_counter=of_program_counter,
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of_program_counter=of_program_counter,
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of_reg_a=of_reg_a,
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of_reg_a=of_reg_a,
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of_reg_b=of_reg_b,
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of_reg_b=of_reg_b,
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of_reg_d=of_reg_d,
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of_reg_d=of_reg_d,
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of_reg_write=of_reg_write,
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of_reg_write=of_reg_write,
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of_transfer_size=of_transfer_size,
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of_transfer_size=of_transfer_size,
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# Write back stage output
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# Write back stage output
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of_fwd_mem_result=of_fwd_mem_result,
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of_fwd_mem_result=of_fwd_mem_result,
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of_fwd_reg_d=of_fwd_reg_d,
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of_fwd_reg_d=of_fwd_reg_d,
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of_fwd_reg_write=of_fwd_reg_write,
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of_fwd_reg_write=of_fwd_reg_write,
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# if __debug__:
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# Ports only for debug
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#of_instruction=of_instruction,
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of_instruction=of_instruction,
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)
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)
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exeu = ExecuteUnit(
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exeu = ExecuteUnit(
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# Inputs
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# Inputs
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clock=clock,
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clock=clock,
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reset=reset,
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reset=reset,
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enable=dmem_ena_in,
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enable=dmem_ena_in,
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dmem_data_in=dmem_data_in,
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dmem_data_in=dmem_data_in,
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gprf_dat_a=gprf_dat_a,
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gprf_dat_a=gprf_dat_a,
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gprf_dat_b=gprf_dat_b,
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gprf_dat_b=gprf_dat_b,
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gprf_dat_d=gprf_dat_d,
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gprf_dat_d=gprf_dat_d,
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mm_alu_result=mm_alu_result,
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mm_alu_result=mm_alu_result,
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mm_mem_read=mm_mem_read,
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mm_mem_read=mm_mem_read,
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mm_reg_d=mm_reg_d,
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mm_reg_d=mm_reg_d,
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mm_reg_write=mm_reg_write,
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mm_reg_write=mm_reg_write,
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mm_transfer_size=mm_transfer_size,
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mm_transfer_size=mm_transfer_size,
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of_alu_op=of_alu_op,
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of_alu_op=of_alu_op,
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of_alu_src_a=of_alu_src_a,
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of_alu_src_a=of_alu_src_a,
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of_alu_src_b=of_alu_src_b,
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of_alu_src_b=of_alu_src_b,
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of_branch_cond=of_branch_cond,
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of_branch_cond=of_branch_cond,
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of_carry=of_carry,
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of_carry=of_carry,
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of_carry_keep=of_carry_keep,
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of_carry_keep=of_carry_keep,
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of_delay=of_delay,
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of_delay=of_delay,
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of_immediate=of_immediate,
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of_immediate=of_immediate,
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of_mem_read=of_mem_read,
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of_mem_read=of_mem_read,
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of_mem_write=of_mem_write,
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of_mem_write=of_mem_write,
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of_operation=of_operation,
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of_operation=of_operation,
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of_program_counter=of_program_counter,
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of_program_counter=of_program_counter,
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of_reg_a=of_reg_a,
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of_reg_a=of_reg_a,
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of_reg_b=of_reg_b,
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of_reg_b=of_reg_b,
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of_reg_d=of_reg_d,
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of_reg_d=of_reg_d,
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of_reg_write=of_reg_write,
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of_reg_write=of_reg_write,
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of_transfer_size=of_transfer_size,
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of_transfer_size=of_transfer_size,
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|
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# Write back stage forwards,
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# Write back stage forwards,
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of_fwd_mem_result=of_fwd_mem_result,
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of_fwd_mem_result=of_fwd_mem_result,
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of_fwd_reg_d=of_fwd_reg_d,
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of_fwd_reg_d=of_fwd_reg_d,
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of_fwd_reg_write=of_fwd_reg_write,
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of_fwd_reg_write=of_fwd_reg_write,
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|
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# Outputs
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# Outputs
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ex_alu_result=ex_alu_result,
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ex_alu_result=ex_alu_result,
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ex_reg_d=ex_reg_d,
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ex_reg_d=ex_reg_d,
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ex_reg_write=ex_reg_write,
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ex_reg_write=ex_reg_write,
|
|
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ex_branch=ex_branch,
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ex_branch=ex_branch,
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ex_dat_d=ex_dat_d,
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ex_dat_d=ex_dat_d,
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ex_flush_id=ex_flush_id,
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ex_flush_id=ex_flush_id,
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ex_mem_read=ex_mem_read,
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ex_mem_read=ex_mem_read,
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ex_mem_write=ex_mem_write,
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ex_mem_write=ex_mem_write,
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ex_program_counter=ex_program_counter,
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ex_program_counter=ex_program_counter,
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ex_transfer_size=ex_transfer_size,
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ex_transfer_size=ex_transfer_size,
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|
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# if __debug__
|
# Ports only for debug
|
#of_instruction=of_instruction,
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of_instruction=of_instruction,
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#ex_dat_a=ex_dat_a,
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ex_dat_a=ex_dat_a,
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#ex_dat_b=ex_dat_b,
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ex_dat_b=ex_dat_b,
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#ex_instruction=ex_instruction,
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ex_instruction=ex_instruction,
|
#ex_reg_a=ex_reg_a,
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ex_reg_a=ex_reg_a,
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#ex_reg_b=ex_reg_b,
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ex_reg_b=ex_reg_b,
|
)
|
)
|
|
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memu = MemUnit(
|
memu = MemUnit(
|
# Inputs
|
# Inputs
|
clock=clock,
|
clock=clock,
|
reset=reset,
|
reset=reset,
|
enable=dmem_ena_in,
|
enable=dmem_ena_in,
|
ex_alu_result=ex_alu_result,
|
ex_alu_result=ex_alu_result,
|
ex_reg_d=ex_reg_d,
|
ex_reg_d=ex_reg_d,
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ex_reg_write=ex_reg_write,
|
ex_reg_write=ex_reg_write,
|
ex_branch=ex_branch,
|
ex_branch=ex_branch,
|
ex_dat_d=ex_dat_d,
|
ex_dat_d=ex_dat_d,
|
ex_mem_read=ex_mem_read,
|
ex_mem_read=ex_mem_read,
|
ex_mem_write=ex_mem_write,
|
ex_mem_write=ex_mem_write,
|
ex_program_counter=ex_program_counter,
|
ex_program_counter=ex_program_counter,
|
ex_transfer_size=ex_transfer_size,
|
ex_transfer_size=ex_transfer_size,
|
# Outputs
|
# Outputs
|
mm_alu_result=mm_alu_result,
|
mm_alu_result=mm_alu_result,
|
mm_mem_read=mm_mem_read,
|
mm_mem_read=mm_mem_read,
|
mm_reg_d=mm_reg_d,
|
mm_reg_d=mm_reg_d,
|
mm_reg_write=mm_reg_write,
|
mm_reg_write=mm_reg_write,
|
mm_transfer_size=mm_transfer_size,
|
mm_transfer_size=mm_transfer_size,
|
dmem_data_out=dmem_data_out,
|
dmem_data_out=dmem_data_out,
|
dmem_sel_out=dmem_sel_out,
|
dmem_sel_out=dmem_sel_out,
|
dmem_we_out=dmem_we_out,
|
dmem_we_out=dmem_we_out,
|
dmem_addr_out=dmem_addr_out,
|
dmem_addr_out=dmem_addr_out,
|
dmem_ena_out=dmem_ena_out,
|
dmem_ena_out=dmem_ena_out,
|
)
|
)
|
|
|
#@always_comb
|
@always_comb
|
#def debug_output():
|
def debug_output():
|
#debug_if_program_counter.next = if_program_counter
|
debug_if_program_counter.next = if_program_counter
|
|
|
#debug_of_alu_op.next = of_alu_op
|
debug_of_alu_op.next = of_alu_op
|
#debug_of_alu_src_a.next = of_alu_src_a
|
debug_of_alu_src_a.next = of_alu_src_a
|
#debug_of_alu_src_b.next = of_alu_src_b
|
debug_of_alu_src_b.next = of_alu_src_b
|
#debug_of_branch_cond.next = of_branch_cond
|
debug_of_branch_cond.next = of_branch_cond
|
#debug_of_carry.next = of_carry
|
debug_of_carry.next = of_carry
|
#debug_of_carry_keep.next = of_carry_keep
|
debug_of_carry_keep.next = of_carry_keep
|
#debug_of_delay.next = of_delay
|
debug_of_delay.next = of_delay
|
#debug_of_hazard.next = of_hazard
|
debug_of_hazard.next = of_hazard
|
#debug_of_immediate.next = of_immediate
|
debug_of_immediate.next = of_immediate
|
#debug_of_instruction.next = of_instruction
|
debug_of_instruction.next = of_instruction
|
#debug_of_mem_read.next = of_mem_read
|
debug_of_mem_read.next = of_mem_read
|
#debug_of_mem_write.next = of_mem_write
|
debug_of_mem_write.next = of_mem_write
|
#debug_of_operation.next = of_operation
|
debug_of_operation.next = of_operation
|
#debug_of_program_counter.next = of_program_counter
|
debug_of_program_counter.next = of_program_counter
|
#debug_of_reg_a.next = of_reg_a
|
debug_of_reg_a.next = of_reg_a
|
#debug_of_reg_b.next = of_reg_b
|
debug_of_reg_b.next = of_reg_b
|
#debug_of_reg_d.next = of_reg_d
|
debug_of_reg_d.next = of_reg_d
|
#debug_of_reg_write.next = of_reg_write
|
debug_of_reg_write.next = of_reg_write
|
#debug_of_transfer_size.next = of_transfer_size
|
debug_of_transfer_size.next = of_transfer_size
|
|
|
#debug_of_fwd_mem_result.next = of_fwd_mem_result
|
debug_of_fwd_mem_result.next = of_fwd_mem_result
|
#debug_of_fwd_reg_d.next = of_fwd_reg_d
|
debug_of_fwd_reg_d.next = of_fwd_reg_d
|
#debug_of_fwd_reg_write.next = of_fwd_reg_write
|
debug_of_fwd_reg_write.next = of_fwd_reg_write
|
|
|
#debug_gprf_dat_a.next = gprf_dat_a
|
debug_gprf_dat_a.next = gprf_dat_a
|
#debug_gprf_dat_b.next = gprf_dat_b
|
debug_gprf_dat_b.next = gprf_dat_b
|
#debug_gprf_dat_d.next = gprf_dat_d
|
debug_gprf_dat_d.next = gprf_dat_d
|
|
|
#debug_ex_alu_result.next = ex_alu_result
|
debug_ex_alu_result.next = ex_alu_result
|
#debug_ex_reg_d.next = ex_reg_d
|
debug_ex_reg_d.next = ex_reg_d
|
#debug_ex_reg_write.next = ex_reg_write
|
debug_ex_reg_write.next = ex_reg_write
|
|
|
#debug_ex_branch.next = ex_branch
|
debug_ex_branch.next = ex_branch
|
#debug_ex_dat_d.next = ex_dat_d
|
debug_ex_dat_d.next = ex_dat_d
|
#debug_ex_flush_id.next = ex_flush_id
|
debug_ex_flush_id.next = ex_flush_id
|
#debug_ex_mem_read.next = ex_mem_read
|
debug_ex_mem_read.next = ex_mem_read
|
#debug_ex_mem_write.next = ex_mem_write
|
debug_ex_mem_write.next = ex_mem_write
|
#debug_ex_program_counter.next = ex_program_counter
|
debug_ex_program_counter.next = ex_program_counter
|
#debug_ex_transfer_size.next = ex_transfer_size
|
debug_ex_transfer_size.next = ex_transfer_size
|
|
|
#debug_ex_dat_a.next = ex_dat_a
|
debug_ex_dat_a.next = ex_dat_a
|
#debug_ex_dat_b.next = ex_dat_b
|
debug_ex_dat_b.next = ex_dat_b
|
#debug_ex_instruction.next = ex_instruction
|
debug_ex_instruction.next = ex_instruction
|
#debug_ex_reg_a.next = ex_reg_a
|
debug_ex_reg_a.next = ex_reg_a
|
#debug_ex_reg_b.next = ex_reg_b
|
debug_ex_reg_b.next = ex_reg_b
|
|
|
#debug_mm_alu_result.next = mm_alu_result
|
debug_mm_alu_result.next = mm_alu_result
|
#debug_mm_mem_read.next = mm_mem_read
|
debug_mm_mem_read.next = mm_mem_read
|
#debug_mm_reg_d.next = mm_reg_d
|
debug_mm_reg_d.next = mm_reg_d
|
#debug_mm_reg_write.next = mm_reg_write
|
debug_mm_reg_write.next = mm_reg_write
|
#debug_mm_transfer_size.next = mm_transfer_size
|
debug_mm_transfer_size.next = mm_transfer_size
|
|
|
return instances()
|
if DEBUG:
|
|
return ftch, deco, exeu, memu, debug_output
|
|
return ftch, deco, exeu, memu
|
|
|
def bench():
|
def bench():
|
clock = Signal(False)
|
clock = Signal(False)
|
reset = Signal(False)
|
reset = Signal(False)
|
|
|
dmem_ena_in = Signal(False)
|
dmem_ena_in = Signal(False)
|
dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_sel_out = Signal(intbv(0)[4:])
|
dmem_sel_out = Signal(intbv(0)[4:])
|
dmem_we_out = Signal(False)
|
dmem_we_out = Signal(False)
|
dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
|
dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
|
dmem_ena_out = Signal(False)
|
dmem_ena_out = Signal(False)
|
imem_data_in = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
imem_data_in = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
imem_ena_out = Signal(False)
|
imem_ena_out = Signal(False)
|
|
|
core = MyBlazeCore(
|
core = MyBlazeCore(
|
clock=clock,
|
clock=clock,
|
reset=reset,
|
reset=reset,
|
dmem_ena_in=dmem_ena_in,
|
dmem_ena_in=dmem_ena_in,
|
|
|
dmem_data_in=dmem_data_in,
|
dmem_data_in=dmem_data_in,
|
dmem_data_out=dmem_data_out,
|
dmem_data_out=dmem_data_out,
|
dmem_sel_out=dmem_sel_out,
|
dmem_sel_out=dmem_sel_out,
|
dmem_we_out=dmem_we_out,
|
dmem_we_out=dmem_we_out,
|
dmem_addr_out=dmem_addr_out,
|
dmem_addr_out=dmem_addr_out,
|
dmem_ena_out=dmem_ena_out,
|
dmem_ena_out=dmem_ena_out,
|
imem_data_in=imem_data_in,
|
imem_data_in=imem_data_in,
|
imem_addr_out=imem_addr_out,
|
imem_addr_out=imem_addr_out,
|
imem_ena_out=imem_ena_out,
|
imem_ena_out=imem_ena_out,
|
)
|
)
|
#code = ['001000''00','001''00000','0000''0000','0000''0001', # addi r1,r0,1
|
#code = ['001000''00','001''00000','0000''0000','0000''0001', # addi r1,r0,1
|
#'001000''00','010''00000','0000''0000','0000''0010', # addi r1,r0,2
|
#'001000''00','010''00000','0000''0000','0000''0010', # addi r1,r0,2
|
#'001000''00','011''00000','0000''0000','0000''0011', # addi r1,r0,3
|
#'001000''00','011''00000','0000''0000','0000''0011', # addi r1,r0,3
|
#'001000''00','100''00000','0000''0000','0000''0100', # addi r1,r0,4
|
#'001000''00','100''00000','0000''0000','0000''0100', # addi r1,r0,4
|
#'001000''00','101''00000','0000''0000','0000''0101', # addi r1,r0,5
|
#'001000''00','101''00000','0000''0000','0000''0101', # addi r1,r0,5
|
#'001000''00','110''00000','0000''0000','0000''0110', # addi r1,r0,6
|
#'001000''00','110''00000','0000''0000','0000''0110', # addi r1,r0,6
|
#'001000''00','111''00000','0000''0000','0000''0111', # addi r1,r0,7
|
#'001000''00','111''00000','0000''0000','0000''0111', # addi r1,r0,7
|
#'001000''01','000''00000','0000''0000','0000''1000', # addi r1,r0,8
|
#'001000''01','000''00000','0000''0000','0000''1000', # addi r1,r0,8
|
#]
|
#]
|
#imem = [int(x, 16) for x in code]
|
#imem = [int(x, 16) for x in code]
|
imem = []
|
imem = []
|
for x in open('rom.vmem').readlines():
|
for x in open('rom.vmem').readlines():
|
x = int(x, 16)
|
x = int(x, 16)
|
imem.append((x>>24)%256)
|
imem.append((x>>24)%256)
|
imem.append((x>>16)%256)
|
imem.append((x>>16)%256)
|
imem.append((x>>8)%256)
|
imem.append((x>>8)%256)
|
imem.append((x>>0)%256)
|
imem.append((x>>0)%256)
|
|
|
dmem = imem
|
dmem = imem
|
print 'memory size: 0x%04x' % len(imem)
|
print 'memory size: 0x%04x' % len(imem)
|
#imem = [int(x, 16) for x in open('rom.vmem').readlines()]
|
#imem = [int(x, 16) for x in open('rom.vmem').readlines()]
|
#dmem = [Signal(intbv(0)[32:]) for i in range(2**14)]
|
#dmem = [Signal(intbv(0)[32:]) for i in range(2**14)]
|
import re
|
import re
|
|
|
@always(delay(10))
|
@always(delay(10))
|
def clockgen():
|
def clockgen():
|
clock.next = not clock
|
clock.next = not clock
|
|
|
@instance
|
@instance
|
def ram():
|
def ram():
|
while 1:
|
while 1:
|
yield clock.posedge
|
yield clock.posedge
|
if dmem_ena_out:
|
if dmem_ena_out:
|
dmem_ena_in.next = False
|
dmem_ena_in.next = False
|
addr = int(dmem_addr_out)
|
addr = int(dmem_addr_out)
|
aligned_addr = (dmem_addr_out/4*4)
|
aligned_addr = (dmem_addr_out/4*4)
|
if (dmem_sel_out == 0b1000 or
|
if (dmem_sel_out == 0b1000 or
|
dmem_sel_out == 0b0100 or
|
dmem_sel_out == 0b0100 or
|
dmem_sel_out == 0b0010 or
|
dmem_sel_out == 0b0010 or
|
dmem_sel_out == 0b0001):
|
dmem_sel_out == 0b0001):
|
size = 1
|
size = 1
|
elif (dmem_sel_out == 0b1100 or
|
elif (dmem_sel_out == 0b1100 or
|
dmem_sel_out == 0b0011) and addr%2==0:
|
dmem_sel_out == 0b0011) and addr%2==0:
|
size = 2
|
size = 2
|
elif dmem_sel_out == 0b1111 and addr%4==0:
|
elif dmem_sel_out == 0b1111 and addr%4==0:
|
size = 4
|
size = 4
|
else:
|
else:
|
assert False
|
assert False
|
|
|
if dmem_we_out:
|
if dmem_we_out:
|
if size==1:
|
if size==1:
|
if addr == 0xffffffc0:
|
if addr == 0xffffffc0:
|
print chr(dmem_data_out%256),
|
print chr(dmem_data_out%256),
|
else:
|
else:
|
dmem[addr] = dmem_data_out%256
|
dmem[addr] = dmem_data_out%256
|
elif size==2:
|
elif size==2:
|
dmem[addr] = (dmem_data_out>>8)%256
|
dmem[addr] = (dmem_data_out>>8)%256
|
dmem[addr+1] = dmem_data_out%256
|
dmem[addr+1] = dmem_data_out%256
|
else:
|
else:
|
dmem[addr] = (dmem_data_out>>24)%256
|
dmem[addr] = (dmem_data_out>>24)%256
|
dmem[addr+1] = (dmem_data_out>>16)%256
|
dmem[addr+1] = (dmem_data_out>>16)%256
|
dmem[addr+2] = (dmem_data_out>>8)%256
|
dmem[addr+2] = (dmem_data_out>>8)%256
|
dmem[addr+3] = (dmem_data_out>>0)%256
|
dmem[addr+3] = (dmem_data_out>>0)%256
|
#dmem[dmem_addr_out/4].next = dmem_data_out
|
#dmem[dmem_addr_out/4].next = dmem_data_out
|
#print 'write addr=0x%08x data=0x%08x' % (dmem_addr_out, dmem_data_out)
|
#print 'write addr=0x%08x data=0x%08x' % (dmem_addr_out, dmem_data_out)
|
else:
|
else:
|
dmem_data_in.next = (
|
dmem_data_in.next = (
|
((dmem[aligned_addr]%256)<<24)
|
((dmem[aligned_addr]%256)<<24)
|
+((dmem[aligned_addr+1]%256)<<16)
|
+((dmem[aligned_addr+1]%256)<<16)
|
+((dmem[aligned_addr+2]%256)<<8)
|
+((dmem[aligned_addr+2]%256)<<8)
|
+(dmem[aligned_addr+3]%256)
|
+(dmem[aligned_addr+3]%256)
|
)
|
)
|
#yield clock.posedge
|
#yield clock.posedge
|
yield clock.posedge
|
yield clock.posedge
|
dmem_ena_in.next = True
|
dmem_ena_in.next = True
|
|
|
@instance
|
@instance
|
def stimulus():
|
def stimulus():
|
reset.next = True
|
reset.next = True
|
yield delay(33)
|
yield delay(33)
|
reset.next = False
|
reset.next = False
|
dmem_ena_in.next = True
|
dmem_ena_in.next = True
|
yield reset.negedge
|
yield reset.negedge
|
#for i in range(len(imem)):
|
#for i in range(len(imem)):
|
while 1:
|
while 1:
|
iaddr = int(imem_addr_out)
|
iaddr = int(imem_addr_out)
|
if iaddr >= len(imem):
|
if iaddr >= len(imem):
|
break
|
break
|
#print 'cycle %d: imem addr:=0x%x code:=0x%08x\n' % (
|
|
#i, iaddr, imem[iaddr/4])
|
|
word = (((imem[iaddr]%256)<<24)
|
word = (((imem[iaddr]%256)<<24)
|
+((imem[iaddr+1]%256)<<16)
|
+((imem[iaddr+1]%256)<<16)
|
+((imem[iaddr+2]%256)<<8)
|
+((imem[iaddr+2]%256)<<8)
|
+(imem[iaddr+3]%256))
|
+(imem[iaddr+3]%256))
|
#print 'imem addr:=0x%x code:=0x%08x' % (iaddr, word)
|
#print 'imem addr:=0x%x code:=0x%08x' % (iaddr, word)
|
#print '<dissemble> %s' % code.get(iaddr)
|
#print '<dissemble> %s' % code.get(iaddr)
|
imem_data_in.next = word
|
imem_data_in.next = word
|
yield clock.negedge
|
yield clock.negedge
|
|
|
for i in range(8):
|
for i in range(8):
|
#print 'cycle %d: imem addr:=0x%x code:=NOP' % (i+len(imem),
|
#print 'cycle %d: imem addr:=0x%x code:=NOP' % (i+len(imem),
|
#imem_addr_out)
|
#imem_addr_out)
|
imem_data_in.next = 0
|
imem_data_in.next = 0
|
yield clock.negedge
|
yield clock.negedge
|
StopSimulation()
|
StopSimulation()
|
assert False # map(int, dmem[:4]
|
assert False # map(int, dmem[:4]
|
return instances()
|
return instances()
|
|
|
if __name__ == '__main__':
|
if __name__ == '__main__':
|
if 0:
|
if 0:
|
clock = Signal(False)
|
clock = Signal(False)
|
reset = Signal(False)
|
reset = Signal(False)
|
|
|
dmem_ena_in = Signal(False)
|
dmem_ena_in = Signal(False)
|
dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
dmem_sel_out = Signal(intbv(0)[4:])
|
dmem_sel_out = Signal(intbv(0)[4:])
|
dmem_we_out = Signal(False)
|
dmem_we_out = Signal(False)
|
dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
|
dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
|
dmem_ena_out = Signal(False)
|
dmem_ena_out = Signal(False)
|
imem_data_in = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
imem_data_in = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
imem_ena_out = Signal(False)
|
imem_ena_out = Signal(False)
|
|
|
kw = dict(
|
kw = dict(
|
func=MyBlazeCore,
|
|
clock=clock,
|
clock=clock,
|
reset=reset,
|
reset=reset,
|
dmem_ena_in=dmem_ena_in,
|
dmem_ena_in=dmem_ena_in,
|
|
|
dmem_data_in=dmem_data_in,
|
dmem_data_in=dmem_data_in,
|
dmem_data_out=dmem_data_out,
|
dmem_data_out=dmem_data_out,
|
dmem_sel_out=dmem_sel_out,
|
dmem_sel_out=dmem_sel_out,
|
dmem_we_out=dmem_we_out,
|
dmem_we_out=dmem_we_out,
|
dmem_addr_out=dmem_addr_out,
|
dmem_addr_out=dmem_addr_out,
|
dmem_ena_out=dmem_ena_out,
|
dmem_ena_out=dmem_ena_out,
|
imem_data_in=imem_data_in,
|
imem_data_in=imem_data_in,
|
imem_addr_out=imem_addr_out,
|
imem_addr_out=imem_addr_out,
|
imem_ena_out=imem_ena_out,
|
imem_ena_out=imem_ena_out,
|
)
|
)
|
toVHDL(**kw)
|
toVHDL(MyBlazeCore, **kw)
|
toVerilog(**kw)
|
toVerilog(MyBlazeCore, **kw)
|
else:
|
else:
|
tb = bench()
|
tb = bench()
|
#tb = traceSignals(bench)
|
#tb = traceSignals(bench)
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Simulation(tb).run(2000000)
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Simulation(tb).run(2000000)
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### EOF ###
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### EOF ###
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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