# -*- coding: utf-8 -*-
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# -*- coding: utf-8 -*-
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"""
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"""
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top.py
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top.py
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======
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======
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Top Level of the System Design
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Top Level of the System Design
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:copyright: Copyright (c) 2010 Jian Luo
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:copyright: Copyright (c) 2010 Jian Luo
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:author-email: jian.luo.cn(at_)gmail.com
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:author-email: jian.luo.cn(at_)gmail.com
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:license: LGPL, see LICENSE for details
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:license: LGPL, see LICENSE for details
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:revision: $Id: top.py 3 2010-11-21 07:17:00Z rockee $
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:revision: $Id: top.py 6 2010-11-21 23:18:44Z rockee $
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"""
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"""
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from myhdl import *
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from myhdl import *
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from defines import *
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from defines import *
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from functions import *
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from functions import *
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from core import *
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from core import *
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from uart import *
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from uart import *
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from bram import *
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from bram import *
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program = []
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program = []
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def prepare():
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def prepare():
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one = open('rom.vmem')
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one = open('rom.vmem')
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banks = [open('rom%s.vmem'%i, 'w') for i in range(4)]
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banks = [open('rom%s.vmem'%i, 'w') for i in range(4)]
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try:
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try:
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for line in one.readlines():
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for line in one.readlines():
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program.append(int(line, 16))
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program.append(int(line, 16))
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for i in range(4):
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for i in range(4):
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print >>banks[3-i], line[i*2:(i+1)*2]
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print >>banks[3-i], line[i*2:(i+1)*2]
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finally:
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finally:
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[f.close() for f in banks]
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[f.close() for f in banks]
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one.close()
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one.close()
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def Program(data_out, data_in, address, write, enable, clock, *args, **kw):
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def Program(data_out, data_in, address, write, enable, clock, *args, **kw):
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imem = tuple(program)
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imem = tuple(program)
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@always(clock.posedge)
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@always(clock.posedge)
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def output():
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def output():
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#if enable:
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#if enable:
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data_out.next = imem[address[:2]]
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data_out.next = imem[address[:2]]
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return instances()
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return instances()
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def SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
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def SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
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# if __debug__:
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# Ports only for debug
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debug_if_program_counter,
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debug_if_program_counter=0,
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debug_of_alu_op,
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debug_of_alu_src_a,
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debug_of_alu_src_b,
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debug_of_branch_cond,
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debug_of_carry,
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debug_of_carry_keep,
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debug_of_delay,
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debug_of_hazard,
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debug_of_immediate,
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debug_of_instruction,
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debug_of_mem_read,
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debug_of_mem_write,
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debug_of_operation,
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debug_of_program_counter,
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debug_of_reg_a,
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debug_of_reg_b,
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debug_of_reg_d,
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debug_of_reg_write,
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debug_of_transfer_size,
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debug_of_fwd_mem_result,
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debug_of_fwd_reg_d,
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debug_of_fwd_reg_write,
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debug_gprf_dat_a,
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debug_gprf_dat_b,
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debug_gprf_dat_d,
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debug_ex_alu_result,
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debug_ex_reg_d,
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debug_ex_reg_write,
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debug_ex_branch,
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debug_ex_dat_d,
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debug_ex_flush_id,
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debug_ex_mem_read,
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debug_ex_mem_write,
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debug_ex_program_counter,
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debug_ex_transfer_size,
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debug_ex_dat_a,
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debug_of_alu_op=0,
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debug_ex_dat_b,
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debug_of_alu_src_a=0,
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debug_ex_instruction,
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debug_of_alu_src_b=0,
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debug_ex_reg_a,
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debug_of_branch_cond=0,
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debug_ex_reg_b,
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debug_of_carry=0,
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debug_of_carry_keep=0,
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debug_of_delay=0,
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debug_of_hazard=0,
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debug_of_immediate=0,
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debug_of_instruction=0,
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debug_of_mem_read=0,
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debug_of_mem_write=0,
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debug_of_operation=0,
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debug_of_program_counter=0,
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debug_of_reg_a=0,
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debug_of_reg_b=0,
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debug_of_reg_d=0,
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debug_of_reg_write=0,
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debug_of_transfer_size=0,
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debug_of_fwd_mem_result=0,
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debug_of_fwd_reg_d=0,
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debug_of_fwd_reg_write=0,
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debug_gprf_dat_a=0,
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debug_gprf_dat_b=0,
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debug_gprf_dat_d=0,
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debug_ex_alu_result=0,
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debug_ex_reg_d=0,
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debug_ex_reg_write=0,
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debug_ex_branch=0,
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debug_ex_dat_d=0,
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debug_ex_flush_id=0,
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debug_ex_mem_read=0,
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debug_ex_mem_write=0,
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debug_ex_program_counter=0,
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debug_ex_transfer_size=0,
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debug_ex_dat_a=0,
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debug_ex_dat_b=0,
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debug_ex_instruction=0,
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debug_ex_reg_a=0,
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debug_ex_reg_b=0,
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debug_mm_alu_result=0,
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debug_mm_mem_read=0,
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debug_mm_reg_d=0,
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debug_mm_reg_write=0,
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debug_mm_transfer_size=0,
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debug_dmem_ena_in=0,
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debug_dmem_data_in=0,
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debug_dmem_data_out=0,
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debug_dmem_sel_out=0,
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debug_dmem_we_out=0,
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debug_dmem_addr_out=0,
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debug_dmem_ena_out=0,
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debug_dmem_ena=0,
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debug_imem_data_in=0,
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debug_imem_data_out=0,
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debug_imem_sel_out=0,
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debug_imem_we_out=0,
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debug_imem_addr_out=0,
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debug_imem_ena=0,
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debug_imem_ena_out=0,
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debug_mm_alu_result,
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size=4, DEBUG=True):
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debug_mm_mem_read,
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debug_mm_reg_d,
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debug_mm_reg_write,
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debug_mm_transfer_size,
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debug_dmem_ena_in,
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debug_dmem_data_in,
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debug_dmem_data_out,
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debug_dmem_sel_out,
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debug_dmem_we_out,
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debug_dmem_addr_out,
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debug_dmem_ena_out,
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debug_dmem_ena,
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debug_imem_data_in,
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debug_imem_data_out,
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debug_imem_sel_out,
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debug_imem_we_out,
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debug_imem_addr_out,
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debug_imem_ena,
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debug_imem_ena_out,
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size=4):
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rx_data = Signal(intbv(0)[32:])
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rx_data = Signal(intbv(0)[32:])
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rx_avail = Signal(False)
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rx_avail = Signal(False)
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rx_error = Signal(False)
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rx_error = Signal(False)
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read_en = Signal(False)
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read_en = Signal(False)
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tx_data = Signal(intbv(0)[32:])
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tx_data = Signal(intbv(0)[32:])
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tx_busy = Signal(False)
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tx_busy = Signal(False)
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write_en = Signal(False)
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write_en = Signal(False)
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uart_rxd = Signal(False)
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uart_rxd = Signal(False)
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uart_txd = Signal(False)
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uart_txd = Signal(False)
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rx_data2 = Signal(intbv(0)[32:])
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rx_data2 = Signal(intbv(0)[32:])
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rx_avail2 = Signal(False)
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rx_avail2 = Signal(False)
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rx_error2 = Signal(False)
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rx_error2 = Signal(False)
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read_en2 = Signal(False)
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read_en2 = Signal(False)
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tx_data2 = Signal(intbv(0)[32:])
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tx_data2 = Signal(intbv(0)[32:])
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tx_busy2 = Signal(False)
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tx_busy2 = Signal(False)
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write_en2 = Signal(False)
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write_en2 = Signal(False)
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uart_rxd2 = Signal(False)
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uart_rxd2 = Signal(False)
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uart_txd2 = Signal(False)
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uart_txd2 = Signal(False)
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led_reg = Signal(intbv(0)[32:])
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led_reg = Signal(intbv(0)[32:])
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led_low = Signal(intbv(0)[32:])
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led_low = Signal(intbv(0)[32:])
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dmem_ena_in = Signal(False)
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dmem_ena_in = Signal(False)
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dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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dmem_sel_out = Signal(intbv(0)[4:])
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dmem_sel_out = Signal(intbv(0)[4:])
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dmem_sel = Signal(intbv(0)[4:])
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dmem_sel = Signal(intbv(0)[4:])
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dmem_we_out = Signal(False)
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dmem_we_out = Signal(False)
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dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
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dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
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dmem_ena_out = Signal(False)
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dmem_ena_out = Signal(False)
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dmem_ena = Signal(False)
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dmem_ena = Signal(False)
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imem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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imem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
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imem_data_out = Signal(intbv(0)[CFG_IMEM_WIDTH:])
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imem_data_out = Signal(intbv(0)[CFG_IMEM_WIDTH:])
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imem_sel_out = Signal(intbv(0)[4:])
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imem_sel_out = Signal(intbv(0)[4:])
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imem_we_out = Signal(False)
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imem_we_out = Signal(False)
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imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
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imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
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imem_ena = Signal(True)
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imem_ena = Signal(True)
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imem_ena_out = Signal(False)
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imem_ena_out = Signal(False)
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imem = BankedBRAM(imem_data_in, imem_data_out, imem_addr_out,
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imem = BankedBRAM(imem_data_in, imem_data_out, imem_addr_out,
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imem_sel_out, imem_ena_out, clock,
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imem_sel_out, imem_ena_out, clock,
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size=size, to_verilog=True,
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size=size, to_verilog=True,
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filename_pattern='rom%s.vmem')
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filename_pattern='rom%s.vmem')
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#imem = Program(imem_data_in, imem_data_out, imem_addr_out,
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#imem = Program(imem_data_in, imem_data_out, imem_addr_out,
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#imem_sel_out, imem_ena_out, clock,
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#imem_sel_out, imem_ena_out, clock,
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#size=size, to_verilog=True,
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#size=size, to_verilog=True,
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#filename_pattern='rom%s.vmem')
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#filename_pattern='rom%s.vmem')
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dmem = BankedBRAM(dmem_data_in, dmem_data_out, dmem_addr_out,
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dmem = BankedBRAM(dmem_data_in, dmem_data_out, dmem_addr_out,
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dmem_sel, dmem_ena, clock,
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dmem_sel, dmem_ena, clock,
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size=size, to_verilog=True,
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size=size, to_verilog=True,
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filename_pattern='rom%s.vmem')
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filename_pattern='rom%s.vmem')
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core = MyBlazeCore(
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core = MyBlazeCore(
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clock=clock,
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clock=clock,
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reset=reset,
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reset=reset,
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dmem_ena_in=dmem_ena_in,
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dmem_ena_in=dmem_ena_in,
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dmem_data_in=dmem_data_in,
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dmem_data_in=dmem_data_in,
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dmem_data_out=dmem_data_out,
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dmem_data_out=dmem_data_out,
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dmem_sel_out=dmem_sel_out,
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dmem_sel_out=dmem_sel_out,
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dmem_we_out=dmem_we_out,
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dmem_we_out=dmem_we_out,
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dmem_addr_out=dmem_addr_out,
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dmem_addr_out=dmem_addr_out,
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dmem_ena_out=dmem_ena_out,
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dmem_ena_out=dmem_ena_out,
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imem_data_in=imem_data_in,
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imem_data_in=imem_data_in,
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imem_addr_out=imem_addr_out,
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imem_addr_out=imem_addr_out,
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imem_ena_out=imem_ena_out,
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imem_ena_out=imem_ena_out,
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# if __debug__:
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# Ports only for debug
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debug_if_program_counter=debug_if_program_counter,
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debug_if_program_counter=debug_if_program_counter,
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debug_of_alu_op=debug_of_alu_op,
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debug_of_alu_op=debug_of_alu_op,
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debug_of_alu_src_a=debug_of_alu_src_a,
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debug_of_alu_src_a=debug_of_alu_src_a,
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debug_of_alu_src_b=debug_of_alu_src_b,
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debug_of_alu_src_b=debug_of_alu_src_b,
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debug_of_branch_cond=debug_of_branch_cond,
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debug_of_branch_cond=debug_of_branch_cond,
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debug_of_carry=debug_of_carry,
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debug_of_carry=debug_of_carry,
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debug_of_carry_keep=debug_of_carry_keep,
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debug_of_carry_keep=debug_of_carry_keep,
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debug_of_delay=debug_of_delay,
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debug_of_delay=debug_of_delay,
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debug_of_hazard=debug_of_hazard,
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debug_of_hazard=debug_of_hazard,
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debug_of_immediate=debug_of_immediate,
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debug_of_immediate=debug_of_immediate,
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debug_of_instruction=debug_of_instruction,
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debug_of_instruction=debug_of_instruction,
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debug_of_mem_read=debug_of_mem_read,
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debug_of_mem_read=debug_of_mem_read,
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debug_of_mem_write=debug_of_mem_write,
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debug_of_mem_write=debug_of_mem_write,
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debug_of_operation=debug_of_operation,
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debug_of_operation=debug_of_operation,
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debug_of_program_counter=debug_of_program_counter,
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debug_of_program_counter=debug_of_program_counter,
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debug_of_reg_a=debug_of_reg_a,
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debug_of_reg_a=debug_of_reg_a,
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debug_of_reg_b=debug_of_reg_b,
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debug_of_reg_b=debug_of_reg_b,
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debug_of_reg_d=debug_of_reg_d,
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debug_of_reg_d=debug_of_reg_d,
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debug_of_reg_write=debug_of_reg_write,
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debug_of_reg_write=debug_of_reg_write,
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debug_of_transfer_size=debug_of_transfer_size,
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debug_of_transfer_size=debug_of_transfer_size,
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debug_of_fwd_mem_result=debug_of_fwd_mem_result,
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debug_of_fwd_mem_result=debug_of_fwd_mem_result,
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debug_of_fwd_reg_d=debug_of_fwd_reg_d,
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debug_of_fwd_reg_d=debug_of_fwd_reg_d,
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debug_of_fwd_reg_write=debug_of_fwd_reg_write,
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debug_of_fwd_reg_write=debug_of_fwd_reg_write,
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debug_gprf_dat_a=debug_gprf_dat_a,
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debug_gprf_dat_a=debug_gprf_dat_a,
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debug_gprf_dat_b=debug_gprf_dat_b,
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debug_gprf_dat_b=debug_gprf_dat_b,
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debug_gprf_dat_d=debug_gprf_dat_d,
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debug_gprf_dat_d=debug_gprf_dat_d,
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debug_ex_alu_result=debug_ex_alu_result,
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debug_ex_alu_result=debug_ex_alu_result,
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debug_ex_reg_d=debug_ex_reg_d,
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debug_ex_reg_d=debug_ex_reg_d,
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debug_ex_reg_write=debug_ex_reg_write,
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debug_ex_reg_write=debug_ex_reg_write,
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debug_ex_branch=debug_ex_branch,
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debug_ex_branch=debug_ex_branch,
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debug_ex_dat_d=debug_ex_dat_d,
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debug_ex_dat_d=debug_ex_dat_d,
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debug_ex_flush_id=debug_ex_flush_id,
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debug_ex_flush_id=debug_ex_flush_id,
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debug_ex_mem_read=debug_ex_mem_read,
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debug_ex_mem_read=debug_ex_mem_read,
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debug_ex_mem_write=debug_ex_mem_write,
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debug_ex_mem_write=debug_ex_mem_write,
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debug_ex_program_counter=debug_ex_program_counter,
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debug_ex_program_counter=debug_ex_program_counter,
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debug_ex_transfer_size=debug_ex_transfer_size,
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debug_ex_transfer_size=debug_ex_transfer_size,
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debug_ex_dat_a=debug_ex_dat_a,
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debug_ex_dat_a=debug_ex_dat_a,
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debug_ex_dat_b=debug_ex_dat_b,
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debug_ex_dat_b=debug_ex_dat_b,
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debug_ex_instruction=debug_ex_instruction,
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debug_ex_instruction=debug_ex_instruction,
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debug_ex_reg_a=debug_ex_reg_a,
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debug_ex_reg_a=debug_ex_reg_a,
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debug_ex_reg_b=debug_ex_reg_b,
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debug_ex_reg_b=debug_ex_reg_b,
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debug_mm_alu_result=debug_mm_alu_result,
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debug_mm_alu_result=debug_mm_alu_result,
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debug_mm_mem_read=debug_mm_mem_read,
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debug_mm_mem_read=debug_mm_mem_read,
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debug_mm_reg_d=debug_mm_reg_d,
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debug_mm_reg_d=debug_mm_reg_d,
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debug_mm_reg_write=debug_mm_reg_write,
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debug_mm_reg_write=debug_mm_reg_write,
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debug_mm_transfer_size=debug_mm_transfer_size,
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debug_mm_transfer_size=debug_mm_transfer_size,
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DEBUG=DEBUG,
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)
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)
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|
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uart = UART(rx_data, rx_avail, rx_error, read_en,
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uart = UART(rx_data, rx_avail, rx_error, read_en,
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tx_data, tx_busy, write_en,
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tx_data, tx_busy, write_en,
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uart_rxd, uart_txd, reset, clock,
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uart_rxd, uart_txd, reset, clock,
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freq_hz=50000000, baud=115200)
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freq_hz=50000000, baud=115200)
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uart2 = UART(rx_data2, rx_avail2, rx_error2, read_en2,
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uart2 = UART(rx_data2, rx_avail2, rx_error2, read_en2,
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tx_data2, tx_busy2, write_en2,
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tx_data2, tx_busy2, write_en2,
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uart_rxd2, uart_txd2, reset, clock,
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uart_rxd2, uart_txd2, reset, clock,
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freq_hz=50000000, baud=115200)
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freq_hz=50000000, baud=115200)
|
|
|
@always_comb
|
@always_comb
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def glue():
|
def glue():
|
dmem_ena_in.next = True
|
dmem_ena_in.next = True
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if dmem_we_out:
|
if dmem_we_out:
|
dmem_sel.next = dmem_sel_out
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dmem_sel.next = dmem_sel_out
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else:
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else:
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dmem_sel.next = 0
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dmem_sel.next = 0
|
tx_data.next = dmem_data_out
|
tx_data.next = dmem_data_out
|
if dmem_addr_out < 2**size:
|
if dmem_addr_out < 2**size:
|
dmem_ena.next = dmem_ena_out
|
dmem_ena.next = dmem_ena_out
|
#dmem_ena_in.next = True
|
|
write_en.next = False
|
write_en.next = False
|
elif dmem_we_out and dmem_addr_out[28:] >= 0xfffffb0:
|
elif dmem_we_out and dmem_addr_out[28:] >= 0xfffffc0:
|
dmem_ena.next = False
|
dmem_ena.next = False
|
#dmem_ena_in.next = not tx_busy
|
dmem_ena_in.next = not tx_busy
|
write_en.next = True
|
write_en.next = True
|
else:
|
else:
|
write_en.next = False
|
write_en.next = False
|
dmem_ena.next = False
|
dmem_ena.next = False
|
#dmem_ena_in.next = True
|
|
|
|
#leds.next = concat(led_reg[4:], led_low[4:])
|
#leds.next = concat(led_reg[4:], led_low[4:])
|
leds.next = led_reg[8:]
|
leds.next = led_reg[8:]
|
|
|
count = Signal(intbv(0)[20:])
|
count = Signal(intbv(0)[20:])
|
@always(clock.posedge)
|
@always(clock.posedge)
|
def run():
|
def run():
|
|
|
if reset:
|
if reset:
|
txd_line.next = False
|
txd_line.next = False
|
txd_line2.next = False
|
txd_line2.next = False
|
led_reg.next = 1
|
led_reg.next = 1
|
led_low.next = 1
|
led_low.next = 1
|
imem_data_out.next = 0
|
imem_data_out.next = 0
|
imem_sel_out.next = 0
|
imem_sel_out.next = 0
|
read_en.next = False
|
read_en.next = False
|
uart_rxd.next = 1
|
uart_rxd.next = 1
|
read_en2.next = False
|
read_en2.next = False
|
uart_rxd2.next = 1
|
uart_rxd2.next = 1
|
count.next = 0
|
count.next = 0
|
else:
|
else:
|
txd_line.next = uart_txd
|
txd_line.next = uart_txd
|
uart_rxd.next = rxd_line
|
uart_rxd.next = rxd_line
|
txd_line2.next = uart_txd2
|
txd_line2.next = uart_txd2
|
uart_rxd2.next = rxd_line2
|
uart_rxd2.next = rxd_line2
|
read_en.next = False
|
read_en.next = False
|
count.next = (count+1)%(2**20)
|
count.next = (count+1)%(2**20)
|
if count == 0:
|
#if count == 0:
|
led_low.next = concat(led_low[31:], led_low[31])
|
#led_low.next = concat(led_low[31:], led_low[31])
|
|
|
#if write_en and not tx_busy:
|
#if write_en and not tx_busy:
|
#led_reg.next = concat(led_reg[31:], led_reg[31])
|
#led_reg.next = concat(led_reg[31:], led_reg[31])
|
#if dmem_we_out and dmem_addr_out[28:] == 0xFFFFFB0:
|
if dmem_we_out and dmem_addr_out[28:] == 0xFFFFFB0:
|
#led_reg.next = dmem_data_out
|
led_reg.next = dmem_data_out
|
#else:
|
else:
|
#led_reg.next = led_reg
|
led_reg.next = led_reg
|
#led_reg.next = concat(dmem_ena_in, dmem_we_out, dmem_ena_out,
|
#led_reg.next = concat(dmem_ena_in, dmem_we_out, dmem_ena_out,
|
#write_en,)
|
#write_en,)
|
if imem_addr_out == 0x244:
|
#if imem_addr_out == 0x244:
|
led_reg.next = 0xff
|
#led_reg.next = 0xff
|
|
|
|
|
@always_comb
|
@always_comb
|
def debug_output():
|
def debug_output():
|
debug_dmem_ena_in.next = dmem_ena_in
|
debug_dmem_ena_in.next = dmem_ena_in
|
debug_dmem_data_in.next = dmem_data_in
|
debug_dmem_data_in.next = dmem_data_in
|
debug_dmem_data_out.next = dmem_data_out
|
debug_dmem_data_out.next = dmem_data_out
|
debug_dmem_sel_out.next = dmem_sel_out
|
debug_dmem_sel_out.next = dmem_sel_out
|
debug_dmem_we_out.next = dmem_we_out
|
debug_dmem_we_out.next = dmem_we_out
|
debug_dmem_addr_out.next = dmem_addr_out
|
debug_dmem_addr_out.next = dmem_addr_out
|
debug_dmem_ena_out.next = dmem_ena_out
|
debug_dmem_ena_out.next = dmem_ena_out
|
debug_dmem_ena.next = dmem_ena
|
debug_dmem_ena.next = dmem_ena
|
|
|
debug_imem_data_in.next = imem_data_in
|
debug_imem_data_in.next = imem_data_in
|
debug_imem_data_out.next = imem_data_out
|
debug_imem_data_out.next = imem_data_out
|
debug_imem_sel_out.next = imem_sel_out
|
debug_imem_sel_out.next = imem_sel_out
|
debug_imem_we_out.next = imem_we_out
|
debug_imem_we_out.next = imem_we_out
|
debug_imem_addr_out.next = imem_addr_out
|
debug_imem_addr_out.next = imem_addr_out
|
debug_imem_ena.next = imem_ena
|
debug_imem_ena.next = imem_ena
|
debug_imem_ena_out.next = imem_ena_out
|
debug_imem_ena_out.next = imem_ena_out
|
|
|
return instances()
|
if DEBUG:
|
|
return imem, dmem, core, uart, uart2, glue, run, debug_output
|
|
|
|
return imem, dmem, core, uart, uart2, glue, run
|
|
|
import sys
|
import sys
|
from numpy import log2
|
from numpy import log2
|
|
|
def TopBench():
|
def TopBench():
|
prepare()
|
prepare()
|
size = int(log2(int(sys.argv[1]))) if len(sys.argv) > 1 else 4
|
size = int(log2(int(sys.argv[1]))) if len(sys.argv) > 1 else 4
|
print 'size=%s' % size
|
print 'size=%s' % size
|
|
|
txd_line = Signal(False)
|
txd_line = Signal(False)
|
rxd_line = Signal(False)
|
rxd_line = Signal(False)
|
txd_line2 = Signal(False)
|
txd_line2 = Signal(False)
|
rxd_line2 = Signal(False)
|
rxd_line2 = Signal(False)
|
leds = Signal(intbv(0)[8:])
|
leds = Signal(intbv(0)[8:])
|
reset = Signal(False)
|
reset = Signal(False)
|
clock = Signal(False)
|
clock = Signal(False)
|
|
|
|
|
debug_if_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
debug_if_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
|
|
debug_gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_gprf_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_gprf_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_gprf_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
|
|
debug_of_alu_op = Signal(alu_operation.ALU_ADD)
|
debug_of_alu_op = Signal(alu_operation.ALU_ADD)
|
debug_of_alu_src_a = Signal(src_type_a.REGA)
|
debug_of_alu_src_a = Signal(src_type_a.REGA)
|
debug_of_alu_src_b = Signal(src_type_b.REGB)
|
debug_of_alu_src_b = Signal(src_type_b.REGB)
|
debug_of_branch_cond = Signal(branch_condition.NOP)
|
debug_of_branch_cond = Signal(branch_condition.NOP)
|
debug_of_carry = Signal(carry_type.C_ZERO)
|
debug_of_carry = Signal(carry_type.C_ZERO)
|
debug_of_carry_keep = Signal(False)
|
debug_of_carry_keep = Signal(False)
|
debug_of_delay = Signal(False)
|
debug_of_delay = Signal(False)
|
debug_of_hazard = Signal(False)
|
debug_of_hazard = Signal(False)
|
debug_of_immediate = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_of_immediate = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_of_instruction = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
debug_of_instruction = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
debug_of_mem_read = Signal(False)
|
debug_of_mem_read = Signal(False)
|
debug_of_mem_write = Signal(False)
|
debug_of_mem_write = Signal(False)
|
debug_of_operation = Signal(False)
|
debug_of_operation = Signal(False)
|
debug_of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
debug_of_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
debug_of_reg_a = Signal(intbv(0)[5:])
|
debug_of_reg_a = Signal(intbv(0)[5:])
|
debug_of_reg_b = Signal(intbv(0)[5:])
|
debug_of_reg_b = Signal(intbv(0)[5:])
|
debug_of_reg_d = Signal(intbv(0)[5:])
|
debug_of_reg_d = Signal(intbv(0)[5:])
|
debug_of_reg_write = Signal(False)
|
debug_of_reg_write = Signal(False)
|
debug_of_transfer_size = Signal(transfer_size_type.WORD)
|
debug_of_transfer_size = Signal(transfer_size_type.WORD)
|
|
|
# Write back stage forwards
|
# Write back stage forwards
|
debug_of_fwd_mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_of_fwd_mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_of_fwd_reg_d = Signal(intbv(0)[5:])
|
debug_of_fwd_reg_d = Signal(intbv(0)[5:])
|
debug_of_fwd_reg_write = Signal(False)
|
debug_of_fwd_reg_write = Signal(False)
|
|
|
debug_ex_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_reg_d = Signal(intbv(0)[5:])
|
debug_ex_reg_d = Signal(intbv(0)[5:])
|
debug_ex_reg_write = Signal(False)
|
debug_ex_reg_write = Signal(False)
|
|
|
debug_ex_branch = Signal(False)
|
debug_ex_branch = Signal(False)
|
debug_ex_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_dat_d = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_flush_id = Signal(False)
|
debug_ex_flush_id = Signal(False)
|
debug_ex_mem_read = Signal(False)
|
debug_ex_mem_read = Signal(False)
|
debug_ex_mem_write = Signal(False)
|
debug_ex_mem_write = Signal(False)
|
debug_ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
debug_ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
debug_ex_transfer_size = Signal(transfer_size_type.WORD)
|
debug_ex_transfer_size = Signal(transfer_size_type.WORD)
|
|
|
debug_ex_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_dat_a = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_dat_b = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_instruction = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_ex_reg_a = Signal(intbv(0)[5:])
|
debug_ex_reg_a = Signal(intbv(0)[5:])
|
debug_ex_reg_b = Signal(intbv(0)[5:])
|
debug_ex_reg_b = Signal(intbv(0)[5:])
|
|
|
debug_mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_mm_mem_read = Signal(False)
|
debug_mm_mem_read = Signal(False)
|
debug_mm_reg_d = Signal(intbv(0)[5:])
|
debug_mm_reg_d = Signal(intbv(0)[5:])
|
debug_mm_reg_write = Signal(False)
|
debug_mm_reg_write = Signal(False)
|
debug_mm_transfer_size = Signal(transfer_size_type.WORD)
|
debug_mm_transfer_size = Signal(transfer_size_type.WORD)
|
|
|
debug_dmem_ena_in = Signal(False)
|
debug_dmem_ena_in = Signal(False)
|
debug_dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_dmem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_dmem_data_out = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_dmem_sel_out = Signal(intbv(0)[4:])
|
debug_dmem_sel_out = Signal(intbv(0)[4:])
|
debug_dmem_we_out = Signal(False)
|
debug_dmem_we_out = Signal(False)
|
debug_dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
|
debug_dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
|
debug_dmem_ena_out = Signal(False)
|
debug_dmem_ena_out = Signal(False)
|
debug_dmem_ena = Signal(False)
|
debug_dmem_ena = Signal(False)
|
|
|
debug_imem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_imem_data_in = Signal(intbv(0)[CFG_DMEM_WIDTH:])
|
debug_imem_data_out = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
debug_imem_data_out = Signal(intbv(0)[CFG_IMEM_WIDTH:])
|
debug_imem_sel_out = Signal(intbv(0)[4:])
|
debug_imem_sel_out = Signal(intbv(0)[4:])
|
debug_imem_we_out = Signal(False)
|
debug_imem_we_out = Signal(False)
|
debug_imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
debug_imem_addr_out = Signal(intbv(0)[CFG_IMEM_SIZE:])
|
debug_imem_ena = Signal(True)
|
debug_imem_ena = Signal(True)
|
debug_imem_ena_out = Signal(False)
|
debug_imem_ena_out = Signal(False)
|
|
|
top = SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
|
top = SysTop(txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock,
|
|
|
# if __debug__:
|
# Ports only for debug
|
debug_if_program_counter,
|
debug_if_program_counter,
|
|
|
debug_of_alu_op,
|
debug_of_alu_op,
|
debug_of_alu_src_a,
|
debug_of_alu_src_a,
|
debug_of_alu_src_b,
|
debug_of_alu_src_b,
|
debug_of_branch_cond,
|
debug_of_branch_cond,
|
debug_of_carry,
|
debug_of_carry,
|
debug_of_carry_keep,
|
debug_of_carry_keep,
|
debug_of_delay,
|
debug_of_delay,
|
debug_of_hazard,
|
debug_of_hazard,
|
debug_of_immediate,
|
debug_of_immediate,
|
debug_of_instruction,
|
debug_of_instruction,
|
debug_of_mem_read,
|
debug_of_mem_read,
|
debug_of_mem_write,
|
debug_of_mem_write,
|
debug_of_operation,
|
debug_of_operation,
|
debug_of_program_counter,
|
debug_of_program_counter,
|
debug_of_reg_a,
|
debug_of_reg_a,
|
debug_of_reg_b,
|
debug_of_reg_b,
|
debug_of_reg_d,
|
debug_of_reg_d,
|
debug_of_reg_write,
|
debug_of_reg_write,
|
debug_of_transfer_size,
|
debug_of_transfer_size,
|
|
|
debug_of_fwd_mem_result,
|
debug_of_fwd_mem_result,
|
debug_of_fwd_reg_d,
|
debug_of_fwd_reg_d,
|
debug_of_fwd_reg_write,
|
debug_of_fwd_reg_write,
|
|
|
debug_gprf_dat_a,
|
debug_gprf_dat_a,
|
debug_gprf_dat_b,
|
debug_gprf_dat_b,
|
debug_gprf_dat_d,
|
debug_gprf_dat_d,
|
|
|
debug_ex_alu_result,
|
debug_ex_alu_result,
|
debug_ex_reg_d,
|
debug_ex_reg_d,
|
debug_ex_reg_write,
|
debug_ex_reg_write,
|
|
|
debug_ex_branch,
|
debug_ex_branch,
|
debug_ex_dat_d,
|
debug_ex_dat_d,
|
debug_ex_flush_id,
|
debug_ex_flush_id,
|
debug_ex_mem_read,
|
debug_ex_mem_read,
|
debug_ex_mem_write,
|
debug_ex_mem_write,
|
debug_ex_program_counter,
|
debug_ex_program_counter,
|
debug_ex_transfer_size,
|
debug_ex_transfer_size,
|
|
|
debug_ex_dat_a,
|
debug_ex_dat_a,
|
debug_ex_dat_b,
|
debug_ex_dat_b,
|
debug_ex_instruction,
|
debug_ex_instruction,
|
debug_ex_reg_a,
|
debug_ex_reg_a,
|
debug_ex_reg_b,
|
debug_ex_reg_b,
|
|
|
debug_mm_alu_result,
|
debug_mm_alu_result,
|
debug_mm_mem_read,
|
debug_mm_mem_read,
|
debug_mm_reg_d,
|
debug_mm_reg_d,
|
debug_mm_reg_write,
|
debug_mm_reg_write,
|
debug_mm_transfer_size,
|
debug_mm_transfer_size,
|
|
|
debug_dmem_ena_in,
|
debug_dmem_ena_in,
|
debug_dmem_data_in,
|
debug_dmem_data_in,
|
debug_dmem_data_out,
|
debug_dmem_data_out,
|
debug_dmem_sel_out,
|
debug_dmem_sel_out,
|
debug_dmem_we_out,
|
debug_dmem_we_out,
|
debug_dmem_addr_out,
|
debug_dmem_addr_out,
|
debug_dmem_ena_out,
|
debug_dmem_ena_out,
|
debug_dmem_ena,
|
debug_dmem_ena,
|
|
|
debug_imem_data_in,
|
debug_imem_data_in,
|
debug_imem_data_out,
|
debug_imem_data_out,
|
debug_imem_sel_out,
|
debug_imem_sel_out,
|
debug_imem_we_out,
|
debug_imem_we_out,
|
debug_imem_addr_out,
|
debug_imem_addr_out,
|
debug_imem_ena,
|
debug_imem_ena,
|
debug_imem_ena_out,
|
debug_imem_ena_out,
|
|
|
size=size)
|
size=size)
|
|
|
@instance
|
@instance
|
def clockgen():
|
def clockgen():
|
yield delay(10)
|
yield delay(10)
|
clock.next = False
|
clock.next = False
|
while 1:
|
while 1:
|
yield delay(10)
|
yield delay(10)
|
clock.next = not clock
|
clock.next = not clock
|
|
|
@instance
|
@instance
|
def stimulus():
|
def stimulus():
|
reset.next = False
|
reset.next = False
|
yield delay(37)
|
yield delay(37)
|
reset.next = True
|
reset.next = True
|
yield delay(53)
|
yield delay(53)
|
reset.next = False
|
reset.next = False
|
for i in range(2000):
|
for i in range(3000):
|
yield clock.negedge
|
yield clock.negedge
|
reset.next = False
|
reset.next = False
|
yield delay(37)
|
yield delay(37)
|
reset.next = True
|
reset.next = True
|
yield delay(53)
|
yield delay(53)
|
reset.next = False
|
reset.next = False
|
for i in range(2000):
|
for i in range(3000):
|
yield clock.negedge
|
yield clock.negedge
|
|
|
raise StopSimulation
|
raise StopSimulation
|
|
|
@instance
|
@instance
|
def monitor():
|
def monitor():
|
while 1:
|
while 1:
|
yield clock.posedge
|
yield clock.posedge
|
#if debug_dmem_ena_in:
|
#if debug_dmem_ena_in:
|
#print '%x' % debug_ex_program_counter
|
#print '%x' % debug_ex_program_counter
|
|
|
#if debug_ex_program_counter == 0x0:
|
#if debug_ex_program_counter == 0x0:
|
#print 'reach the start 00000000'
|
#print 'reach the start 00000000'
|
#if debug_ex_program_counter == 0x244:
|
#if debug_ex_program_counter == 0x244:
|
#print 'reach the second xil_print call'
|
#print 'reach the second xil_print call'
|
if debug_dmem_addr_out == 0xffffffc0:
|
if debug_dmem_addr_out == 0xffffffc0:
|
#if debug_dmem_sel_out == 0b1000:
|
#if debug_dmem_sel_out == 0b1000:
|
if debug_dmem_we_out:
|
if debug_dmem_we_out:
|
#sys.stdout.write(chr(int(debug_dmem_data_out[8:])))
|
sys.stdout.write(chr(int(debug_dmem_data_out[8:])))
|
#sys.stdout.flush()
|
sys.stdout.flush()
|
print int(debug_dmem_data_out[8:])
|
#print int(debug_dmem_data_out[8:])
|
#print 'output: %d' % debug_dmem_data_out[8:]
|
#print 'output: %d' % debug_dmem_data_out[8:]
|
|
|
|
|
|
|
|
|
#print 'if_pc: %x\timem_addr: %x\treset: %x' % (
|
#print 'if_pc: %x\timem_addr: %x\treset: %x' % (
|
#debug_if_program_counter, debug_imem_addr_out, reset
|
#debug_if_program_counter, debug_imem_addr_out, reset
|
#)
|
#)
|
#print ('of_pc: %x\tof_instruction:%x'
|
#print ('of_pc: %x\tof_instruction:%x'
|
##'\tbranch_cond:%s\talu_op:%s'
|
##'\tbranch_cond:%s\talu_op:%s'
|
#'\thazard:%x') % (
|
#'\thazard:%x') % (
|
#debug_of_program_counter, debug_of_instruction,
|
#debug_of_program_counter, debug_of_instruction,
|
##debug_of_branch_cond, debug_of_alu_op,
|
##debug_of_branch_cond, debug_of_alu_op,
|
#debug_of_hazard,
|
#debug_of_hazard,
|
#)
|
#)
|
#print 'ex_pc: %x\tex_instruction:%x' % (
|
#print 'ex_pc: %x\tex_instruction:%x' % (
|
#debug_ex_program_counter,
|
#debug_ex_program_counter,
|
#debug_ex_instruction,
|
#debug_ex_instruction,
|
#)
|
#)
|
#print 'Ra: r%d=%x\tRb: r%d=%x\t-> Rd:%d\tdat_d:%x\talu_result: %x\tbranch: %x' % (
|
#print 'Ra: r%d=%x\tRb: r%d=%x\t-> Rd:%d\tdat_d:%x\talu_result: %x\tbranch: %x' % (
|
#debug_ex_reg_a, debug_ex_dat_a,
|
#debug_ex_reg_a, debug_ex_dat_a,
|
#debug_ex_reg_b, debug_ex_dat_b,
|
#debug_ex_reg_b, debug_ex_dat_b,
|
#debug_ex_reg_d, debug_ex_dat_d,
|
#debug_ex_reg_d, debug_ex_dat_d,
|
#debug_ex_alu_result,
|
#debug_ex_alu_result,
|
#debug_ex_branch,
|
#debug_ex_branch,
|
#)
|
#)
|
#print 'ex_mem_read %s ex_mem_write %s' % (
|
#print 'ex_mem_read %s ex_mem_write %s' % (
|
#debug_ex_mem_read, debug_ex_mem_write)
|
#debug_ex_mem_read, debug_ex_mem_write)
|
#print ''
|
#print ''
|
|
|
|
|
|
|
|
|
#if enable and not ex_r_flush_ex: # and (ex_comb_r_reg_write
|
#if enable and not ex_r_flush_ex: # and (ex_comb_r_reg_write
|
##or ex_comb_mem_read or ex_comb_mem_write): # and DEBUG_VERBOSE:
|
##or ex_comb_mem_read or ex_comb_mem_write): # and DEBUG_VERBOSE:
|
##if DEBUG_VERBOSE:
|
##if DEBUG_VERBOSE:
|
#print 'EX:',
|
#print 'EX:',
|
#dissembly(of_program_counter,
|
#dissembly(of_program_counter,
|
#of_instruction,
|
#of_instruction,
|
#ex_comb_r_reg_d,
|
#ex_comb_r_reg_d,
|
#of_reg_a,
|
#of_reg_a,
|
#of_reg_b,
|
#of_reg_b,
|
#ex_comb_dat_d,
|
#ex_comb_dat_d,
|
#ex_comb_dat_a,
|
#ex_comb_dat_a,
|
#ex_comb_dat_b,
|
#ex_comb_dat_b,
|
#ex_comb_r_alu_result,
|
#ex_comb_r_alu_result,
|
#True)
|
#True)
|
#print "\t",of_alu_op, of_alu_src_a, of_alu_src_b, of_immediate.signed()
|
#print "\t",of_alu_op, of_alu_src_a, of_alu_src_b, of_immediate.signed()
|
#print "\treg_write:=%s mem_read:=%s mem_write:=%s branch:=%s flush_ex:=%s" % (
|
#print "\treg_write:=%s mem_read:=%s mem_write:=%s branch:=%s flush_ex:=%s" % (
|
#ex_comb_r_reg_write,ex_comb_mem_read,ex_comb_mem_write,
|
#ex_comb_r_reg_write,ex_comb_mem_read,ex_comb_mem_write,
|
#ex_comb_branch, ex_comb_r_flush_ex)
|
#ex_comb_branch, ex_comb_r_flush_ex)
|
#print ''
|
#print ''
|
#if of_program_counter == 0x244:
|
#if of_program_counter == 0x244:
|
#raw_input()
|
#raw_input()
|
|
|
|
|
return instances()
|
return instances()
|
|
|
if __name__ == '__main__':
|
if __name__ == '__main__':
|
if 1:
|
if 0:
|
#tb = traceSignals(TopBench)
|
tb = traceSignals(TopBench)
|
#Simulation(tb).run()
|
Simulation(tb).run()
|
conversion.verify.simulator = 'icarus'
|
#conversion.verify.simulator = 'icarus'
|
conversion.verify(TopBench)
|
#conversion.verify(TopBench)
|
else:
|
else:
|
prepare()
|
prepare()
|
txd_line = Signal(False)
|
txd_line = Signal(False)
|
rxd_line = Signal(False)
|
rxd_line = Signal(False)
|
txd_line2 = Signal(False)
|
txd_line2 = Signal(False)
|
rxd_line2 = Signal(False)
|
rxd_line2 = Signal(False)
|
leds = Signal(intbv(0)[8:])
|
leds = Signal(intbv(0)[8:])
|
reset = Signal(False)
|
reset = Signal(False)
|
clock = Signal(False)
|
clock = Signal(False)
|
size = int(log2(int(sys.argv[1]))) if len(sys.argv) > 1 else 4
|
size = int(log2(int(sys.argv[1]))) if len(sys.argv) > 1 else 4
|
print 'size=%s' % size
|
print 'size=%s' % size
|
#toVHDL(uart_test_top, txd_line, rxd_line, leds, reset, clock)
|
#toVHDL(uart_test_top, txd_line, rxd_line, leds, reset, clock)
|
toVerilog(SysTop, txd_line, rxd_line, txd_line2, rxd_line2, leds, reset, clock, size=size)
|
toVerilog(SysTop, txd_line, rxd_line, txd_line2, rxd_line2, leds, reset,
|
|
clock, size=size, DEBUG=False)
|
|
|
|
|
|
|
### EOF ###
|
### EOF ###
|
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
|
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
|
|
|
|
|