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-- Title : ONFI compliant NAND interface
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-- Title : ONFI compliant NAND interface
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-- File : io_unit.vhd
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-- File : io_unit.vhd
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-- Author : Alexey Lyashko <pradd@opencores.org>
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-- Author : Alexey Lyashko <pradd@opencores.org>
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-- License : LGPL
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-- License : LGPL
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-- Description:
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-- Description:
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-- This file implements data IO unit of the controller.
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-- This file implements data IO unit of the controller.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.onfi.all;
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use work.onfi.all;
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entity io_unit is
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entity io_unit is
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generic (io_type : io_t);
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generic (io_type : io_t);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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activate : in std_logic;
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activate : in std_logic;
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data_in : in std_logic_vector(15 downto 0);
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data_in : in std_logic_vector(15 downto 0);
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io_ctrl : out std_logic := '1';
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io_ctrl : out std_logic := '1';
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data_out : out std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0);
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busy : out std_logic
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busy : out std_logic
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);
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);
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end io_unit;
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end io_unit;
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architecture action of io_unit is
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architecture action of io_unit is
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type io_state_t is (IO_IDLE, IO_HOLD, IO_DELAY);
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type io_state_t is (IO_IDLE, IO_HOLD, IO_DELAY);
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signal state : io_state_t := IO_IDLE;
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signal state : io_state_t := IO_IDLE;
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signal n_state : io_state_t := IO_IDLE;
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signal n_state : io_state_t := IO_IDLE;
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signal delay : integer := 0;
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signal delay : integer := 0;
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signal data_reg : std_logic_vector(15 downto 0);
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signal data_reg : std_logic_vector(15 downto 0);
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begin
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begin
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busy <= '1' when state /= IO_IDLE else
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busy <= '1' when state /= IO_IDLE else
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'0';
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'0';
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data_out <= data_reg when (io_type = IO_WRITE and state /= IO_IDLE) or
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data_out <= data_reg when (io_type = IO_WRITE and state /= IO_IDLE) or
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io_type = IO_READ else
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io_type = IO_READ else
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x"0000";
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x"0000";
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io_ctrl <= '0' when state = IO_DELAY and n_state = IO_HOLD else
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io_ctrl <= '0' when state = IO_DELAY and n_state = IO_HOLD else
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'1';
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'1';
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IO: process(clk, activate)
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IO: process(clk, activate)
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begin
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begin
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if(rising_edge(clk))then
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if(rising_edge(clk))then
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case state is
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case state is
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when IO_IDLE =>
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when IO_IDLE =>
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if(io_type = IO_WRITE)then
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if(io_type = IO_WRITE)then
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data_reg <= data_in;
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data_reg <= data_in;
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end if;
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end if;
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if(activate = '1')then
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if(activate = '1')then
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if(io_type = IO_WRITE)then
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if(io_type = IO_WRITE)then
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delay <= t_wp;
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delay <= t_wp;
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else
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else
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delay <= t_rea;
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delay <= t_rea;
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end if;
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end if;
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n_state <= IO_HOLD;
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n_state <= IO_HOLD;
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state <= IO_DELAY;
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state <= IO_DELAY;
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end if;
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end if;
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when IO_HOLD =>
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when IO_HOLD =>
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if(io_type = IO_WRITE)then
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if(io_type = IO_WRITE)then
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delay <= t_wh;
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delay <= t_wh;
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else
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else
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delay <= t_reh;
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delay <= t_reh;
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end if;
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end if;
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n_state <= IO_IDLE;
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n_state <= IO_IDLE;
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state <= IO_DELAY;
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state <= IO_DELAY;
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when IO_DELAY =>
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when IO_DELAY =>
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if(delay > 1)then
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if(delay > 1)then
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delay <= delay - 1;
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delay <= delay - 1;
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else
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if(delay = 2 and io_type = IO_READ)then
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if(io_type = IO_READ and n_state = IO_IDLE)then
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data_reg <= data_in;
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data_reg <= data_in; -- This thing needs to be checked with read hardware. Assignment may be needed somewhat earlier.
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end if;
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end if;
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else
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-- if(io_type = IO_READ and n_state = IO_IDLE)then
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-- data_reg <= data_in; -- This thing needs to be checked with real hardware. Assignment may be needed somewhat earlier.
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-- end if;
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state <= n_state;
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state <= n_state;
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end if;
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end if;
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when others =>
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when others =>
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state <= IO_IDLE;
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state <= IO_IDLE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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