--##############################################################################
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--##############################################################################
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--
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--
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-- InstructionDecoder
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-- InstructionDecoder
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-- Instriction decoder
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-- Instriction decoder
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--
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--
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-- Provides different parts of the instruction word to differnent blocks.
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-- Provides different parts of the instruction word to differnent blocks.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Versions / Authors
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-- Versions / Authors
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-- 1.0 Francois Corthay first implementation
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-- 1.0 Francois Corthay first implementation
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--
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--
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-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html>
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-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html>
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--
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--
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-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
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-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
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-- <http://www.hevs.ch/en/rad-instituts/institut-systemes-industriels/>.
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-- <http://www.hevs.ch/en/rad-instituts/institut-systemes-industriels/>.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Hierarchy
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-- Hierarchy
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-- Used by "nanoblaze/nanoProcessor".
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-- Used by "nanoblaze/nanoProcessor".
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--
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--
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--##############################################################################
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--##############################################################################
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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USE ieee.numeric_std.all;
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|
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ENTITY instructionDecoder IS
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ENTITY instructionDecoder IS
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GENERIC(
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GENERIC(
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registerBitNb : positive := 8;
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registerBitNb : positive := 8;
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registerAddressBitNb : positive := 4;
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registerAddressBitNb : positive := 4;
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aluCodeBitNb : positive := 5;
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aluCodeBitNb : positive := 5;
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instructionBitNb : positive := 18;
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instructionBitNb : positive := 18;
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programCounterBitNb : positive := 10;
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programCounterBitNb : positive := 10;
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opCodeBitNb : positive := 5;
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opCodeBitNb : positive := 5;
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branchCondBitNb : positive := 3;
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branchCondBitNb : positive := 3;
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intCodeBitNb : positive := 5;
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intCodeBitNb : positive := 5;
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spadAddressBitNb : natural := 4;
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spadAddressBitNb : natural := 4;
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portAddressBitNb : positive := 8
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portAddressBitNb : positive := 8
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);
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);
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PORT(
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PORT(
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instruction : IN std_ulogic_vector(instructionBitNb-1 DOWNTO 0);
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instruction : IN std_ulogic_vector(instructionBitNb-1 DOWNTO 0);
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aluCode : OUT std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
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aluCode : OUT std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
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addrA : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
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addrA : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
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addrB : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
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addrB : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
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instrData : OUT signed(registerBitNb-1 DOWNTO 0);
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instrData : OUT signed(registerBitNb-1 DOWNTO 0);
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instrAddress : OUT unsigned(programCounterBitNb-1 DOWNTO 0);
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instrAddress : OUT unsigned(programCounterBitNb-1 DOWNTO 0);
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opCode : OUT std_ulogic_vector(opCodeBitNb-1 DOWNTO 0);
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opCode : OUT std_ulogic_vector(opCodeBitNb-1 DOWNTO 0);
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twoRegInstr : OUT std_ulogic;
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twoRegInstr : OUT std_ulogic;
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branchCond : OUT std_ulogic_vector(branchCondBitNb-1 DOWNTO 0);
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branchCond : OUT std_ulogic_vector(branchCondBitNb-1 DOWNTO 0);
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intCode : OUT std_ulogic_vector(intCodeBitNb-1 DOWNTO 0);
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intCode : OUT std_ulogic_vector(intCodeBitNb-1 DOWNTO 0);
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portIndexedSel : OUT std_ulogic;
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portIndexedSel : OUT std_ulogic;
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portAddress : OUT unsigned(portAddressBitNb-1 DOWNTO 0);
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portAddress : OUT unsigned(portAddressBitNb-1 DOWNTO 0);
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spadIndexedSel : OUT std_ulogic;
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spadIndexedSel : OUT std_ulogic;
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spadAddress : OUT unsigned(spadAddressBitNb-1 DOWNTO 0)
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spadAddress : OUT unsigned(spadAddressBitNb-1 DOWNTO 0)
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);
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);
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END instructionDecoder ;
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END instructionDecoder ;
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--==============================================================================
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--==============================================================================
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ARCHITECTURE RTL OF instructionDecoder IS
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ARCHITECTURE RTL OF instructionDecoder IS
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|
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constant opCodeIndexH : integer := instruction'high;
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constant opCodeIndexH : integer := instruction'high;
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constant opCodeIndexL : integer := opCodeIndexH - opCodeBitNb + 1;
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constant opCodeIndexL : integer := opCodeIndexH - opCodeBitNb + 1;
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constant twoRegInstrIndex : integer := opCodeIndexL - 1;
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constant twoRegInstrIndex : integer := opCodeIndexL - 1;
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constant ioAddrIndexed : integer := twoRegInstrIndex;
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constant ioAddrIndexed : integer := twoRegInstrIndex;
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|
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constant addrAIndexH : integer := twoRegInstrIndex - 1;
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constant addrAIndexH : integer := twoRegInstrIndex - 1;
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constant addrAIndexL : integer := addrAIndexH - registerAddressBitNb + 1;
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constant addrAIndexL : integer := addrAIndexH - registerAddressBitNb + 1;
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constant immediateDataIndexH : integer := registerBitNb-1;
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constant immediateDataIndexH : integer := registerBitNb-1;
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constant immediateDataIndexL : integer := 0;
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constant immediateDataIndexL : integer := 0;
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constant addrBIndexH : integer := addrAIndexL - 1;
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constant addrBIndexH : integer := addrAIndexL - 1;
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constant addrBIndexL : integer := addrBIndexH - registerAddressBitNb + 1;
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constant addrBIndexL : integer := addrBIndexH - registerAddressBitNb + 1;
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constant aluCodeIndexH : integer := opCodeIndexH;
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constant aluCodeIndexH : integer := opCodeIndexH;
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constant aluCodeIndexL : integer := aluCodeIndexH - aluCodeBitNb + 1;
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constant aluCodeIndexL : integer := aluCodeIndexH - aluCodeBitNb + 1;
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constant portAddressH : integer := registerBitNb-1;
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constant portAddressH : integer := registerBitNb-1;
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constant portAddressL : integer := portAddressH-portAddressBitNb+1;
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constant portAddressL : integer := portAddressH-portAddressBitNb+1;
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constant spadAddressH : integer := registerBitNb-1;
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constant spadAddressH : integer := registerBitNb-1;
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constant spadAddressL : integer := spadAddressH-spadAddressBitNb+1;
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constant spadAddressL : integer := spadAddressH-spadAddressBitNb+1;
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constant branchCondH : integer := opCodeIndexL-1;
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constant branchCondH : integer := opCodeIndexL-1;
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constant branchCondL : integer := branchCondH-branchCondBitNb+1;
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constant branchCondL : integer := branchCondH-branchCondBitNb+1;
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BEGIN
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BEGIN
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- ALU control
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-- ALU control
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aluCode <=
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aluCode <=
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instruction(aluCodeIndexH downto aluCodeIndexL)
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instruction(aluCodeIndexH downto aluCodeIndexL)
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when instruction(aluCodeIndexH) = '0' else
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when instruction(aluCodeIndexH) = '0' else
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'1' & instruction(aluCodeBitNb-2 downto 0);
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'1' & instruction(aluCodeBitNb-2 downto 0);
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opCode <= instruction(opCodeIndexH downto opCodeIndexL);
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opCode <= instruction(opCodeIndexH downto opCodeIndexL);
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twoRegInstr <= instruction(twoRegInstrIndex);
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twoRegInstr <= instruction(twoRegInstrIndex);
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addrA <= unsigned(instruction(addrAIndexH downto addrAIndexL));
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addrA <= unsigned(instruction(addrAIndexH downto addrAIndexL));
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addrB <= unsigned(instruction(addrBIndexH downto addrBIndexL));
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addrB <= unsigned(instruction(addrBIndexH downto addrBIndexL));
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instrData <= signed(instruction(immediateDataIndexH downto immediateDataIndexL));
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instrData <= signed(instruction(immediateDataIndexH downto immediateDataIndexL));
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- I/O control
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-- I/O control
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portIndexedSel <= instruction(ioAddrIndexed);
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portIndexedSel <= instruction(ioAddrIndexed);
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portAddress <= unsigned(instruction(portAddressH downto portAddressL));
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portAddress <= unsigned(instruction(portAddressH downto portAddressL));
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- scratchpad control
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-- scratchpad control
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spadIndexedSel <= instruction(ioAddrIndexed);
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spadIndexedSel <= instruction(ioAddrIndexed);
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spadAddress <= unsigned(instruction(spadAddressH downto spadAddressL));
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spadAddress <= unsigned(instruction(spadAddressH downto spadAddressL));
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|
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- branch control
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-- branch control
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branchCond <= instruction(branchCondH downto branchCondL);
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branchCond <= instruction(branchCondH downto branchCondL);
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instrAddress <= unsigned(instruction(instrAddress'range));
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instrAddress <= unsigned(instruction(instrAddress'range));
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END ARCHITECTURE RTL;
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END ARCHITECTURE RTL;
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