//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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//
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//
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// This file is part of the Next186 project
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// This file is part of the Next186 project
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// http://opencores.org/project,next186
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// http://opencores.org/project,next186
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//
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//
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// Filename: Next186_BIU_2T_delayread.v
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// Filename: Next186_BIU_2T_delayread.v
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// Description: Part of the Next186 CPU project, bus interface unit
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// Description: Part of the Next186 CPU project, bus interface unit
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// Version 1.0
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// Version 1.0
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// Creation date: 20Jan2012 - 10Mar2012
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// Creation date: 20Jan2012 - 10Mar2012
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//
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//
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// Author: Nicolae Dumitrache
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// Author: Nicolae Dumitrache
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// e-mail: ndumitrache@opencores.org
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// e-mail: ndumitrache@opencores.org
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//
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//
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2012 Nicolae Dumitrache
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// Copyright (C) 2012 Nicolae Dumitrache
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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// Additional Comments:
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// Additional Comments:
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//
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//
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// - Links the CPU with a 32bit static synchronous RAM (or cache)
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// - Links the CPU with a 32bit static synchronous RAM (or cache)
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// - Able to address up to 1MB
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// - Able to address up to 1MB
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// - 16byte instruction queue
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// - 16byte instruction queue
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// - Works at 2 X CPU frequency (80Mhz on Spartan3AN), requiring minimum 2T for an instruction.
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// - Works at 2 X CPU frequency (80Mhz on Spartan3AN), requiring minimum 2T for an instruction.
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// - The 32bit data bus and the double CPU clock allows the instruction queue to be almost always full, avoiding the CPU starving.
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// - The 32bit data bus and the double CPU clock allows the instruction queue to be almost always full, avoiding the CPU starving.
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// The data un-alignement penalties are required only when data words crosses the 4byte boundaries.
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// The data un-alignement penalties are required only when data words crosses the 4byte boundaries.
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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//
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//
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// How to compute each instruction duration, in clock cycles (for this particular BIU implementation!):
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// How to compute each instruction duration, in clock cycles (for this particular BIU implementation!):
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//
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//
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// 1 - From the Next186_features.doc see for each instruction how many T states are required (you will notice they are always
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// 1 - From the Next186_features.doc see for each instruction how many T states are required (you will notice they are always
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// less or equal than 486 and much less than the original 80186
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// less or equal than 486 and much less than the original 80186
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// 2 - Multiply this number by 2 - the BIU works at double ALU frequency because it needs to multiplex the data and instructions,
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// 2 - Multiply this number by 2 - the BIU works at double ALU frequency because it needs to multiplex the data and instructions,
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// in order to keep the ALU permanently feed with instructions. The 16bit queue acts like a flexible instruction buffer.
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// in order to keep the ALU permanently feed with instructions. The 16bit queue acts like a flexible instruction buffer.
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// 3 - Add penalties, as follows:
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// 3 - Add penalties, as follows:
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// +1T for each memory read - because of the synchronous SRAM which need this extra cycle to deliver the data
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// +1T for each memory read - because of the synchronous SRAM which need this extra cycle to deliver the data
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// +2T for each jump - required to flush and re-fill the instruction queue
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// +2T for each jump - required to flush and re-fill the instruction queue
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// +1T for each 16bit(word) read/write which overlaps the 4byte boundary - specific to 32bit bus width
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// +1T for each 16bit(word) read/write which overlaps the 4byte boundary - specific to 32bit bus width
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// +1T if the jump is made at an address with the latest 2bits 11 - specific to 32bit bus width
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// +1T if the jump is made at an address with the latest 2bits 11 - specific to 32bit bus width
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// +1T when the instruction queue empties - this case appears very rare, when a lot of 5-6 bytes memory write instructions are executed in direct sequence
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// +1T when the instruction queue empties - this case appears very rare, when a lot of 5-6 bytes memory write instructions are executed in direct sequence
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//
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//
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// Some examples:
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// Some examples:
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// - "lea ax,[bx+si+1234]" requires 2T
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// - "lea ax,[bx+si+1234]" requires 2T
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// - "add ax, 2345" requires 2T
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// - "add ax, 2345" requires 2T
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// - "xchg ax, bx" requires 4T
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// - "xchg ax, bx" requires 4T
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// - "inc word ptr [1]" requires 5T (2x2T inc M + 1T read)
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// - "inc word ptr [1]" requires 5T (2x2T inc M + 1T read)
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// - "inc word ptr [3]" requires 7T (2x2T inc M + 1T read + 1T unaligned read + 1T unaligned write)
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// - "inc word ptr [3]" requires 7T (2x2T inc M + 1T read + 1T unaligned read + 1T unaligned write)
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// - "imul ax,bx,234" requires 4T (2x2T imul)
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// - "imul ax,bx,234" requires 4T (2x2T imul)
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// - "loop address != 3(mod 4)" requires 4T (2x1T loop + 2T flush)
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// - "loop address != 3(mod 4)" requires 4T (2x1T loop + 2T flush)
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// - "loop address == 3(mod 4)" requires 5T (2x1T loop + 2T flush + 1T unaligned jump)
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// - "loop address == 3(mod 4)" requires 5T (2x1T loop + 2T flush + 1T unaligned jump)
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// - "call address 0" requires 4T (2x1T call near + 2T flush
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// - "call address 0" requires 4T (2x1T call near + 2T flush
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// - "ret address 0" requires 7T (2x2T ret + 1T read penalty + 2T flush)
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// - "ret address 0" requires 7T (2x2T ret + 1T read penalty + 2T flush)
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module BIU186_32bSync_2T_DelayRead(
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module BIU186_32bSync_2T_DelayRead(
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input CLK,
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input CLK,
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output [47:0]INSTR,
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output [47:0]INSTR,
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input [2:0]ISIZE,
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input [2:0]ISIZE,
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input IFETCH,
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input IFETCH,
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input FLUSH,
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input FLUSH,
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input MREQ,
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input MREQ,
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input WR,
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input WR,
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input WORD,
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input WORD,
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input [20:0]ADDR,
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input [20:0]ADDR,
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input [20:0]IADDR,
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input [20:0]IADDR,
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output reg CE186, // CPU clock enable
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output reg CE186, // CPU clock enable
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input [31:0]RAM_DIN,
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input [31:0]RAM_DIN,
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output [31:0]RAM_DOUT,
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output [31:0]RAM_DOUT,
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output [18:0]RAM_ADDR,
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output [18:0]RAM_ADDR,
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output RAM_MREQ,
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output RAM_MREQ,
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output wire[3:0]RAM_WMASK,
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output wire[3:0]RAM_WMASK,
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output reg [15:0]DOUT,
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output reg [15:0]DOUT,
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input [15:0]DIN,
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input [15:0]DIN,
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input CE, // BIU clock enable
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input CE, // BIU clock enable
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output reg data_bound,
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output reg data_bound,
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input [1:0]WSEL, // normally {~ADDR[0], ADDR[0]}
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input [1:0]WSEL, // normally {~ADDR[0], ADDR[0]}
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output reg RAM_RD,
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output reg RAM_RD,
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output reg RAM_WR
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output reg RAM_WR,
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input IORQ,
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input FASTIO
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);
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);
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reg [31:0]queue[3:0];
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reg [31:0]queue[3:0];
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reg [1:0]STATE = 0;
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reg [1:0]STATE = 0;
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reg OLDSTATE = 1;
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reg OLDSTATE = 1;
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reg [3:0]qpos = 0;
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reg [3:0]qpos = 0;
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reg [4:0]qsize = 0;
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reg [4:0]qsize = 0;
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reg [1:0]rpos = 0;
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reg [1:0]rpos = 0;
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reg [18:0]piaddr = 0;
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reg [18:0]piaddr = 0;
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reg [7:0]exdata = 0;
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reg [7:0]exdata = 0;
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reg rdi = 0;
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reg rdi = 0;
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reg [1:0]NEXTSTATE;
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reg [1:0]NEXTSTATE;
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reg sflush;
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reg sflush;
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wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;
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wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;
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wire qnofull = qsize < 13;
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wire qnofull = qsize < 13;
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reg iread;// = (qnofull && !RAM_RD && !RAM_WR) || sflush;
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reg iread;// = (qnofull && !RAM_RD && !RAM_WR) || sflush;
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wire [3:0]nqpos = (FLUSH && IFETCH) ? {2'b00, IADDR[1:0]} : (qpos + ISIZE);
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wire [3:0]nqpos = (FLUSH && IFETCH) ? {2'b00, IADDR[1:0]} : (qpos + ISIZE);
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wire [18:0]MIADDR = sflush ? IADDR[20:2] : piaddr;
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wire [18:0]MIADDR = sflush ? IADDR[20:2] : piaddr;
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wire split = (&ADDR[1:0]) && WORD; // data between dwords
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wire split = (&ADDR[1:0]) && WORD; // data between dwords
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wire [15:0]DSWAP = {WSEL[1] ? DIN[15:8] : DIN[7:0], WSEL[0] ? DIN[15:8] : DIN[7:0]}; //ADDR[0] ? {DIN[7:0], DIN[15:8]} : DIN;
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wire [15:0]DSWAP = {WSEL[1] ? DIN[15:8] : DIN[7:0], WSEL[0] ? DIN[15:8] : DIN[7:0]}; //ADDR[0] ? {DIN[7:0], DIN[15:8]} : DIN;
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wire [1:0]a1 = nqpos[3:2] + 1;
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wire [1:0]a1 = nqpos[3:2] + 1;
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wire [1:0]a2 = nqpos[3:2] + 2;
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wire [1:0]a2 = nqpos[3:2] + 2;
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wire [31:0]q1 = rdi && (a1 == rpos) ? RAM_DIN : queue[a1];
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wire [31:0]q1 = rdi && (a1 == rpos) ? RAM_DIN : queue[a1];
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wire [7:0]q2 = rdi && (a2 == rpos) ? RAM_DIN[7:0] : queue[a2][7:0];
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wire [7:0]q2 = rdi && (a2 == rpos) ? RAM_DIN[7:0] : queue[a2][7:0];
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assign INSTR = {q2, q1, queue[nqpos[3:2]]} >> {nqpos[1:0], 3'b000};
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assign INSTR = {q2, q1, queue[nqpos[3:2]]} >> {nqpos[1:0], 3'b000};
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// assign DOUT = split ? {RAM_DIN[7:0], exdata} : (RAM_DIN >> {ADDR[1:0], 3'b000});
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// assign DOUT = split ? {RAM_DIN[7:0], exdata} : (RAM_DIN >> {ADDR[1:0], 3'b000});
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assign RAM_DOUT = {DSWAP, DSWAP};
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assign RAM_DOUT = {DSWAP, DSWAP};
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assign RAM_MREQ = iread || RAM_RD || RAM_WR;
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assign RAM_MREQ = iread || RAM_RD || RAM_WR;
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assign RAM_ADDR = iread ? MIADDR : ADDR[20:2] + data_bound;
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assign RAM_ADDR = iread ? MIADDR : ADDR[20:2] + data_bound;
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assign RAM_WMASK = data_bound ? {3'b000, RAM_WR} : {2'b00, WORD & RAM_WR, RAM_WR} << ADDR[1:0];
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assign RAM_WMASK = data_bound ? {3'b000, RAM_WR} : {2'b00, WORD & RAM_WR, RAM_WR} << ADDR[1:0];
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always @(*) begin
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always @(*) begin
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RAM_RD = 0;
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RAM_RD = 0;
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RAM_WR = 0;
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RAM_WR = 0;
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CE186 = 0;
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CE186 = 0;
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sflush = 0;
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sflush = 0;
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data_bound = 0;
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data_bound = 0;
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iread = 0;
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iread = 0;
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case(ADDR[1:0])
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case(ADDR[1:0])
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2'b00: DOUT = RAM_DIN[15:0];
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2'b00: DOUT = RAM_DIN[15:0];
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2'b01: DOUT = RAM_DIN[23:8];
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2'b01: DOUT = RAM_DIN[23:8];
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2'b10: DOUT = RAM_DIN[31:16];
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2'b10: DOUT = RAM_DIN[31:16];
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2'b11: DOUT = {RAM_DIN[7:0], WORD ? exdata : RAM_DIN[31:24]};
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2'b11: DOUT = {RAM_DIN[7:0], WORD ? exdata : RAM_DIN[31:24]};
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endcase
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endcase
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case(STATE)
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case(STATE)
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0: begin // no cpu activity on first state
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0: begin // no cpu activity on first state
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iread = qnofull;
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iread = qnofull;
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NEXTSTATE = 1;
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NEXTSTATE = 1;
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end
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end
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1: begin
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1: begin
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NEXTSTATE = 1;
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NEXTSTATE = 1;
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if(FLUSH && IFETCH && !OLDSTATE) begin
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if(FLUSH && IFETCH && !OLDSTATE) begin
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sflush = 1;
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sflush = 1;
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iread = 1;
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iread = 1;
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end else if((FLUSH && IFETCH && (qsize > 5)) || (qsize > 11)) begin
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end else if((FLUSH && IFETCH && (qsize > 5)) || (qsize > 11)) begin
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NEXTSTATE = 0;
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NEXTSTATE = 0;
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if(MREQ) begin
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if(MREQ) begin
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if(WR) begin // write
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if(WR) begin // write
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RAM_WR = 1;
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RAM_WR = 1;
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if(split) NEXTSTATE = 3;
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if(split) NEXTSTATE = 3;
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else CE186 = 1;
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else CE186 = 1;
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end else begin
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end else begin
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RAM_RD = 1;
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RAM_RD = 1;
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NEXTSTATE = split ? 2 : 3;
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NEXTSTATE = split ? 2 : 3;
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end
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end
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end else begin
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end else begin
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iread = qnofull;
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iread = qnofull;
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CE186 = 1;
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if(IORQ && !WR && !FASTIO) NEXTSTATE = 3;
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else CE186 = 1;
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end
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end
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end else iread = 1; // else nextstate = 1
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end else iread = 1; // else nextstate = 1
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end
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end
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2: begin
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2: begin
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RAM_RD = 1;
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RAM_RD = 1;
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data_bound = 1; // split memory access
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data_bound = 1; // split memory access
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NEXTSTATE = 3;
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NEXTSTATE = 3;
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end
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end
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3: begin
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3: begin
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RAM_WR = WR && MREQ;
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RAM_WR = WR && MREQ;
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iread = !(WR && MREQ) && qnofull;
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iread = !(WR && MREQ) && qnofull;
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data_bound = split;
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data_bound = split;
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CE186 = 1;
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CE186 = 1;
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NEXTSTATE = 0;
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NEXTSTATE = 0;
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end
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end
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endcase
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endcase
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end
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end
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always @ (posedge CLK) if(CE) begin
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always @ (posedge CLK) if(CE) begin
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rdi <= iread;
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rdi <= iread;
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if(rdi) queue[rpos] <= RAM_DIN;
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if(rdi) queue[rpos] <= RAM_DIN;
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if(iread) begin
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if(iread) begin
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qsize <= {newqsize[4:2] + 1, newqsize[1:0]};
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qsize <= {newqsize[4:2] + 1, newqsize[1:0]};
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piaddr <= MIADDR + 1;
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piaddr <= MIADDR + 1;
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end else begin
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end else begin
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qsize <= newqsize;
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qsize <= newqsize;
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piaddr <= MIADDR;
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piaddr <= MIADDR;
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end
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end
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if(CE186 && IFETCH) qpos <= nqpos;
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if(CE186 && IFETCH) qpos <= nqpos;
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if(sflush) rpos <= 0;
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if(sflush) rpos <= 0;
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else if(rdi) rpos <= rpos + 1;
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else if(rdi) rpos <= rpos + 1;
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OLDSTATE <= STATE[0];
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OLDSTATE <= STATE[0];
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STATE <= NEXTSTATE;
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STATE <= NEXTSTATE;
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if(data_bound) exdata <= RAM_DIN[31:24];
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if(data_bound) exdata <= RAM_DIN[31:24];
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end
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end
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endmodule
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endmodule
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