//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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//
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//
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// This file is part of the Next186 project
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// This file is part of the Next186 project
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// http://opencores.org/project,next186
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// http://opencores.org/project,next186
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//
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//
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// Filename: Next186_Regs.v
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// Filename: Next186_Regs.v
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// Description: Part of the Next186 CPU project, registers module
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// Description: Part of the Next186 CPU project, registers module
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// Version 1.0
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// Version 1.0
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// Creation date: 11Apr2011 - 07Jun2011
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// Creation date: 11Apr2011 - 07Jun2011
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//
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//
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// Author: Nicolae Dumitrache
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// Author: Nicolae Dumitrache
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// e-mail: ndumitrache@opencores.org
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// e-mail: ndumitrache@opencores.org
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//
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//
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2011 Nicolae Dumitrache
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// Copyright (C) 2011 Nicolae Dumitrache
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_Regs(
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module Next186_Regs(
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input [2:0]RASEL,
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input [2:0]RASEL,
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input [2:0]RBSEL,
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input [2:0]RBSEL,
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input BASEL,
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input BASEL,
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input [1:0]BBSEL,
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input [1:0]BBSEL,
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input [1:0]RSSEL,
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input [1:0]RSSEL,
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input [15:0]DIN,
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input [15:0]DIN,
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input [15:0]ALUOUT,
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input [15:0]ALUOUT,
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input [15:0]ADDR16,
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input [15:0]ADDR16,
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input [15:0]DIMM,
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input [15:0]DIMM,
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input [4:0]WE, // 4=flags, 3=TMP16, 2=RSSEL, 1=RASEL_HI, 0=RASEL_LO
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input [4:0]WE, // 4=flags, 3=TMP16, 2=RSSEL, 1=RASEL_HI, 0=RASEL_LO
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input IFETCH,
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input IFETCH,
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input [15:0]FIN,
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input [15:0]FIN,
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input [1:0]DISEL,
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input [1:0]DISEL,
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input [15:0]IPIN,
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input [15:0]IPIN,
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input WORD,
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input WORD,
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input INCSP,
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input INCSP,
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input DECCX,
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input DECCX,
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input DIVOP,
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input DIVOP,
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input DIVEND,
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input DIVEND,
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input DIVC,
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input DIVC,
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input DIVSGN,
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input DIVSGN,
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output [1:0]CXZ,
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output [1:0]CXZ,
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output [15:0]FOUT,
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output [15:0]FOUT,
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output [15:0]RA,
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output [15:0]RA,
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output [15:0]RB,
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output [15:0]RB,
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output reg [15:0]TMP16,
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output reg [15:0]TMP16,
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output reg [15:0]SP,
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output reg [15:0]SP,
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output reg [15:0]IP,
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output reg [15:0]IP,
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output reg [15:0]AX,
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output reg [15:0]AX,
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output reg [15:0]BX,
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output reg [15:0]BX,
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output reg [15:0]BP,
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output reg [15:0]BP,
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output reg [15:0]SI,
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output reg [15:0]SI,
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output reg [15:0]DI,
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output reg [15:0]DI,
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output [15:0]RS,
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output [15:0]RS,
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output [15:0]CS,
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output [15:0]CS,
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output reg [15:0]DX,
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output reg [15:0]DX,
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output DIVEXC,
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output DIVEXC,
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input CLK,
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input CLK,
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input CLKEN
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input CLKEN
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);
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);
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reg [15:0]CX;
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reg [15:0]CX;
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reg [15:0]SREG[3:0];
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reg [15:0]SREG[3:0];
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reg [8:0]FLG;
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reg [8:0]FLG;
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reg [15:0]REG_ASEL;
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reg [15:0]REG_ASEL;
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reg [15:0]REG_BSEL;
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reg [15:0]REG_BSEL;
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wire [15:0]RW = DISEL[0] ? ALUOUT : ADDR16; // x1=ALU, 10=ADDR, 00=DIN
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wire [15:0]RW = DISEL[0] ? ALUOUT : ADDR16; // x1=ALU, 10=ADDR, 00=DIN
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wire [2:0]ASEL = {WORD & RASEL[2], RASEL[1:0]};
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wire [2:0]ASEL = {WORD & RASEL[2], RASEL[1:0]};
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wire [2:0]BSEL = {WORD & RBSEL[2], RBSEL[1:0]};
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wire [2:0]BSEL = {WORD & RBSEL[2], RBSEL[1:0]};
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wire [7:0]RWHI = WORD || &WE[1:0] ? RW[15:8] : RW[7:0];
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wire [7:0]RWHI = WORD || &WE[1:0] ? RW[15:8] : RW[7:0];
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wire [8:0]RWDL = {DIVOP && ~DIVC ? DX[7:0] : RW[7:0], AX[15]};
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wire [8:0]RWDL = {DIVOP && ~DIVC ? DX[7:0] : RW[7:0], AX[15]};
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wire [8:0]RWDH = {DIVOP && ~DIVC ? DX[15:7] : {RWHI, RW[7]}};
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wire [8:0]RWDH = {DIVOP && ~DIVC ? DX[15:7] : {RWHI, RW[7]}};
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wire [8:0]RWAH = {DIVOP && ~DIVC ? AX[15:8] : RWHI, AX[7]};
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wire [8:0]RWAH = {DIVOP && ~DIVC ? AX[15:8] : RWHI, AX[7]};
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assign DIVEXC = WORD ? RWDH[8] : RWAH[8];
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assign DIVEXC = WORD ? RWDH[8] : RWAH[8];
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wire FASTDIN = ~|DISEL;
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wire FASTDIN = ~|DISEL;
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wire [15:0]FDRW = FASTDIN ? DIN : RW;
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wire [15:0]FDRW = FASTDIN ? DIN : RW;
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wire [7:0]FASTDINH = WORD || &WE[1:0] ? DIN[15:8] : DIN[7:0]; // fast data path for AH/DH (tweak for speed)
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wire [7:0]FASTDINH = WORD || &WE[1:0] ? DIN[15:8] : DIN[7:0]; // fast data path for AH/DH (tweak for speed)
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wire [15:0]CXM1 = CX + 16'hffff;
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wire [15:0]CXM1 = CX + 16'hffff;
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assign FOUT = {4'b0000, FLG[8:3], 1'b0, FLG[2], 1'b0, FLG[1], 1'b1, FLG[0]};
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assign FOUT = {4'b0000, FLG[8:3], 1'b0, FLG[2], 1'b0, FLG[1], 1'b1, FLG[0]};
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assign CS = SREG[1];
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assign CS = SREG[1];
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assign CXZ = {|CX[15:1], CX[0]};
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assign CXZ = {|CX[15:1], CX[0]};
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wire [15:0]RA1 = {REG_ASEL[15:8], WORD | !RASEL[2] ? REG_ASEL[7:0] : REG_ASEL[15:8]};
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wire [15:0]RA1 = {REG_ASEL[15:8], WORD | !RASEL[2] ? REG_ASEL[7:0] : REG_ASEL[15:8]};
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assign RA = BASEL ? RA1 : TMP16;
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assign RA = BASEL ? RA1 : TMP16;
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assign RB = BBSEL[1] ? BBSEL[0] ? SREG[BSEL[1:0]] : DIMM : BBSEL[0] ? {REG_BSEL[15:8], WORD | !RBSEL[2] ? REG_BSEL[7:0] : REG_BSEL[15:8]} : TMP16;
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assign RB = BBSEL[1] ? BBSEL[0] ? SREG[BSEL[1:0]] : DIMM : BBSEL[0] ? {REG_BSEL[15:8], WORD | !RBSEL[2] ? REG_BSEL[7:0] : REG_BSEL[15:8]} : TMP16;
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assign RS = SREG[RSSEL];
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assign RS = SREG[RSSEL];
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always @* begin
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always @* begin
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case(ASEL)
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case(ASEL)
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0: REG_ASEL = AX;
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0: REG_ASEL = AX;
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1: REG_ASEL = CX;
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1: REG_ASEL = CX;
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2: REG_ASEL = DX;
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2: REG_ASEL = DX;
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3: REG_ASEL = BX;
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3: REG_ASEL = BX;
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4: REG_ASEL = SP;
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4: REG_ASEL = SP;
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5: REG_ASEL = BP;
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5: REG_ASEL = BP;
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6: REG_ASEL = SI;
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6: REG_ASEL = SI;
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7: REG_ASEL = DI;
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7: REG_ASEL = DI;
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endcase
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endcase
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case(BSEL)
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case(BSEL)
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0: REG_BSEL = AX;
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0: REG_BSEL = AX;
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1: REG_BSEL = CX;
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1: REG_BSEL = CX;
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2: REG_BSEL = DX;
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2: REG_BSEL = DX;
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3: REG_BSEL = BX;
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3: REG_BSEL = BX;
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4: REG_BSEL = SP;
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4: REG_BSEL = SP;
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5: REG_BSEL = BP;
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5: REG_BSEL = BP;
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6: REG_BSEL = SI;
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6: REG_BSEL = SI;
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7: REG_BSEL = DI;
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7: REG_BSEL = DI;
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endcase
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endcase
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end
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end
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/*
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BUFG BUFG_inst (
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.O(CLKD), // Clock buffer output
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.I(CLK) // Clock buffer input
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);
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*/
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always @(posedge CLK)
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always @(posedge CLK)
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if(CLKEN) begin
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if(CLKEN) begin
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if(WE[0] && ASEL == 0) AX[7:0] <= FDRW[7:0];
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if(WE[0] && ASEL == 0) AX[7:0] <= FDRW[7:0];
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else if(DIVOP) AX[7:0] <= {AX[6:0], DIVC ^ DIVSGN};
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else if(DIVOP) AX[7:0] <= {AX[6:0], DIVC ^ DIVSGN};
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if(WE[1] && ASEL == 0) AX[15:8] <= FASTDIN ? FASTDINH : (DIVOP && ~DIVEND ? RWAH[7:0] : RWAH[8:1]);
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if(WE[1] && ASEL == 0) AX[15:8] <= FASTDIN ? FASTDINH : (DIVOP && ~DIVEND ? RWAH[7:0] : RWAH[8:1]);
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else if(DIVOP) AX[15:8] <= AX[14:7];
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else if(DIVOP) AX[15:8] <= AX[14:7];
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if(WE[0] && ASEL == 1) CX[7:0] <= FDRW[7:0];
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if(WE[0] && ASEL == 1) CX[7:0] <= FDRW[7:0];
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else if(DECCX) CX[7:0] <= CXM1[7:0];
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else if(DECCX) CX[7:0] <= CXM1[7:0];
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if(WE[1] && ASEL == 1) CX[15:8] <= FASTDIN ? FASTDINH : RWHI;
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if(WE[1] && ASEL == 1) CX[15:8] <= FASTDIN ? FASTDINH : RWHI;
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else if(DECCX) CX[15:8] <= CXM1[15:8];
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else if(DECCX) CX[15:8] <= CXM1[15:8];
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if(WE[0] && ASEL == 2) DX[7:0] <= FASTDIN ? DIN[7:0] : (DIVOP && ~DIVEND ? RWDL[7:0] : RWDL[8:1]);
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if(WE[0] && ASEL == 2) DX[7:0] <= FASTDIN ? DIN[7:0] : (DIVOP && ~DIVEND ? RWDL[7:0] : RWDL[8:1]);
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if(WE[1] && ASEL == 2) DX[15:8] <= FASTDIN ? FASTDINH : (DIVOP && ~DIVEND ? RWDH[7:0] : RWDH[8:1]);
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if(WE[1] && ASEL == 2) DX[15:8] <= FASTDIN ? FASTDINH : (DIVOP && ~DIVEND ? RWDH[7:0] : RWDH[8:1]);
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if(WE[0] && ASEL == 3) BX[7:0] <= FDRW[7:0];
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if(WE[0] && ASEL == 3) BX[7:0] <= FDRW[7:0];
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if(WE[1] && ASEL == 3) BX[15:8] <= FASTDIN ? FASTDINH : RWHI;
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if(WE[1] && ASEL == 3) BX[15:8] <= FASTDIN ? FASTDINH : RWHI;
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if(WE[0] && ASEL == 4) SP <= FDRW;
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if(WE[0] && ASEL == 4) SP <= FDRW;
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else if(INCSP) SP <= ADDR16;
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else if(INCSP) SP <= ADDR16;
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if(WE[0] && ASEL == 5) BP <= FDRW;
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if(WE[0] && ASEL == 5) BP <= FDRW;
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if(WE[0] && ASEL == 6) SI <= FDRW;
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if(WE[0] && ASEL == 6) SI <= FDRW;
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if(WE[0] && ASEL == 7) DI <= FDRW;
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if(WE[0] && ASEL == 7) DI <= FDRW;
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if(WE[2])
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if(WE[2])
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case(RASEL[1:0])
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case(RASEL[1:0])
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0: SREG[0] <= FDRW;
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0: SREG[0] <= FDRW;
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1: SREG[1] <= FDRW;
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1: SREG[1] <= FDRW;
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2: SREG[2] <= FDRW;
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2: SREG[2] <= FDRW;
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3: SREG[3] <= FDRW;
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3: SREG[3] <= FDRW;
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endcase
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endcase
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if(WE[3]) TMP16 <= |WE[1:0] ? (&DISEL[1:0] ? DIN : ADDR16) : FDRW; // TMP16
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if(WE[3]) TMP16 <= |WE[1:0] ? (&DISEL[1:0] ? DIN : ADDR16) : FDRW; // TMP16
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else TMP16 <= RA; // XCHG, MUL
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else TMP16 <= RA; // XCHG, MUL
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if(WE[4]) FLG <= {FIN[11:6], FIN[4], FIN[2], FIN[0]}; // FLAGS
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if(WE[4]) FLG <= {FIN[11:6], FIN[4], FIN[2], FIN[0]}; // FLAGS
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if(IFETCH) IP <= IPIN; // IP
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if(IFETCH) IP <= IPIN; // IP
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end
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end
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endmodule
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endmodule
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