/*
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/*
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Distributed under the MIT licesnse.
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Distributed under the MIT licesnse.
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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SOFTWARE.
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*/
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*/
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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//XXX: NOTE: All counts are 24bits long, this could be a parameter in the future
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//XXX: NOTE: All counts are 24bits long, this could be a parameter in the future
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module ppfifo
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module ppfifo
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#(parameter DATA_WIDTH = 8,
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#(parameter DATA_WIDTH = 8,
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ADDRESS_WIDTH = 4
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ADDRESS_WIDTH = 4
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)(
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)(
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//universal input
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//universal input
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input reset,
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input reset,
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//write side
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//write side
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input write_clock,
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input write_clock,
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output reg [1:0] write_ready,
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output reg [1:0] write_ready,
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input [1:0] write_activate,
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input [1:0] write_activate,
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output [23:0] write_fifo_size,
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output [23:0] write_fifo_size,
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input write_strobe,
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input write_strobe,
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input [DATA_WIDTH - 1: 0] write_data,
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input [DATA_WIDTH - 1: 0] write_data,
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output starved,
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output starved,
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//read side
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//read side
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input read_clock,
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input read_clock,
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input read_strobe,
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input read_strobe,
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output reg read_ready,
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output reg read_ready,
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input read_activate,
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input read_activate,
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output reg [23:0] read_count,
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output reg [23:0] read_count,
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output [DATA_WIDTH - 1: 0] read_data,
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output [DATA_WIDTH - 1: 0] read_data,
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output inactive
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output inactive
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);
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);
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localparam FIFO_DEPTH = (1 << ADDRESS_WIDTH);
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localparam FIFO_DEPTH = (1 << ADDRESS_WIDTH);
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//Local Registers/Wires
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//Local Registers/Wires
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//Write Side
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//Write Side
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wire ppfifo_ready; // The write side only needs to
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wire ppfifo_ready; // The write side only needs to
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// know were ready if we don't
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// know were ready if we don't
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// write anything read won't start
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// write anything read won't start
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wire [ADDRESS_WIDTH: 0] addr_in; // Actual address to the BRAM
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wire [ADDRESS_WIDTH: 0] addr_in; // Actual address to the BRAM
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reg [ADDRESS_WIDTH - 1: 0]write_address;
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reg [ADDRESS_WIDTH - 1: 0]write_address;
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reg r_wselect; // Select the FIFO to work with
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reg r_wselect; // Select the FIFO to work with
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reg write_enable; // Enable a write to the BRAM
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reg write_enable; // Enable a write to the BRAM
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reg [1:0] wcc_read_ready;// Tell read side a FIFO is ready
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reg [1:0] wcc_read_ready;// Tell read side a FIFO is ready
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wire [1:0] wcc_read_done;
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wire [1:0] wcc_read_done;
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// write status of the read
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// write status of the read
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// available
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// available
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reg wcc_tie_select; //because it's possible if the read
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reg wcc_tie_select; //because it's possible if the read
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//side is slower than the write
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//side is slower than the write
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//side it might be unknown which
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//side it might be unknown which
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//side was selected first, so use
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//side was selected first, so use
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//this signal to break ties
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//this signal to break ties
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reg [23:0] w_count[1:0]; // save the write count for the read
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reg [23:0] w_count[1:0]; // save the write count for the read
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// side
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// side
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reg w_empty[1:0];
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reg w_empty[1:0];
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reg w_reset; //write side reset
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reg w_reset; //write side reset
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reg [4:0] w_reset_timeout;
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reg [4:0] w_reset_timeout;
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wire ready;
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wire ready;
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//Read Side
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//Read Side
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wire [ADDRESS_WIDTH: 0] addr_out; //Actual address to the BRAM
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wire [ADDRESS_WIDTH: 0] addr_out; //Actual address to the BRAM
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reg r_reset;
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reg r_reset;
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reg [4:0] r_reset_timeout;
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reg [4:0] r_reset_timeout;
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reg [ADDRESS_WIDTH - 1: 0]r_address; //Address to access a bank
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reg [ADDRESS_WIDTH - 1: 0]r_address; //Address to access a bank
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reg r_rselect; //Select a bank (Select a FIFO)
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reg r_rselect; //Select a bank (Select a FIFO)
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wire [1:0] rcc_read_ready;
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wire [1:0] rcc_read_ready;
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// Write side says X is ready
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// Write side says X is ready
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reg [1:0] rcc_read_done;// Tell write side X is ready
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reg [1:0] rcc_read_done;// Tell write side X is ready
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wire rcc_tie_select;
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wire rcc_tie_select;
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//If there is a tie, then this will
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//If there is a tie, then this will
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//break it
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//break it
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reg [23:0] r_size[1:0]; // Size of FX read
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reg [23:0] r_size[1:0]; // Size of FX read
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reg [1:0] r_ready; //FIFO is ready
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reg [1:0] r_ready; //FIFO is ready
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reg [1:0] r_wait; //Waiting for write side to send data
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reg [1:0] r_wait; //Waiting for write side to send data
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reg [1:0] r_activate; //Controls which FIFO is activated
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reg [1:0] r_activate; //Controls which FIFO is activated
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reg r_next_fifo; //If both FIFOs are availalbe use this
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reg r_next_fifo; //If both FIFOs are availalbe use this
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reg [1:0] r_pre_activate; //Used to delay the clock cycle by
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reg [1:0] r_pre_activate; //Used to delay the clock cycle by
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//one when the user activates the
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//one when the user activates the
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//FIFO
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//FIFO
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reg r_pre_strobe;
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reg r_pre_strobe;
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reg r_pre_read_wait;//Wait an extra cycle so the registered data has a chance to set
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reg r_pre_read_wait;//Wait an extra cycle so the registered data has a chance to set
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//the data to be registered
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//the data to be registered
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wire [DATA_WIDTH - 1: 0] w_read_data; //data from the read FIFO
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wire [DATA_WIDTH - 1: 0] w_read_data; //data from the read FIFO
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reg [DATA_WIDTH - 1: 0] r_read_data; //data from the read FIFO
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reg [DATA_WIDTH - 1: 0] r_read_data; //data from the read FIFO
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//assign r_wselect = (write_activate == 2'b00) ? 1'b0 :
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//assign r_wselect = (write_activate == 2'b00) ? 1'b0 :
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// (write_activate == 2'b01) ? 1'b0 :
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// (write_activate == 2'b01) ? 1'b0 :
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// (write_activate == 2'b10) ? 1'b1 :
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// (write_activate == 2'b10) ? 1'b1 :
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// reset ? 1'b0 :
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// reset ? 1'b0 :
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// r_wselect;
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// r_wselect;
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// //I know this can be shortened down but it's more
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// //I know this can be shortened down but it's more
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// //readible thi way
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// //readible thi way
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assign write_fifo_size = FIFO_DEPTH;
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assign write_fifo_size = FIFO_DEPTH;
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assign addr_in = {r_wselect, write_address};
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assign addr_in = {r_wselect, write_address};
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//assign write_enable = (write_activate > 0) && write_strobe;
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//assign write_enable = (write_activate > 0) && write_strobe;
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assign ppfifo_ready = !(w_reset || r_reset);
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assign ppfifo_ready = !(w_reset || r_reset);
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assign ready = ppfifo_ready;
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assign ready = ppfifo_ready;
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//assign wcc_tie_select = (wcc_read_ready == 2'b00) ? 1'b0 :
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//assign wcc_tie_select = (wcc_read_ready == 2'b00) ? 1'b0 :
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// (wcc_read_ready == 2'b01) ? 1'b0 :
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// (wcc_read_ready == 2'b01) ? 1'b0 :
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// (wcc_read_ready == 2'b10) ? 1'b1 :
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// (wcc_read_ready == 2'b10) ? 1'b1 :
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// wcc_tie_select;
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// wcc_tie_select;
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// If the first FIFO is ready,
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// If the first FIFO is ready,
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// then both FIFOs are ready then
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// then both FIFOs are ready then
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// keep the first FIFO
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// keep the first FIFO
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assign addr_out = {r_rselect, r_address};
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assign addr_out = {r_rselect, r_address};
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//Debug
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//Debug
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//wire [23:0] debug_f0_w_count;
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//wire [23:0] debug_f0_w_count;
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//wire [23:0] debug_f1_w_count;
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//wire [23:0] debug_f1_w_count;
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//wire [23:0] debug_f0_r_size;
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//wire [23:0] debug_f0_r_size;
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//wire [23:0] debug_f1_r_size;
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//wire [23:0] debug_f1_r_size;
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//wire [23:0] debug_f0_r_count;
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//wire [23:0] debug_f0_r_count;
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//wire [23:0] debug_f1_r_count;
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//wire [23:0] debug_f1_r_count;
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//assign debug_f0_w_count = w_count[0];
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//assign debug_f0_w_count = w_count[0];
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//assign debug_f1_w_count = w_count[1];
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//assign debug_f1_w_count = w_count[1];
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//assign debug_f0_r_size = r_size[0];
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//assign debug_f0_r_size = r_size[0];
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//assign debug_f1_r_size = r_size[1];
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//assign debug_f1_r_size = r_size[1];
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assign inactive = (w_count[0] == 0) &&
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assign inactive = (w_count[0] == 0) &&
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(w_count[1] == 0) &&
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(w_count[1] == 0) &&
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(write_ready == 2'b11) &&
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(write_ready == 2'b11) &&
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(!write_strobe);
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(!write_strobe);
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assign read_data = (r_pre_strobe) ? w_read_data : r_read_data;
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assign read_data = (r_pre_strobe) ? w_read_data : r_read_data;
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//Submodules
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//Submodules
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blk_mem #(
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blk_mem #(
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.DATA_WIDTH(DATA_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.ADDRESS_WIDTH(ADDRESS_WIDTH + 1)
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.ADDRESS_WIDTH(ADDRESS_WIDTH + 1)
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) fifo0 (
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) fifo0 (
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//Write
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//Write
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.clka (write_clock ),
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.clka (write_clock ),
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.wea (write_enable ), //This may just be replaced with write activate
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.wea (write_enable ), //This may just be replaced with write activate
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.dina (write_data ),
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.dina (write_data ),
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.addra (addr_in ),
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.addra (addr_in ),
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.clkb (read_clock ),
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.clkb (read_clock ),
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.doutb (w_read_data ),
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.doutb (w_read_data ),
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.addrb (addr_out )
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.addrb (addr_out )
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);
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);
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//W - R FIFO 0
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//W - R FIFO 0
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cross_clock_enable ccwf0 (
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cross_clock_enable ccwf0 (
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.rst (reset ),
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.rst (reset ),
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.in_en (wcc_read_ready[0] ),
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.in_en (wcc_read_ready[0] ),
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.out_clk (read_clock ),
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.out_clk (read_clock ),
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.out_en (rcc_read_ready[0] )
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.out_en (rcc_read_ready[0] )
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);
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);
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//W - R FIFO 1
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//W - R FIFO 1
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cross_clock_enable ccwf1 (
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cross_clock_enable ccwf1 (
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.rst (reset ),
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.rst (reset ),
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.in_en (wcc_read_ready[1] ),
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.in_en (wcc_read_ready[1] ),
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.out_clk (read_clock ),
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.out_clk (read_clock ),
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.out_en (rcc_read_ready[1] )
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.out_en (rcc_read_ready[1] )
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);
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);
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//W - R Tie Select
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//W - R Tie Select
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cross_clock_enable ccts (
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cross_clock_enable ccts (
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.rst (reset ),
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.rst (reset ),
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.in_en (wcc_tie_select ),
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.in_en (wcc_tie_select ),
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.out_clk (read_clock ),
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.out_clk (read_clock ),
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.out_en (rcc_tie_select )
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.out_en (rcc_tie_select )
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);
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);
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//R - W FIFO 0
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//R - W FIFO 0
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cross_clock_enable ccrf0 (
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cross_clock_enable ccrf0 (
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.rst (reset ),
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.rst (reset ),
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.in_en (rcc_read_done[0] ),
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.in_en (rcc_read_done[0] ),
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.out_clk (read_clock ),
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.out_clk (read_clock ),
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.out_en (wcc_read_done[0] )
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.out_en (wcc_read_done[0] )
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);
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);
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//R - W FIFO 1
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//R - W FIFO 1
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cross_clock_enable ccrf1 (
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cross_clock_enable ccrf1 (
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.rst (reset ),
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.rst (reset ),
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.in_en (rcc_read_done[1] ),
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.in_en (rcc_read_done[1] ),
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.out_clk (read_clock ),
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.out_clk (read_clock ),
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.out_en (wcc_read_done[1] )
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.out_en (wcc_read_done[1] )
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);
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);
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//R - W Reset
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//R - W Reset
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cross_clock_enable cc_starved(
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cross_clock_enable cc_starved(
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.rst (reset ),
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.rst (reset ),
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.in_en (!read_ready && !read_activate ),
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.in_en (!read_ready && !read_activate ),
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.out_clk (write_clock ),
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.out_clk (write_clock ),
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.out_en (starved )
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.out_en (starved )
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);
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);
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//asynchronous logic
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//asynchronous logic
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always @ (*) begin
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always @ (*) begin
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case (wcc_read_ready)
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case (wcc_read_ready)
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2'b00: begin
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2'b00: begin
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wcc_tie_select = 1'b0;
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wcc_tie_select = 1'b0;
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end
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end
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2'b01: begin
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2'b01: begin
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wcc_tie_select = 1'b0;
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wcc_tie_select = 1'b0;
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end
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end
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2'b10: begin
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2'b10: begin
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wcc_tie_select = 1'b1;
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wcc_tie_select = 1'b1;
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end
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end
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default: begin
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default: begin
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wcc_tie_select = 1'b0;
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wcc_tie_select = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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always @ (*) begin
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always @ (*) begin
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case (write_activate)
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case (write_activate)
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2'b00: begin
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2'b00: begin
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r_wselect = 1'b0;
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r_wselect = 1'b0;
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end
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end
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2'b01: begin
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2'b01: begin
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r_wselect = 1'b0;
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r_wselect = 1'b0;
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end
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end
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2'b10: begin
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2'b10: begin
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r_wselect = 1'b1;
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r_wselect = 1'b1;
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end
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end
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default: begin
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default: begin
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r_wselect = 1'b0;
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r_wselect = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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always @ (*) begin
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always @ (*) begin
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if (write_activate > 0 && write_strobe) begin
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if (write_activate > 0 && write_strobe) begin
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write_enable = 1'b1;
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write_enable = 1'b1;
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end
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end
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else begin
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else begin
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write_enable = 1'b0;
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write_enable = 1'b0;
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end
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end
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end
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end
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//synchronous logic
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//synchronous logic
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//Reset Logic
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//Reset Logic
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always @ (posedge write_clock) begin
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always @ (posedge write_clock) begin
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if (reset) begin
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if (reset) begin
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w_reset <= 1;
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w_reset <= 1;
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w_reset_timeout <= 0;
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w_reset_timeout <= 0;
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end
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end
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else begin
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else begin
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if (w_reset && (w_reset_timeout < 5'h4)) begin
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if (w_reset && (w_reset_timeout < 5'h4)) begin
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w_reset_timeout <= w_reset_timeout + 5'h1;
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w_reset_timeout <= w_reset_timeout + 5'h1;
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end
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end
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else begin
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else begin
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w_reset <= 0;
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w_reset <= 0;
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end
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end
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end
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end
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end
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end
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always @ (posedge read_clock) begin
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always @ (posedge read_clock) begin
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if (reset) begin
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if (reset) begin
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r_reset <= 1;
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r_reset <= 1;
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r_reset_timeout <= 0;
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r_reset_timeout <= 0;
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end
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end
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else begin
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else begin
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if (r_reset && (r_reset_timeout < 5'h4)) begin
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if (r_reset && (r_reset_timeout < 5'h4)) begin
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r_reset_timeout <= r_reset_timeout + 5'h1;
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r_reset_timeout <= r_reset_timeout + 5'h1;
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end
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end
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else begin
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else begin
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r_reset <= 0;
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r_reset <= 0;
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end
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end
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end
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end
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end
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end
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//---------------Write Side---------------
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//---------------Write Side---------------
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initial begin
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initial begin
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write_address = 0;
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write_address = 0;
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wcc_read_ready = 2'b00;
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wcc_read_ready = 2'b00;
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write_ready = 2'b00;
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write_ready = 2'b00;
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w_reset = 1;
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w_reset = 1;
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w_reset_timeout = 0;
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w_reset_timeout = 0;
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write_enable = 0;
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write_enable = 0;
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r_wselect = 0;
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r_wselect = 0;
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wcc_tie_select = 0;
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wcc_tie_select = 0;
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end
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end
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always @ (posedge write_clock) begin
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always @ (posedge write_clock) begin
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if (reset) begin
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if (reset) begin
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write_ready <= 0;
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write_ready <= 0;
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end
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end
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else if (ready) begin
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else if (ready) begin
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//Logic for the Write Enable
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//Logic for the Write Enable
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if (write_activate[0] && write_strobe) begin
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if (write_activate[0] && write_strobe) begin
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write_ready[0] <= 1'b0;
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write_ready[0] <= 1'b0;
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end
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end
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if (write_activate[1] && write_strobe) begin
|
if (write_activate[1] && write_strobe) begin
|
write_ready[1] <= 1'b0;
|
write_ready[1] <= 1'b0;
|
end
|
end
|
|
|
if (!write_activate[0] && (w_count[0] == 0) && wcc_read_done[0]) begin
|
if (!write_activate[0] && (w_count[0] == 0) && wcc_read_done[0]) begin
|
//FIFO 0 is not accessed by the read side, and user has not activated
|
//FIFO 0 is not accessed by the read side, and user has not activated
|
write_ready[0] <= 1;
|
write_ready[0] <= 1;
|
end
|
end
|
if (!write_activate[1] && (w_count[1] == 0) && wcc_read_done[1]) begin
|
if (!write_activate[1] && (w_count[1] == 0) && wcc_read_done[1]) begin
|
//FIFO 1 is not accessed by the read side, and user has not activated
|
//FIFO 1 is not accessed by the read side, and user has not activated
|
write_ready[1] <= 1;
|
write_ready[1] <= 1;
|
end
|
end
|
|
|
//When the user is finished reading the ready signal might go high
|
//When the user is finished reading the ready signal might go high
|
//I SHOULD MAKE A CONDITION WHERE THE WRITE COUND MUST BE 0
|
//I SHOULD MAKE A CONDITION WHERE THE WRITE COUND MUST BE 0
|
end
|
end
|
end
|
end
|
|
|
always @ (posedge write_clock) begin
|
always @ (posedge write_clock) begin
|
if (reset) begin //Asynchronous Reset
|
if (reset) begin //Asynchronous Reset
|
wcc_read_ready <= 2'b00;
|
wcc_read_ready <= 2'b00;
|
write_address <= 0;
|
write_address <= 0;
|
w_count[0] <= 24'h0;
|
w_count[0] <= 24'h0;
|
w_count[1] <= 24'h0;
|
w_count[1] <= 24'h0;
|
end
|
end
|
else begin
|
else begin
|
if (write_activate > 0 && write_strobe) begin
|
if (write_activate > 0 && write_strobe) begin
|
write_address <= write_address + 1;
|
write_address <= write_address + 1;
|
if (write_activate[0]) begin
|
if (write_activate[0]) begin
|
w_count[0] <= w_count[0] + 1;
|
w_count[0] <= w_count[0] + 1;
|
end
|
end
|
if (write_activate[1]) begin
|
if (write_activate[1]) begin
|
w_count[1] <= w_count[1] + 1;
|
w_count[1] <= w_count[1] + 1;
|
end
|
end
|
end
|
end
|
if (write_activate == 0) begin
|
if (write_activate == 0) begin
|
write_address <= 0;
|
write_address <= 0;
|
if (w_count[0] > 0) begin
|
if (w_count[0] > 0) begin
|
wcc_read_ready[0] <= 1;
|
wcc_read_ready[0] <= 1;
|
end
|
end
|
if (w_count[1] > 0) begin
|
if (w_count[1] > 0) begin
|
wcc_read_ready[1] <= 1;
|
wcc_read_ready[1] <= 1;
|
end
|
end
|
end
|
end
|
//I can't reset the w_count until the read side has indicated that it
|
//I can't reset the w_count until the read side has indicated that it
|
//is done but that may be mistriggered when the write side finishes
|
//is done but that may be mistriggered when the write side finishes
|
//a write. So how do
|
//a write. So how do
|
|
|
//Only reset the write count when the done signal has been de-asserted
|
//Only reset the write count when the done signal has been de-asserted
|
|
|
//Deassert w_readX_ready when we see the read has de-asserted r_readX_done
|
//Deassert w_readX_ready when we see the read has de-asserted r_readX_done
|
if (!wcc_read_done[0]) begin
|
if (!wcc_read_done[0]) begin
|
//Only reset write count when the read side has said it's busy so it
|
//Only reset write count when the read side has said it's busy so it
|
//must be done reading
|
//must be done reading
|
w_count[0] <= 0;
|
w_count[0] <= 0;
|
wcc_read_ready[0] <= 0;
|
wcc_read_ready[0] <= 0;
|
end
|
end
|
if (!wcc_read_done[1]) begin
|
if (!wcc_read_done[1]) begin
|
w_count[1] <= 0;
|
w_count[1] <= 0;
|
wcc_read_ready[1] <= 0;
|
wcc_read_ready[1] <= 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
//---------------Read Side---------------
|
//---------------Read Side---------------
|
initial begin
|
initial begin
|
r_rselect = 0;
|
r_rselect = 0;
|
r_address = 0;
|
r_address = 0;
|
|
|
rcc_read_done = 2'b00;
|
rcc_read_done = 2'b00;
|
|
|
r_size[0] = 24'h0;
|
r_size[0] = 24'h0;
|
r_size[1] = 24'h0;
|
r_size[1] = 24'h0;
|
|
|
r_wait = 2'b11;
|
r_wait = 2'b11;
|
r_ready = 2'b00;
|
r_ready = 2'b00;
|
r_activate = 2'b00;
|
r_activate = 2'b00;
|
r_pre_activate = 0;
|
r_pre_activate = 0;
|
|
|
r_next_fifo = 0;
|
r_next_fifo = 0;
|
r_reset = 1;
|
r_reset = 1;
|
r_reset_timeout = 0;
|
r_reset_timeout = 0;
|
read_ready = 0;
|
read_ready = 0;
|
r_read_data = 32'h0;
|
r_read_data = 32'h0;
|
r_pre_read_wait = 0;
|
r_pre_read_wait = 0;
|
end
|
end
|
|
|
always @ (posedge read_clock) begin
|
always @ (posedge read_clock) begin
|
if (reset) begin //Asynchronous Reset
|
if (reset) begin //Asynchronous Reset
|
r_rselect <= 0;
|
r_rselect <= 0;
|
r_address <= 0;
|
r_address <= 0;
|
rcc_read_done <= 2'b11;
|
rcc_read_done <= 2'b11;
|
read_count <= 0;
|
read_count <= 0;
|
r_activate <= 2'b00;
|
r_activate <= 2'b00;
|
r_pre_activate <= 2'b00;
|
r_pre_activate <= 2'b00;
|
r_pre_read_wait <= 0;
|
r_pre_read_wait <= 0;
|
|
|
r_size[0] <= 24'h0;
|
r_size[0] <= 24'h0;
|
r_size[1] <= 24'h0;
|
r_size[1] <= 24'h0;
|
|
|
//are these signals redundant?? can I just use the done?
|
//are these signals redundant?? can I just use the done?
|
r_wait <= 2'b11;
|
r_wait <= 2'b11;
|
|
|
r_ready <= 2'b00;
|
r_ready <= 2'b00;
|
|
|
r_next_fifo <= 0;
|
r_next_fifo <= 0;
|
r_read_data <= 0;
|
r_read_data <= 0;
|
|
read_ready <= 0;
|
|
|
end
|
end
|
else begin
|
else begin
|
r_pre_strobe <= read_strobe;
|
r_pre_strobe <= read_strobe;
|
//Handle user enable and ready
|
//Handle user enable and ready
|
if (!read_activate && !r_pre_activate) begin
|
if (!read_activate && !r_pre_activate) begin
|
//User has not activated the read side
|
//User has not activated the read side
|
|
|
//Prepare the read side
|
//Prepare the read side
|
//Reset the address
|
//Reset the address
|
if (r_activate == 0) begin
|
if (r_activate == 0) begin
|
read_count <= 0;
|
read_count <= 0;
|
r_address <= 0;
|
r_address <= 0;
|
r_pre_read_wait <= 0;
|
r_pre_read_wait <= 0;
|
if (r_ready > 0) begin
|
if (r_ready > 0) begin
|
//This goes to one instead of activate
|
//This goes to one instead of activate
|
//Output select
|
//Output select
|
//read_ready <= 1;
|
//read_ready <= 1;
|
|
|
if (r_ready[0] && r_ready[1]) begin
|
if (r_ready[0] && r_ready[1]) begin
|
//$display ("Tie");
|
//$display ("Tie");
|
//Tie
|
//Tie
|
r_rselect <= r_next_fifo;
|
r_rselect <= r_next_fifo;
|
r_pre_activate[r_next_fifo] <= 1;
|
r_pre_activate[r_next_fifo] <= 1;
|
r_pre_activate[~r_next_fifo]<= 0;
|
r_pre_activate[~r_next_fifo]<= 0;
|
r_next_fifo <= ~r_next_fifo;
|
r_next_fifo <= ~r_next_fifo;
|
read_count <= r_size[r_next_fifo];
|
read_count <= r_size[r_next_fifo];
|
end
|
end
|
else begin
|
else begin
|
//Only one side is ready
|
//Only one side is ready
|
if (r_ready[0]) begin
|
if (r_ready[0]) begin
|
//$display ("select 0");
|
//$display ("select 0");
|
r_rselect <= 0;
|
r_rselect <= 0;
|
r_pre_activate[0] <= 1;
|
r_pre_activate[0] <= 1;
|
r_pre_activate[1] <= 0;
|
r_pre_activate[1] <= 0;
|
r_next_fifo <= 1;
|
r_next_fifo <= 1;
|
read_count <= r_size[0];
|
read_count <= r_size[0];
|
end
|
end
|
else begin
|
else begin
|
//$display ("select 1");
|
//$display ("select 1");
|
r_rselect <= 1;
|
r_rselect <= 1;
|
r_pre_activate[0] <= 0;
|
r_pre_activate[0] <= 0;
|
r_pre_activate[1] <= 1;
|
r_pre_activate[1] <= 1;
|
r_next_fifo <= 0;
|
r_next_fifo <= 0;
|
read_count <= r_size[1];
|
read_count <= r_size[1];
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
//User has finished reading something
|
//User has finished reading something
|
else if (r_activate[r_rselect] && !r_ready[r_rselect]) begin
|
else if (r_activate[r_rselect] && !r_ready[r_rselect]) begin
|
r_activate[r_rselect] <= 0;
|
r_activate[r_rselect] <= 0;
|
rcc_read_done[r_rselect] <= 1;
|
rcc_read_done[r_rselect] <= 1;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if ((r_pre_activate > 0) && r_pre_read_wait) begin
|
if ((r_pre_activate > 0) && r_pre_read_wait) begin
|
read_ready <= 1;
|
read_ready <= 1;
|
end
|
end
|
|
|
|
|
if (r_activate) begin
|
if (r_activate) begin
|
read_ready <= 0;
|
read_ready <= 0;
|
//User is requesting an accss
|
//User is requesting an accss
|
//Handle read strobes
|
//Handle read strobes
|
//Only handle strobes when we are enabled
|
//Only handle strobes when we are enabled
|
r_ready[r_rselect] <= 0;
|
r_ready[r_rselect] <= 0;
|
end
|
end
|
|
|
//XXX: There should be a better way to handle these edge conditions
|
//XXX: There should be a better way to handle these edge conditions
|
if (!r_activate && r_pre_read_wait) begin
|
if (!r_activate && r_pre_read_wait) begin
|
r_read_data <= w_read_data;
|
r_read_data <= w_read_data;
|
r_address <= r_address + 1;
|
r_address <= r_address + 1;
|
r_activate <= r_pre_activate;
|
r_activate <= r_pre_activate;
|
r_pre_activate <= 0;
|
r_pre_activate <= 0;
|
end
|
end
|
else if (!r_pre_read_wait) begin
|
else if (!r_pre_read_wait) begin
|
r_pre_read_wait <= 1;
|
r_pre_read_wait <= 1;
|
end
|
end
|
|
|
if (read_strobe && (r_address < (r_size[r_rselect] + 1))) begin
|
if (read_strobe && (r_address < (r_size[r_rselect] + 1))) begin
|
//Increment the address
|
//Increment the address
|
r_read_data <= w_read_data;
|
r_read_data <= w_read_data;
|
r_address <= r_address + 1;
|
r_address <= r_address + 1;
|
end
|
end
|
if (r_pre_strobe && !read_strobe) begin
|
if (r_pre_strobe && !read_strobe) begin
|
r_read_data <= w_read_data;
|
r_read_data <= w_read_data;
|
end
|
end
|
end
|
end
|
if (!rcc_read_ready[0] && !r_ready[0] && !r_activate[0]) begin
|
if (!rcc_read_ready[0] && !r_ready[0] && !r_activate[0]) begin
|
r_wait[0] <= 1;
|
r_wait[0] <= 1;
|
end
|
end
|
if (!rcc_read_ready[1] && !r_ready[1] && !r_activate[1]) begin
|
if (!rcc_read_ready[1] && !r_ready[1] && !r_activate[1]) begin
|
r_wait[1] <= 1;
|
r_wait[1] <= 1;
|
end
|
end
|
|
|
|
|
//Check if the write side has sent over some data
|
//Check if the write side has sent over some data
|
if (rcc_read_ready > 0) begin
|
if (rcc_read_ready > 0) begin
|
if ((r_wait == 2'b11) && (rcc_read_ready == 2'b11) && (w_count[0] > 0) && (w_count[1] > 0)) begin
|
if ((r_wait == 2'b11) && (rcc_read_ready == 2'b11) && (w_count[0] > 0) && (w_count[1] > 0)) begin
|
//An ambiguous sitution that can arrise if the read side is much
|
//An ambiguous sitution that can arrise if the read side is much
|
//slower than the write side, both sides can arrise seemingly at the
|
//slower than the write side, both sides can arrise seemingly at the
|
//same time, so there needs to be a tie breaker
|
//same time, so there needs to be a tie breaker
|
//$display ("Combo breaker goes to: %h", rcc_tie_select);
|
//$display ("Combo breaker goes to: %h", rcc_tie_select);
|
r_next_fifo <= rcc_tie_select;
|
r_next_fifo <= rcc_tie_select;
|
end
|
end
|
|
|
|
|
|
|
|
|
if (r_wait[0] && rcc_read_ready[0]) begin
|
if (r_wait[0] && rcc_read_ready[0]) begin
|
//$display ("write has send over data t othe 0 side");
|
//$display ("write has send over data t othe 0 side");
|
//Normally it would not be cool to transfer data over a clock domain
|
//Normally it would not be cool to transfer data over a clock domain
|
//but the w_count[x] is stable before the write side sends over a write
|
//but the w_count[x] is stable before the write side sends over a write
|
//strobe
|
//strobe
|
if (w_count[0] > 0) begin
|
if (w_count[0] > 0) begin
|
//Only enable when count > 0
|
//Only enable when count > 0
|
if ((r_activate == 0) && (!rcc_read_ready[1])) begin
|
if ((r_activate == 0) && (!rcc_read_ready[1])) begin
|
//$display ("select 0");
|
//$display ("select 0");
|
r_next_fifo <= 0;
|
r_next_fifo <= 0;
|
end
|
end
|
r_size[0] <= w_count[0];
|
r_size[0] <= w_count[0];
|
r_ready[0] <= 1;
|
r_ready[0] <= 1;
|
r_wait[0] <= 0;
|
r_wait[0] <= 0;
|
rcc_read_done[0] <= 0;
|
rcc_read_done[0] <= 0;
|
end
|
end
|
end
|
end
|
|
|
if (r_wait[1] && rcc_read_ready[1]) begin
|
if (r_wait[1] && rcc_read_ready[1]) begin
|
//$display ("write has send over data t othe 1 side");
|
//$display ("write has send over data t othe 1 side");
|
//Write side has sent some data over
|
//Write side has sent some data over
|
if (w_count[1] > 0) begin
|
if (w_count[1] > 0) begin
|
if ((r_activate == 0) && (!rcc_read_ready[0])) begin
|
if ((r_activate == 0) && (!rcc_read_ready[0])) begin
|
//$display ("select 1");
|
//$display ("select 1");
|
r_next_fifo <= 1;
|
r_next_fifo <= 1;
|
end
|
end
|
r_size[1] <= w_count[1];
|
r_size[1] <= w_count[1];
|
r_ready[1] <= 1;
|
r_ready[1] <= 1;
|
r_wait[1] <= 0;
|
r_wait[1] <= 0;
|
rcc_read_done[1] <= 0;
|
rcc_read_done[1] <= 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
