//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OMS 8051 cores UART Interface Module ////
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//// OMS 8051 cores UART Interface Module ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : ////
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//// Revision : ////
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//// v-0.0 : Nov 26, 2016 ////
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//// v-0.0 : Nov 26, 2016 ////
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//// 1. Initial version picked from ////
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//// 1. Initial version picked from ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// v-0.1 : Nov 28, 2016 ////
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//// v-0.1 : Nov 28, 2016 ////
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//// 1. Register access for Read/Write fifo & baudrate ////
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//// 1. Register access for Read/Write fifo & baudrate ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module uart_cfg (
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module uart_cfg (
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mclk,
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mclk,
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reset_n,
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reset_n,
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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reg_cs,
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reg_cs,
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reg_wr,
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reg_wr,
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reg_addr,
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reg_addr,
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reg_wdata,
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reg_wdata,
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reg_be,
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reg_be,
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// Outputs
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// Outputs
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reg_rdata,
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reg_rdata,
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reg_ack,
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reg_ack,
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// Uart Tx fifo interface
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// Uart Tx fifo interface
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tx_fifo_full,
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tx_fifo_full,
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tx_fifo_wr_en,
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tx_fifo_wr_en,
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tx_fifo_data,
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tx_fifo_data,
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// Uart Rx fifo interface
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// Uart Rx fifo interface
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rx_fifo_empty,
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rx_fifo_empty,
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rx_fifo_rd_en,
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rx_fifo_rd_en,
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rx_fifo_data,
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rx_fifo_data,
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// configuration
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// configuration
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cfg_tx_enable,
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cfg_tx_enable,
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cfg_rx_enable,
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cfg_rx_enable,
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cfg_stop_bit ,
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cfg_stop_bit ,
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cfg_pri_mod ,
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cfg_pri_mod ,
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cfg_baud_16x ,
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cfg_baud_16x ,
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frm_error_o,
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frm_error_o,
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par_error_o,
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par_error_o,
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rx_fifo_full_err_o
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rx_fifo_full_err_o
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);
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);
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input mclk;
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input mclk;
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input reset_n;
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input reset_n;
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//--------------------------------
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//--------------------------------
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// Uart Tx fifo interface
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// Uart Tx fifo interface
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//--------------------------------
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//--------------------------------
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input tx_fifo_full;
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input tx_fifo_full;
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output tx_fifo_wr_en;
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output tx_fifo_wr_en;
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output [7:0] tx_fifo_data;
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output [7:0] tx_fifo_data;
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//--------------------------------
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//--------------------------------
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// Uart Rx fifo interface
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// Uart Rx fifo interface
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//--------------------------------
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//--------------------------------
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input rx_fifo_empty;
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input rx_fifo_empty;
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output rx_fifo_rd_en;
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output rx_fifo_rd_en;
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input [7:0] rx_fifo_data;
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input [7:0] rx_fifo_data;
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//----------------------------------
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//----------------------------------
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// configuration
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// configuration
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//----------------------------------
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//----------------------------------
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output cfg_tx_enable ; // Tx Enable
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output cfg_tx_enable ; // Tx Enable
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output cfg_rx_enable ; // Rx Enable
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output cfg_rx_enable ; // Rx Enable
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output cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
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output cfg_stop_bit ; // 0 -> 1 Stop, 1 -> 2 Stop
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output [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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output [1:0] cfg_pri_mod ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
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output [11:0] cfg_baud_16x ; // 16x Baud clock config
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output [11:0] cfg_baud_16x ; // 16x Baud clock config
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input frm_error_o ; // framing error
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input frm_error_o ; // framing error
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input par_error_o ; // par error
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input par_error_o ; // par error
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input rx_fifo_full_err_o ; // rx fifo full error
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input rx_fifo_full_err_o ; // rx fifo full error
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//---------------------------------
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//---------------------------------
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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input reg_cs ;
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input reg_cs ;
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input reg_wr ;
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input reg_wr ;
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input [3:0] reg_addr ;
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input [3:0] reg_addr ;
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input [31:0] reg_wdata ;
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input [7:0] reg_wdata ;
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input [3:0] reg_be ;
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input reg_be ;
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// Outputs
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// Outputs
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output [31:0] reg_rdata ;
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output [7:0] reg_rdata ;
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output reg_ack ;
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output reg_ack ;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Internal Wire Declarations
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// Internal Wire Declarations
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire sw_rd_en;
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wire sw_rd_en;
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wire sw_wr_en;
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wire sw_wr_en;
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wire [3:0] sw_addr ; // addressing 16 registers
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wire [3:0] sw_addr ; // addressing 16 registers
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wire [3:0] wr_be ;
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wire wr_be ;
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reg [31:0] reg_rdata ;
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reg [7:0] reg_rdata ;
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reg reg_ack ;
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reg reg_ack ;
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wire [31:0] reg_0; // Software_Reg_0
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wire [7:0] reg_0; // Software_Reg_0
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wire [31:0] reg_1; // Software-Reg_1
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wire [7:0] reg_1; // Software-Reg_1
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wire [31:0] reg_2; // Software-Reg_2
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wire [7:0] reg_2; // Software-Reg_2
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wire [31:0] reg_3; // Software-Reg_3
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wire [7:0] reg_3; // Software-Reg_3
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wire [31:0] reg_4; // Software-Reg_4
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wire [7:0] reg_4; // Software-Reg_4
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wire [31:0] reg_5; // Software-Reg_5
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wire [7:0] reg_5; // Software-Reg_5
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wire [31:0] reg_6; // Software-Reg_6
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wire [7:0] reg_6; // Software-Reg_6
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wire [31:0] reg_7; // Software-Reg_7
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wire [7:0] reg_7; // Software-Reg_7
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wire [31:0] reg_8; // Software-Reg_8
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wire [7:0] reg_8; // Software-Reg_8
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wire [31:0] reg_9; // Software-Reg_9
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wire [7:0] reg_9; // Software-Reg_9
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wire [31:0] reg_10; // Software-Reg_10
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wire [7:0] reg_10; // Software-Reg_10
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wire [31:0] reg_11; // Software-Reg_11
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wire [7:0] reg_11; // Software-Reg_11
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wire [31:0] reg_12; // Software-Reg_12
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wire [7:0] reg_12; // Software-Reg_12
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wire [31:0] reg_13; // Software-Reg_13
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wire [7:0] reg_13; // Software-Reg_13
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wire [31:0] reg_14; // Software-Reg_14
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wire [7:0] reg_14; // Software-Reg_14
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wire [31:0] reg_15; // Software-Reg_15
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wire [7:0] reg_15; // Software-Reg_15
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reg [31:0] reg_out;
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reg [7:0] reg_out;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Main code starts here
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// Main code starts here
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Internal Logic Starts here
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// Internal Logic Starts here
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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assign sw_addr = reg_addr [3:0];
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assign sw_addr = reg_addr [3:0];
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assign sw_rd_en = reg_cs & !reg_wr;
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assign sw_rd_en = reg_cs & !reg_wr;
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assign sw_wr_en = reg_cs & reg_wr;
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assign sw_wr_en = reg_cs & reg_wr;
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assign wr_be = reg_be;
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assign wr_be = reg_be;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Read path mux
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// Read path mux
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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always @ (posedge mclk or negedge reset_n)
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always @ (posedge mclk or negedge reset_n)
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begin : preg_out_Seq
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begin : preg_out_Seq
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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begin
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begin
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reg_rdata [31:0] <= 32'h0000_0000;
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reg_rdata [7:0] <= 8'h00;
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reg_ack <= 1'b0;
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reg_ack <= 1'b0;
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end
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end
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else if (sw_rd_en && !reg_ack)
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else if (sw_rd_en && !reg_ack)
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begin
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begin
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reg_rdata [31:0] <= reg_out [31:0];
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reg_rdata [7:0] <= reg_out [7:0];
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reg_ack <= 1'b1;
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reg_ack <= 1'b1;
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end
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end
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else if (sw_wr_en && !reg_ack)
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else if (sw_wr_en && !reg_ack)
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reg_ack <= 1'b1;
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reg_ack <= 1'b1;
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else
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else
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begin
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begin
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reg_ack <= 1'b0;
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reg_ack <= 1'b0;
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end
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end
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end
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end
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// register read enable and write enable decoding logic
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// register read enable and write enable decoding logic
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
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wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
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wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
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wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
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wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
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wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
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wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
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wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
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wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
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wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
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wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
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wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
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wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
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wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
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wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
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wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
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wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
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wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
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wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
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wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
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wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
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wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
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wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
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wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
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wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
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wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
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wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
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wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
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wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
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wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
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wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
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wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
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wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
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wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
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wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
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wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
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wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
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wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
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wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
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wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
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wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
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wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
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wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
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wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
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wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
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wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
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wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
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wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
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wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
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wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
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wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
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wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
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wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
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wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
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wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
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wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
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wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
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wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
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wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
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wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
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wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
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wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
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wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
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wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
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always @( *)
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always @( *)
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begin : preg_sel_Com
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begin : preg_sel_Com
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reg_out [31:0] = 32'd0;
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reg_out [7:0] = 8'd0;
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case (sw_addr [3:0])
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case (sw_addr [3:0])
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4'b0000 : reg_out [31:0] = reg_0 [31:0];
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4'b0000 : reg_out [7:0] = reg_0 [7:0];
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4'b0001 : reg_out [31:0] = reg_1 [31:0];
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4'b0001 : reg_out [7:0] = reg_1 [7:0];
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4'b0010 : reg_out [31:0] = reg_2 [31:0];
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4'b0010 : reg_out [7:0] = reg_2 [7:0];
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4'b0011 : reg_out [31:0] = reg_3 [31:0];
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4'b0011 : reg_out [7:0] = reg_3 [7:0];
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4'b0100 : reg_out [31:0] = reg_4 [31:0];
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4'b0100 : reg_out [7:0] = reg_4 [7:0];
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4'b0101 : reg_out [31:0] = reg_5 [31:0];
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4'b0101 : reg_out [7:0] = reg_5 [7:0];
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4'b0110 : reg_out [31:0] = reg_6 [31:0];
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4'b0110 : reg_out [7:0] = reg_6 [7:0];
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4'b0111 : reg_out [31:0] = reg_7 [31:0];
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4'b0111 : reg_out [7:0] = reg_7 [7:0];
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4'b1000 : reg_out [31:0] = reg_8 [31:0];
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4'b1000 : reg_out [7:0] = reg_8 [7:0];
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4'b1001 : reg_out [31:0] = reg_9 [31:0];
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4'b1001 : reg_out [7:0] = reg_9 [7:0];
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4'b1010 : reg_out [31:0] = reg_10 [31:0];
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4'b1010 : reg_out [7:0] = reg_10 [7:0];
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4'b1011 : reg_out [31:0] = reg_11 [31:0];
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4'b1011 : reg_out [7:0] = reg_11 [7:0];
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4'b1100 : reg_out [31:0] = reg_12 [31:0];
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4'b1100 : reg_out [7:0] = reg_12 [7:0];
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4'b1101 : reg_out [31:0] = reg_13 [31:0];
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4'b1101 : reg_out [7:0] = reg_13 [7:0];
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4'b1110 : reg_out [31:0] = reg_14 [31:0];
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4'b1110 : reg_out [7:0] = reg_14 [7:0];
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4'b1111 : reg_out [31:0] = reg_15 [31:0];
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4'b1111 : reg_out [7:0] = reg_15 [7:0];
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endcase
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endcase
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end
|
end
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|
|
|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// Individual register assignments
|
// Individual register assignments
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// Logic for Register 0 : uart Control Register
|
// Logic for Register 0 : uart Control Register
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
wire [1:0] cfg_pri_mod = reg_0[4:3]; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
|
wire [1:0] cfg_pri_mod = reg_0[4:3]; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
|
wire cfg_stop_bit = reg_0[2]; // 0 -> 1 Stop, 1 -> 2 Stop
|
wire cfg_stop_bit = reg_0[2]; // 0 -> 1 Stop, 1 -> 2 Stop
|
wire cfg_rx_enable = reg_0[1]; // Rx Enable
|
wire cfg_rx_enable = reg_0[1]; // Rx Enable
|
wire cfg_tx_enable = reg_0[0]; // Tx Enable
|
wire cfg_tx_enable = reg_0[0]; // Tx Enable
|
|
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generic_register #(5,0 ) u_uart_ctrl_be0 (
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generic_register #(5,0 ) u_uart_ctrl_be0 (
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.we ({5{sw_wr_en_0 &
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.we ({5{sw_wr_en_0 &
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wr_be[0] }} ),
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wr_be }} ),
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.data_in (reg_wdata[4:0] ),
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.data_in (reg_wdata[4:0] ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.clk (mclk ),
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.clk (mclk ),
|
|
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//List of Outs
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//List of Outs
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.data_out (reg_0[4:0] )
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.data_out (reg_0[4:0] )
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);
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);
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|
|
|
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assign reg_0[31:5] = 27'h0;
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assign reg_0[7:5] = 3'h0;
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|
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Logic for Register 1 : uart interrupt status
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// Logic for Register 1 : uart interrupt status
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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stat_register u_intr_bit0 (
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stat_register u_intr_bit0 (
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//inputs
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//inputs
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. clk (mclk ),
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. clk (mclk ),
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. reset_n (reset_n ),
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. reset_n (reset_n ),
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. cpu_we (sw_wr_en_1 &
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. cpu_we (sw_wr_en_1 &
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wr_be[0] ),
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wr_be ),
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. cpu_ack (reg_wdata[0] ),
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. cpu_ack (reg_wdata[0] ),
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. hware_req (frm_error_o ),
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. hware_req (frm_error_o ),
|
|
|
//outputs
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//outputs
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. data_out (reg_1[0] )
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. data_out (reg_1[0] )
|
);
|
);
|
|
|
stat_register u_intr_bit1 (
|
stat_register u_intr_bit1 (
|
//inputs
|
//inputs
|
. clk (mclk ),
|
. clk (mclk ),
|
. reset_n (reset_n ),
|
. reset_n (reset_n ),
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. cpu_we (sw_wr_en_1 &
|
. cpu_we (sw_wr_en_1 &
|
wr_be[0] ),
|
wr_be ),
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. cpu_ack (reg_wdata[1] ),
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. cpu_ack (reg_wdata[1] ),
|
. hware_req (par_error_o ),
|
. hware_req (par_error_o ),
|
|
|
//outputs
|
//outputs
|
. data_out (reg_1[1] )
|
. data_out (reg_1[1] )
|
);
|
);
|
|
|
stat_register u_intr_bit2 (
|
stat_register u_intr_bit2 (
|
//inputs
|
//inputs
|
. clk (mclk ),
|
. clk (mclk ),
|
. reset_n (reset_n ),
|
. reset_n (reset_n ),
|
. cpu_we (sw_wr_en_1 &
|
. cpu_we (sw_wr_en_1 &
|
wr_be[0] ),
|
wr_be ),
|
. cpu_ack (reg_wdata[2] ),
|
. cpu_ack (reg_wdata[2] ),
|
. hware_req (rx_fifo_full_err_o ),
|
. hware_req (rx_fifo_full_err_o ),
|
|
|
//outputs
|
//outputs
|
. data_out (reg_1[2] )
|
. data_out (reg_1[2] )
|
);
|
);
|
|
|
assign reg_1[31:3] = 29'h0;
|
assign reg_1[7:3] = 5'h0;
|
|
|
|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// Logic for Register 2 : Baud Rate Control
|
// Logic for Register 2 : Baud Rate Control
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
wire [11:0] cfg_baud_16x = reg_2[11:0];
|
wire [11:0] cfg_baud_16x = {reg_3[3:0],reg_2[7:0]};
|
|
|
generic_register #(12,0 ) u_uart_ctrl_reg2 (
|
generic_register #(8,0 ) u_uart_ctrl_reg2 (
|
.we ({12{sw_wr_en_2 &
|
.we ({8{sw_wr_en_2 &
|
wr_be[0] }} ),
|
wr_be }} ),
|
.data_in (reg_wdata[11:0] ),
|
.data_in (reg_wdata[7:0] ),
|
.reset_n (reset_n ),
|
.reset_n (reset_n ),
|
.clk (mclk ),
|
.clk (mclk ),
|
|
|
//List of Outs
|
//List of Outs
|
.data_out (reg_2[11:0] )
|
.data_out (reg_2[7:0] )
|
);
|
);
|
|
|
|
generic_register #(4,0 ) u_uart_ctrl_reg3 (
|
|
.we ({4{sw_wr_en_3 &
|
|
wr_be }} ),
|
|
.data_in (reg_wdata[3:0] ),
|
|
.reset_n (reset_n ),
|
|
.clk (mclk ),
|
|
|
assign reg_2[31:12] = 20'h0;
|
//List of Outs
|
|
.data_out (reg_3[3:0] )
|
|
);
|
|
|
|
assign reg_3[7:4] = 4'h0;
|
|
|
|
|
assign reg_3[31:0] = {30'h0,rx_fifo_empty,tx_fifo_full};
|
// reg-4 status
|
|
//
|
|
assign reg_4[7:0] = {6'h0,rx_fifo_empty,tx_fifo_full};
|
|
|
// reg_4 is tx_fifo wr
|
// reg_5 is tx_fifo wr
|
assign tx_fifo_wr_en = sw_wr_en_4 & reg_ack;
|
assign tx_fifo_wr_en = sw_wr_en_5 & reg_ack & !tx_fifo_full;
|
assign tx_fifo_data = reg_wdata[7:0];
|
assign tx_fifo_data = reg_wdata[7:0];
|
|
|
// reg_5 is rx_fifo read
|
// reg_6 is rx_fifo read
|
// rx_fifo read data
|
// rx_fifo read data
|
assign reg_5[31:0] = {24'h0,rx_fifo_data};
|
assign reg_6[7:0] = {rx_fifo_data};
|
assign rx_fifo_rd_en = sw_rd_en_5 & reg_ack;
|
assign rx_fifo_rd_en = sw_rd_en_6 & reg_ack & !rx_fifo_empty;
|
|
|
|
|
endmodule
|
endmodule
|
|
|