//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051/ ////
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//// http://www.opencores.org/cores/oms8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// OMS 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "tb_defines.v"
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`include "tb_defines.v"
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module tb_top;
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module tb_top;
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reg reset_n;
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reg reset_n;
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reg reset;
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reg reset;
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reg xtal_clk;
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reg xtal_clk;
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reg ref_clk_125;
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reg ref_clk_125;
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wire app_clk;
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wire app_clk;
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reg ref_clk_50;
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reg ref_clk_50;
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reg uart_clk_16x;
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reg uart_clk_16x;
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parameter XTAL_CLK_PERIOD = 10; // 100MHZ 40; // 25Mhz
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parameter XTAL_CLK_PERIOD = 10; // 100MHZ 40; // 25Mhz
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parameter APP_CLK_PERIOD = 10;
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parameter APP_CLK_PERIOD = 10;
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parameter REF_CLK_125_PERIOD = 8;
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parameter REF_CLK_125_PERIOD = 8;
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parameter REF_CLK_50_PERIOD = 20;
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parameter REF_CLK_50_PERIOD = 20;
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parameter UART_REF_CLK_PERIOD = 20;
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parameter UART_REF_CLK_PERIOD = 20;
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reg[31:0] events_log;
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reg[31:0] events_log;
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initial
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initial
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begin
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begin
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reset_n = 1;
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reset_n = 1;
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#100 reset_n = 0;
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#100 reset_n = 0;
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#100 reset_n = 1;
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#100 reset_n = 1;
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end
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end
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initial begin
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initial begin
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xtal_clk = 1'b0;
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xtal_clk = 1'b0;
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forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
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forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
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end
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end
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//initial begin
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//initial begin
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// app_clk = 1'b0;
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// app_clk = 1'b0;
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// forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
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// forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
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//end
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//end
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initial begin
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initial begin
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ref_clk_125 = 1'b0;
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ref_clk_125 = 1'b0;
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forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
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forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
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end
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end
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initial begin
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initial begin
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ref_clk_50 = 1'b0;
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ref_clk_50 = 1'b0;
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forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
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forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
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end
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end
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initial begin
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initial begin
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uart_clk_16x = 1'b0;
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uart_clk_16x = 1'b0;
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forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
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forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
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end
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end
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wire [3:0] phy_txd ;
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wire [3:0] phy_txd ;
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wire [3:0] phy_rxd ;
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wire [3:0] phy_rxd ;
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//---------------------------------
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//---------------------------------
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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reg reg_cs ;
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reg reg_cs ;
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reg [3:0] reg_id ;
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reg [3:0] reg_id ;
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reg reg_wr ;
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reg reg_wr ;
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reg [14:0] reg_addr ;
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reg [14:0] reg_addr ;
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reg [31:0] reg_wdata ;
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reg [7:0] reg_wdata ;
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reg [3:0] reg_be ;
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reg reg_be ;
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// Outputs
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// Outputs
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wire [31:0] reg_rdata ;
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wire [7:0] reg_rdata ;
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wire reg_ack ;
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wire reg_ack ;
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reg master_mode ;
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reg master_mode ;
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reg ea_in ; // 1--> Internal Memory
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reg ea_in ; // 1--> Internal Memory
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wire spi_sck ;
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wire spi_sck ;
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wire spi_so ;
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wire spi_so ;
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wire spi_si ;
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wire spi_si ;
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wire [3:0] spi_cs_n ;
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wire [3:0] spi_cs_n ;
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wire clkout ;
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wire clkout ;
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wire reset_out_n ;
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wire reset_out_n ;
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//----------------------------------------
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//----------------------------------------
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// 8051 core ROM related signals
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//---------------------------------------
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wire [15:0] wb_xrom_adr ; // instruction address
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wire wb_xrom_ack ; // instruction acknowlage
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wire wb_xrom_err ; // instruction error
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wire wb_xrom_wr ; // instruction error
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wire [31:0] wb_xrom_rdata ; // rom data input
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wire [31:0] wb_xrom_wdata ; // rom data input
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wire wb_xrom_stb ; // instruction strobe
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wire wb_xrom_cyc ; // instruction cycle
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//----------------------------------------
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// 8051 core RAM related signals
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//---------------------------------------
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wire [15:0] wb_xram_adr ; // data-ram address
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wire wb_xram_ack ; // data-ram acknowlage
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wire wb_xram_err ; // data-ram error
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wire wb_xram_wr ; // data-ram error
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wire [3:0] wb_xram_be ; // data-ram error
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wire [31:0] wb_xram_rdata ; // ram data input
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wire [31:0] wb_xram_wdata ; // ram data input
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wire wb_xram_stb ; // data-ram strobe
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wire wb_xram_cyc ; // data-ram cycle
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//----------------------------------------
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digital_core u_core (
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digital_core u_core (
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. reset_n (reset_n ),
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. reset_n (reset_n ),
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. fastsim_mode (1'b1 ),
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. fastsim_mode (1'b1 ),
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. mastermode (master_mode ),
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. mastermode (master_mode ),
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. xtal_clk (xtal_clk ),
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. xtal_clk (xtal_clk ),
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. clkout (app_clk ),
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. clkout (app_clk ),
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. reset_out_n (reset_out_n ),
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. reset_out_n (reset_out_n ),
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. ea_in (ea_in ), // internal ROM
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. ea_in (ea_in ), // internal ROM
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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. ext_reg_cs (reg_cs ),
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. ext_reg_cs (reg_cs ),
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. ext_reg_tid (reg_id ),
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. ext_reg_tid (reg_id ),
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. ext_reg_wr (reg_wr ),
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. ext_reg_wr (reg_wr ),
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. ext_reg_addr (reg_addr[14:0] ),
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. ext_reg_addr (reg_addr[14:0] ),
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. ext_reg_wdata (reg_wdata ),
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. ext_reg_wdata (reg_wdata ),
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. ext_reg_be (reg_be ),
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// Outputs
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// Outputs
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. ext_reg_rdata (reg_rdata ),
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. ext_reg_rdata (reg_rdata ),
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. ext_reg_ack (reg_ack ),
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. ext_reg_ack (reg_ack ),
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// UART Line Interface
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// UART Line Interface
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.si (si ),
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.si (si ),
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.so (so ),
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.so (so ),
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.spi_sck (spi_sck ),
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.spi_sck (spi_sck ),
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.spi_so (spi_so ),
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.spi_so (spi_so ),
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.spi_si (spi_si ),
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.spi_si (spi_si ),
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.spi_cs_n (spi_cs_n )
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.spi_cs_n (spi_cs_n )
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);
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);
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uart_agent tb_uart (
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uart_agent tb_uart (
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. test_clk (uart_clk_16x ),
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. test_clk (uart_clk_16x ),
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. sin (si ),
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. sin (si ),
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. dsr_n ( ),
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. dsr_n ( ),
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. cts_n ( ),
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. cts_n ( ),
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. dcd_n ( ),
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. dcd_n ( ),
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. sout (so ),
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. sout (so ),
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. dtr_n (1'b0 ),
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. dtr_n (1'b0 ),
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. rts_n (1'b0 ),
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. rts_n (1'b0 ),
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. out1_n (1'b0 ),
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. out1_n (1'b0 ),
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. out2_n (1'b0 )
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. out2_n (1'b0 )
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);
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);
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//----------------------- SPI Agents
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//----------------------- SPI Agents
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m25p20 i_m25p20_0 (
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m25p20 i_m25p20_0 (
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.c (spi_sck ),
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.c (spi_sck ),
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.s (spi_cs_n[0] ), // Include selection logic
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.s (spi_cs_n[0] ), // Include selection logic
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.w (1'b1 ), // Write protect is always disabled
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.w (1'b1 ), // Write protect is always disabled
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.hold (1'b1 ), // Hold support not used
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.hold (1'b1 ), // Hold support not used
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.data_in (spi_so ),
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.data_in (spi_so ),
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.data_out (spi_si )
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.data_out (spi_si )
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);
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);
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AT45DB321 i_AT45DB321_0 (
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AT45DB321 i_AT45DB321_0 (
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.CSB (spi_cs_n[1] ),
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.CSB (spi_cs_n[1] ),
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.SCK (spi_sck ),
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.SCK (spi_sck ),
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.SI (spi_so ),
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.SI (spi_so ),
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.WPB (1'b1 ),
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.WPB (1'b1 ),
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.RESETB (1'b1 ),
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.RESETB (1'b1 ),
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.RDY_BUSYB ( ),
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.RDY_BUSYB ( ),
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.SO (spi_si )
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.SO (spi_si )
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);
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);
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/***************
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/***************
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spi_agent_3120 spi_agent_3120_0 (
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spi_agent_3120 spi_agent_3120_0 (
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.cs_b (spi_cs_n[2] ),
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.cs_b (spi_cs_n[2] ),
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.spi_din (spi_si ),
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.spi_din (spi_si ),
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.spi_dout (spi_so ),
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.spi_dout (spi_so ),
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.spi_clk (spi_sck )
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.spi_clk (spi_sck )
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);
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);
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spi_agent_3120 spi_agent_3120_1 (
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spi_agent_3120 spi_agent_3120_1 (
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.cs_b (spi_cs_n[3] ),
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.cs_b (spi_cs_n[3] ),
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.spi_din (spi_si ),
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.spi_din (spi_si ),
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.spi_dout (spi_so ),
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.spi_dout (spi_so ),
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.spi_clk (spi_sck )
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.spi_clk (spi_sck )
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);
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);
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*****************/
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*****************/
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tb_glbl tb_glbl ();
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tb_glbl tb_glbl ();
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`ifdef DUMP_ENABLE
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`ifdef DUMP_ENABLE
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initial begin
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initial begin
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if ( $test$plusargs("DUMP") ) begin
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if ( $test$plusargs("DUMP") ) begin
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$fsdbDumpfile("../dump/test_1.fsdb");
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$fsdbDumpfile("../dump/test_1.fsdb");
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$fsdbDumpvars;
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$fsdbDumpvars;
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$fsdbDumpon;
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$fsdbDumpon;
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end
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end
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end
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end
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`endif
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`endif
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initial begin //{
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initial begin //{
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$display ("--> Dumpping the design");
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$display ("--> Dumpping the design");
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$shm_open("simvision.shm");
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$shm_open("simvision.shm");
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$shm_probe("AC");
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$shm_probe("AC");
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end //}
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end //}
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initial begin
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initial begin
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if ( $test$plusargs("INTERNAL_ROM") ) begin
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if ( $test$plusargs("INTERNAL_ROM") ) begin
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ea_in = 1;
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ea_in = 1;
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master_mode = 1;
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master_mode = 1;
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end else if ( $test$plusargs("EXTERNAL_ROM") ) begin
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end else if ( $test$plusargs("EXTERNAL_ROM") ) begin
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ea_in = 0;
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ea_in = 0;
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master_mode = 1;
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master_mode = 1;
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end else begin
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end else begin
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ea_in = 0;
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ea_in = 0;
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master_mode = 0;
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master_mode = 0;
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end
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end
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`TB_GLBL.init;
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`TB_GLBL.init;
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#1000 wait(reset_out_n == 1);
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#1000 wait(reset_out_n == 1);
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if ( $test$plusargs("uart_test_1") )
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if ( $test$plusargs("uart_test_1") )
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uart_test1();
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uart_test1();
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else if ( $test$plusargs("spi_test_1") )
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else if ( $test$plusargs("spi_test_1") )
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spi_test1();
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spi_test1();
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else begin
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else begin
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// 8051 Test Cases
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// 8051 Test Cases
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#80000000
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#80000000
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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end
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end
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`TB_GLBL.test_stats;
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`TB_GLBL.test_stats;
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`TB_GLBL.test_finish;
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`TB_GLBL.test_finish;
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#1000 $finish;
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#1000 $finish;
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end
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end
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wire [7:0] p2_out = u_core.u_8051_core.p2_o;
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wire [7:0] p2_out = u_core.u_8051_core.p2_o;
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wire [7:0] p3_out = u_core.u_8051_core.p3_o;
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wire [7:0] p3_out = u_core.u_8051_core.p3_o;
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always @(p2_out or p3_out)
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always @(p2_out or p3_out)
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begin
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begin
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if((p2_out == 8'haa) && // fib.c
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if((p2_out == 8'haa) && // fib.c
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(p3_out == 8'haa )) begin
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(p3_out == 8'haa )) begin
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$display("################################");
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$display("################################");
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$display("TEST STATUS : PASSED ");
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$display("TEST STATUS : PASSED ");
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$display("################################");
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$display("################################");
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#100
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#100
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$finish;
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$finish;
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end else if(p2_out == 8'h55) begin // fib.c
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end else if(p2_out == 8'h55) begin // fib.c
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$display("");
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$display("");
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$display("time ",$time," Error: %h", p3_out);
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$display("time ",$time," Error: %h", p3_out);
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$display("TEST STATUS : FAILED ");
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$display("TEST STATUS : FAILED ");
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$display("");
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$display("");
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#100
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#100
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$finish;
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$finish;
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end
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end
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end
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end
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`include "uart_test1.v"
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`include "uart_test1.v"
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`include "spi_test1.v"
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`include "spi_test1.v"
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`include "tb_tasks.v"
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`include "tb_tasks.v"
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`include "spi_tasks.v"
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`include "spi_tasks.v"
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endmodule
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endmodule
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`include "tb_glbl.v"
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`include "tb_glbl.v"
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