////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: enetctrl
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// Filename: enetctrl
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose: This module translates wishbone commands, whether they be read
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// Purpose: This module translates wishbone commands, whether they be read
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// or write commands, to MIO commands operating on an Ethernet
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// or write commands, to MIO commands operating on an Ethernet
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// controller, such as the TI DP83848 controller on the Artix-7 Arty
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// controller, such as the TI DP83848 controller on the Artix-7 Arty
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// development boarod (used by this project). As designed, the bus
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// development boarod (used by this project). As designed, the bus
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// *will* stall until the command has been completed.
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// *will* stall until the command has been completed.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`define ECTRL_RESET 3'h0
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`define ECTRL_RESET 3'h0
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`define ECTRL_IDLE 3'h1
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`define ECTRL_IDLE 3'h1
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`define ECTRL_ADDRESS 3'h2
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`define ECTRL_ADDRESS 3'h2
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`define ECTRL_READ 3'h3
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`define ECTRL_READ 3'h3
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`define ECTRL_WRITE 3'h4
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`define ECTRL_WRITE 3'h4
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module enetctrl(i_clk, i_rst,
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module enetctrl(i_clk, i_rst,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_mdclk, o_mdio, i_mdio, o_mdwe);
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o_mdclk, o_mdio, i_mdio, o_mdwe,
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o_debug);
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parameter CLKBITS=3; // = 3 for 200MHz source clock, 2 for 100 MHz
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parameter CLKBITS=3; // = 3 for 200MHz source clock, 2 for 100 MHz
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [4:0] i_wb_addr;
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input [4:0] i_wb_addr;
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input [15:0] i_wb_data;
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input [15:0] i_wb_data;
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output reg o_wb_ack, o_wb_stall;
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output reg o_wb_ack, o_wb_stall;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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//
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//
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input i_mdio;
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input i_mdio;
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output wire o_mdclk;
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output wire o_mdclk;
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output reg o_mdio, o_mdwe;
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output reg o_mdio, o_mdwe;
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//
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//
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output wire [31:0] o_debug;
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//
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parameter PHYADDR = 5'h01;
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parameter PHYADDR = 5'h01;
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reg read_pending, write_pending;
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reg read_pending, write_pending;
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reg [4:0] r_addr;
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reg [4:0] r_addr;
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reg [15:0] read_reg, write_reg, r_data;
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reg [15:0] read_reg, write_reg, r_data;
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reg [2:0] ctrl_state;
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reg [2:0] ctrl_state;
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reg [5:0] reg_pos;
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reg [5:0] reg_pos;
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reg zreg_pos;
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reg zreg_pos;
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reg [15:0] r_wb_data;
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reg [15:0] r_wb_data;
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// Step 1: Generate our clock
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// Step 1: Generate our clock
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reg [(CLKBITS-1):0] clk_counter;
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reg [(CLKBITS-1):0] clk_counter;
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initial clk_counter = 0;
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initial clk_counter = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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clk_counter <= clk_counter + 1;
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clk_counter <= clk_counter + 1;
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assign o_mdclk = clk_counter[(CLKBITS-1)];
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assign o_mdclk = clk_counter[(CLKBITS-1)];
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// Step 2: Generate strobes for when to move, given the clock
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// Step 2: Generate strobes for when to move, given the clock
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reg rclk, zclk;
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reg rclk, zclk;
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initial zclk = 0;
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initial zclk = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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zclk <= &clk_counter;
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zclk <= (&clk_counter[(CLKBITS-1):1])&&(!clk_counter[0]);
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initial rclk = 0;
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initial rclk = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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rclk <= (~clk_counter[(CLKBITS-1)])&&(&clk_counter[(CLKBITS-2):0]);
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rclk <= (~clk_counter[(CLKBITS-1)])&&(&clk_counter[(CLKBITS-2):0]);
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// Step 3: Read from our input port
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// Step 3: Read from our input port
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// Note: I read on the falling edge, he changes on the rising edge
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// Note: I read on the falling edge, he changes on the rising edge
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reg in_idle;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (zclk)
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if (zclk)
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read_reg <= { read_reg[14:0], i_mdio };
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read_reg <= { read_reg[14:0], i_mdio };
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always @(posedge i_clk)
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always @(posedge i_clk)
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zreg_pos <= (reg_pos == 0);
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zreg_pos <= (reg_pos == 0);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (rclk)
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if (rclk)
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r_wb_data <= read_reg;
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r_wb_data <= read_reg;
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assign o_wb_data = { 16'h00, r_wb_data };
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assign o_wb_data = { 16'h00, r_wb_data };
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// Step 4: Write to our output port
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// Step 4: Write to our output port
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// Note: I change on the falling edge,
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// Note: I change on the falling edge,
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (zclk)
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if (zclk)
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o_mdio <= write_reg[15];
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o_mdio <= write_reg[15];
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reg in_idle;
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initial in_idle = 1'b0;
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initial in_idle = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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in_idle <= (ctrl_state == `ECTRL_IDLE);
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in_idle <= (ctrl_state == `ECTRL_IDLE);
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initial o_wb_stall = 1'b0;
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initial o_wb_stall = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (ctrl_state != `ECTRL_IDLE)
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if (ctrl_state != `ECTRL_IDLE)
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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else if (o_wb_ack)
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else if (o_wb_ack)
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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else if (((i_wb_stb)&&(in_idle))||(read_pending)||(write_pending))
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else if (((i_wb_stb)&&(in_idle))||(read_pending)||(write_pending))
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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else o_wb_stall <= 1'b0;
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else o_wb_stall <= 1'b0;
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initial read_pending = 1'b0;
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initial read_pending = 1'b0;
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initial write_pending = 1'b0;
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initial write_pending = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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r_addr <= i_wb_addr;
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r_addr <= i_wb_addr;
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if ((i_wb_stb)&&(~o_wb_stall))
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if ((i_wb_stb)&&(~o_wb_stall))
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r_data <= i_wb_data;
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r_data <= i_wb_data;
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if ((i_rst)||(ctrl_state == `ECTRL_READ)||(ctrl_state == `ECTRL_WRITE))
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if ((i_rst)||(ctrl_state == `ECTRL_READ)||(ctrl_state == `ECTRL_WRITE))
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begin
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begin
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read_pending <= 1'b0;
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read_pending <= 1'b0;
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write_pending <= 1'b0;
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write_pending <= 1'b0;
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end else if ((i_wb_stb)&&(~o_wb_stall))
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end else if ((i_wb_stb)&&(~o_wb_stall))
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begin
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begin
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read_pending <= (~i_wb_we);
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read_pending <= (~i_wb_we);
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write_pending <= (i_wb_we);
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write_pending <= (i_wb_we);
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end
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end
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end
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end
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initial reg_pos = 6'h3f;
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initial reg_pos = 6'h3f;
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initial ctrl_state = `ECTRL_RESET;
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initial ctrl_state = `ECTRL_RESET;
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initial write_reg = 16'hffff;
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initial write_reg = 16'hffff;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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if ((zclk)&&(~zreg_pos))
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if ((zclk)&&(!zreg_pos))
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reg_pos <= reg_pos - 1;
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reg_pos <= reg_pos - 1;
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if (zclk)
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if (zclk)
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write_reg <= { write_reg[14:0], 1'b1 };
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write_reg <= { write_reg[14:0], 1'b1 };
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if (i_rst)
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if (i_rst)
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begin // Must go for 167 ms before our 32 clocks
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begin // Must go for 167 ms before our 32 clocks
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ctrl_state <= `ECTRL_RESET;
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ctrl_state <= `ECTRL_RESET;
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reg_pos <= 6'h3f;
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reg_pos <= 6'h3f;
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write_reg[15:0] <= 16'hffff;
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write_reg[15:0] <= 16'hffff;
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end else case(ctrl_state)
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end else case(ctrl_state)
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`ECTRL_RESET: begin
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`ECTRL_RESET: begin
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o_mdwe <= 1'b1; // Write
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o_mdwe <= 1'b1; // Write
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write_reg[15:0] <= 16'hffff;
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write_reg[15:0] <= 16'hffff;
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if ((zclk)&&(zreg_pos))
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if ((zclk)&&(zreg_pos))
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ctrl_state <= `ECTRL_IDLE;
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ctrl_state <= `ECTRL_IDLE;
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end
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end
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`ECTRL_IDLE: begin
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`ECTRL_IDLE: begin
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o_mdwe <= 1'b1; // Write
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o_mdwe <= 1'b1; // Write
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write_reg <= { 4'he, PHYADDR, r_addr, 2'b11 };
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write_reg <= { 4'he, PHYADDR, r_addr, 2'b11 };
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if (write_pending)
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if (write_pending)
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begin
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write_reg[15:12] <= { 4'h5 };
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write_reg[15:12] <= { 4'h5 };
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else if (read_pending)
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write_reg[0] <= 1'b0;
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end else if (read_pending)
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write_reg[15:12] <= { 4'h6 };
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write_reg[15:12] <= { 4'h6 };
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if (read_pending || write_pending)
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if (!zclk)
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begin
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write_reg[15] <= 1'b1;
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reg_pos <= 6'h0f;
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reg_pos <= 6'h0f;
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if ((zclk)&&(read_pending || write_pending))
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begin
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ctrl_state <= `ECTRL_ADDRESS;
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ctrl_state <= `ECTRL_ADDRESS;
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end end
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end end
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`ECTRL_ADDRESS: begin
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`ECTRL_ADDRESS: begin
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o_mdwe <= 1'b1; // Write
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o_mdwe <= 1'b1; // Write
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if ((zreg_pos)&&(zclk))
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if ((zreg_pos)&&(zclk))
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begin
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begin
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reg_pos <= 6'h10;
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reg_pos <= 6'h10;
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if (read_pending)
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if (read_pending)
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ctrl_state <= `ECTRL_READ;
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ctrl_state <= `ECTRL_READ;
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else
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else
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ctrl_state <= `ECTRL_WRITE;
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ctrl_state <= `ECTRL_WRITE;
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write_reg <= r_data;
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write_reg <= r_data;
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end end
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end end
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`ECTRL_READ: begin
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`ECTRL_READ: begin
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o_mdwe <= 1'b0; // Read
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o_mdwe <= 1'b0; // Read
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if ((zreg_pos)&&(zclk))
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if ((zreg_pos)&&(zclk))
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begin
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begin
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ctrl_state <= `ECTRL_IDLE;
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ctrl_state <= `ECTRL_IDLE;
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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end end
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end end
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`ECTRL_WRITE: begin
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`ECTRL_WRITE: begin
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o_mdwe <= 1'b1; // Write
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o_mdwe <= 1'b1; // Write
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if ((zreg_pos)&&(zclk))
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if ((zreg_pos)&&(zclk))
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begin
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begin
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ctrl_state <= `ECTRL_IDLE;
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ctrl_state <= `ECTRL_IDLE;
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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end end
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end end
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default: begin
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default: begin
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o_mdwe <= 1'b0; // Read
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o_mdwe <= 1'b0; // Read
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reg_pos <= 6'h3f;
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reg_pos <= 6'h3f;
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ctrl_state <= `ECTRL_RESET;
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ctrl_state <= `ECTRL_RESET;
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end
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end
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endcase
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endcase
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end
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end
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assign o_debug = {
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o_wb_stall,i_wb_stb,i_wb_we, i_wb_addr, // 8 bits
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o_wb_ack, rclk, o_wb_data[5:0], // 8 bits
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zreg_pos, zclk, reg_pos, // 8 bits
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read_pending, ctrl_state, // 4 bits
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o_mdclk, o_mdwe, o_mdio, i_mdio // 4 bits
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};
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endmodule
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endmodule
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