--! @file
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--! @file
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--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
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--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations.\n
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--! A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations.\n
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--! Most central processing units consist of a datapath and a control unit, with a large part of the control unit dedicated to
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--! Most central processing units consist of a datapath and a control unit, with a large part of the control unit dedicated to
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--! regulating the interaction between the datapath and main memory.
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--! regulating the interaction between the datapath and main memory.
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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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--! The purpose of datapaths is to provide routes for data to travel between functional units.
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entity DataPath is
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entity DataPath is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
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Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
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inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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clk : in STD_LOGIC; --! Clock signal
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clk : in STD_LOGIC; --! Clock signal
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outEn : in typeEnDis; --! Enable/Disable datapath output
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outEn : in typeEnDis; --! Enable/Disable datapath output
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aluOp : in aluOps; --! Alu operations
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aluOp : in aluOps; --! Alu operations
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muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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muxRegFile : in dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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end DataPath;
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end DataPath;
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--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
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--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
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--! @details This description will also show how to instantiate components(Alu, RegisterFile, Multiplexer) on your design
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--! @details This description will also show how to instantiate components(Alu, RegisterFile, Multiplexer) on your design
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architecture Behavioral of DataPath is
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architecture Behavioral of DataPath is
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--! Component declaration to instantiate the Multiplexer circuit
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--! Component declaration to instantiate the Multiplexer circuit
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COMPONENT Multiplexer4_1
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COMPONENT Multiplexer4_1
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
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D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
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E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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sel : in dpMuxInputs; --! Select inputs (1, 2, 3, 4, 5)
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sel : in dpMuxInputs; --! Select inputs (1, 2, 3, 4, 5)
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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END COMPONENT;
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END COMPONENT;
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--! Component declaration to instantiate the Multiplexer3_1 circuit
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--! Component declaration to instantiate the Multiplexer3_1 circuit
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COMPONENT Multiplexer3_1 is
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COMPONENT Multiplexer3_1 is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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sel : in STD_LOGIC_VECTOR(1 downto 0); --! Select inputs (1, 2, 3)
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sel : in dpMuxAluIn; --! Select inputs (fromMemory, fromImediate, fromRegFileA)
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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end COMPONENT;
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end COMPONENT;
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--! Component declaration to instantiate the Alu circuit
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--! Component declaration to instantiate the Alu circuit
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COMPONENT Alu
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COMPONENT Alu
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
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flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
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sel : in aluOps); --! Select operation
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sel : in aluOps); --! Select operation
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END COMPONENT;
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END COMPONENT;
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--! Component declaration to instantiate the testRegisterFile circuit
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--! Component declaration to instantiate the testRegisterFile circuit
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COMPONENT RegisterFile
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COMPONENT RegisterFile
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the registers)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the registers)
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Port ( clk : in STD_LOGIC; --! Clock signal
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Port ( clk : in STD_LOGIC; --! Clock signal
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writeEn : in STD_LOGIC; --! Write enable
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writeEn : in STD_LOGIC; --! Write enable
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writeAddr : in generalRegisters; --! Write Adress
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writeAddr : in generalRegisters; --! Write Adress
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input : in STD_LOGIC_VECTOR (n downto 0); --! Input
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input : in STD_LOGIC_VECTOR (n downto 0); --! Input
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Read_A_En : in STD_LOGIC; --! Enable read A
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Read_A_En : in STD_LOGIC; --! Enable read A
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Read_A_Addr : in generalRegisters; --! Read A adress
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Read_A_Addr : in generalRegisters; --! Read A adress
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Read_B_En : in STD_LOGIC; --! Enable read A
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Read_B_En : in STD_LOGIC; --! Enable read A
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Read_B_Addr : in generalRegisters; --! Read B adress
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Read_B_Addr : in generalRegisters; --! Read B adress
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A_Out : out STD_LOGIC_VECTOR (n downto 0); --! Output A
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A_Out : out STD_LOGIC_VECTOR (n downto 0); --! Output A
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B_Out : out STD_LOGIC_VECTOR (n downto 0)); --! Output B
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B_Out : out STD_LOGIC_VECTOR (n downto 0)); --! Output B
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END COMPONENT;
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END COMPONENT;
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COMPONENT TriStateBuffer
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COMPONENT TriStateBuffer
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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PORT(
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PORT(
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A : IN std_logic_vector(n downto 0); --! Buffer Input
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A : IN std_logic_vector(n downto 0); --! Buffer Input
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sel : IN typeEnDis; --! Enable or Disable the output
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sel : IN typeEnDis; --! Enable or Disable the output
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S : OUT std_logic_vector(n downto 0) --! Enable or Disable the output
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S : OUT std_logic_vector(n downto 0) --! Enable or Disable the output
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Signals that will connect the various components from the DataPath
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-- Signals that will connect the various components from the DataPath
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signal regFilePortA : STD_LOGIC_VECTOR (n downto 0);
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signal regFilePortA : STD_LOGIC_VECTOR (n downto 0);
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signal regFilePortB : STD_LOGIC_VECTOR (n downto 0);
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signal regFilePortB : STD_LOGIC_VECTOR (n downto 0);
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signal aluOut : STD_LOGIC_VECTOR (n downto 0);
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signal aluOut : STD_LOGIC_VECTOR (n downto 0);
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signal muxOut : STD_LOGIC_VECTOR (n downto 0);
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signal muxOut : STD_LOGIC_VECTOR (n downto 0);
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signal muxOutReg : STD_LOGIC_VECTOR (n downto 0);
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signal muxOutReg : STD_LOGIC_VECTOR (n downto 0);
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begin
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begin
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--! Instantiate Multiplexer 5:1
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--! Instantiate Multiplexer 5:1
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uMux: Multiplexer4_1 PORT MAP (
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uMux: Multiplexer4_1 PORT MAP (
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A => inputMm,
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A => inputMm,
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B => inputImm,
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B => inputImm,
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C => regFilePortA,
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C => regFilePortA,
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D => regFilePortB,
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D => regFilePortB,
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E => aluOut,
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E => aluOut,
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sel => muxSel,
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sel => muxSel,
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S => muxOut
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S => muxOut
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);
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);
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--! Instantiate Multiplexer 5:1
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--! Instantiate Multiplexer 5:1
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uMux2: Multiplexer3_1 PORT MAP (
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uMux2: Multiplexer3_1 PORT MAP (
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A => inputMm,
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A => inputMm,
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B => inputImm,
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B => inputImm,
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C => regFilePortA,
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C => regFilePortA,
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sel => muxRegFile,
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sel => muxRegFile,
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S => muxOutReg
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S => muxOutReg
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);
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);
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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uAlu: Alu PORT MAP (
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uAlu: Alu PORT MAP (
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A => muxOutReg,
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A => muxOutReg,
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B => regFilePortB,
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B => regFilePortB,
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S => aluOut,
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S => aluOut,
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flagsOut => dpFlags,
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flagsOut => dpFlags,
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sel => aluOp
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sel => aluOp
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);
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);
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--! Instantiate the Unit Under Test (RegisterFile) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (RegisterFile) (Doxygen bug if it's not commented!)
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uRegisterFile: RegisterFile PORT MAP (
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uRegisterFile: RegisterFile PORT MAP (
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clk => clk,
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clk => clk,
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writeEn => regFileWriteEn,
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writeEn => regFileWriteEn,
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writeAddr => regFileWriteAddr,
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writeAddr => regFileWriteAddr,
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input => muxOut,
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input => muxOut,
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Read_A_En => regFileEnA,
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Read_A_En => regFileEnA,
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Read_A_Addr => regFileReadAddrA,
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Read_A_Addr => regFileReadAddrA,
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Read_B_En => regFileEnB,
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Read_B_En => regFileEnB,
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Read_B_Addr => regFileReadAddrB,
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Read_B_Addr => regFileReadAddrB,
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A_Out => regFilePortA,
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A_Out => regFilePortA,
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B_Out => regFilePortB
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B_Out => regFilePortB
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);
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);
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--!Instantiate the Unit Under Test (Multiplexer2_1) (Doxygen bug if it's not commented!)
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--!Instantiate the Unit Under Test (Multiplexer2_1) (Doxygen bug if it's not commented!)
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uTriState: TriStateBuffer PORT MAP (
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uTriState: TriStateBuffer PORT MAP (
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A => muxOut,
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A => muxOut,
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sel => outEn,
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sel => outEn,
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S => outputDp
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S => outputDp
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);
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);
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end Behavioral;
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end Behavioral;
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