--! @file
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--! @file
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--! @brief Testbench for Alu
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--! @brief Testbench for Alu
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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ENTITY testAlu IS
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ENTITY testAlu IS
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END testAlu;
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END testAlu;
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--! @brief Alu Testbench file
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--! @brief Alu Testbench file
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--! @details Exercise each Alu operation to verify if the description work as planned
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--! @details Exercise each Alu operation to verify if the description work as planned
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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ARCHITECTURE behavior OF testAlu IS
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ARCHITECTURE behavior OF testAlu IS
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--! Component declaration to instantiate the Alu circuit
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--! Component declaration to instantiate the Alu circuit
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COMPONENT Alu
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COMPONENT Alu
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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sel : in aluOps); --! Select operation
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flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
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sel : in aluOps); --! Select operation --! Select operation
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal sel : aluOps := alu_sum; --! Wire to connect Test signal to component
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signal sel : aluOps := alu_sum; --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal flagsOut : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
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BEGIN
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BEGIN
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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uut: Alu PORT MAP (
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uut: Alu PORT MAP (
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A => A,
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A => A,
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B => B,
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B => B,
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S => S,
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S => S,
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flagsOut => flagsOut,
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sel => sel
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sel => sel
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);
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);
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--! Process that will stimulate all of the Alu operations
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--! Process that will stimulate all of the Alu operations
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stim_proc: process
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stim_proc: process
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variable mulResult : std_logic_vector(((nBits*2) - 1)downto 0);
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variable mulResult : std_logic_vector(((nBits*2) - 1)downto 0);
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begin
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begin
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-- Pass ---------------------------------------------------------------------------
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-- Pass ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "Pass input A to output" SEVERITY NOTE;
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REPORT "Pass input A to output" SEVERITY NOTE;
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sel <= alu_pass;
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sel <= alu_pass;
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A <= conv_std_logic_vector(22, nBits);
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A <= conv_std_logic_vector(22, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A ) report "Invalid Pass output" severity FAILURE;
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assert S = (A ) report "Invalid Pass output" severity FAILURE;
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-- Sum ---------------------------------------------------------------------------
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-- Sum ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "Sum without carry 12 AND 13" SEVERITY NOTE;
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REPORT "Sum without carry 12 AND 13" SEVERITY NOTE;
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sel <= alu_sum;
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sel <= alu_sum;
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A <= conv_std_logic_vector(12, nBits);
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A <= conv_std_logic_vector(12, nBits);
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B <= conv_std_logic_vector(13, nBits);
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B <= conv_std_logic_vector(13, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A + B) report "Invalid Sum output" severity FAILURE;
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assert S = (A + B) report "Invalid Sum output" severity FAILURE;
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-- Sub ---------------------------------------------------------------------------
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-- Sub ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "Sub without carry 34 AND 30" SEVERITY NOTE;
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REPORT "Sub without carry 34 AND 30" SEVERITY NOTE;
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sel <= alu_sub;
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sel <= alu_sub;
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A <= conv_std_logic_vector(34, nBits);
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A <= conv_std_logic_vector(34, nBits);
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B <= conv_std_logic_vector(30, nBits);
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B <= conv_std_logic_vector(30, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A - B) report "Invalid Sum Sub" severity FAILURE;
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assert S = (A - B) report "Invalid Sum Sub" severity FAILURE;
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-- Inc ---------------------------------------------------------------------------
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-- Inc ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "Inc without carry 1" SEVERITY NOTE;
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REPORT "Inc without carry 1" SEVERITY NOTE;
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sel <= alu_inc;
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sel <= alu_inc;
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A <= conv_std_logic_vector(1, nBits);
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A <= conv_std_logic_vector(1, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A + 1) report "Invalid Sum Sub" severity FAILURE;
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assert S = (A + 1) report "Invalid Sum Sub" severity FAILURE;
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-- Dec ---------------------------------------------------------------------------
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-- Dec ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "Dec without carry 1" SEVERITY NOTE;
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REPORT "Dec without carry 1" SEVERITY NOTE;
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sel <= alu_dec;
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sel <= alu_dec;
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A <= conv_std_logic_vector(1, nBits);
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A <= conv_std_logic_vector(1, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A - 1) report "Invalid Sum Sub" severity FAILURE;
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assert S = (A - 1) report "Invalid Sum Sub" severity FAILURE;
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-- Mul ---------------------------------------------------------------------------
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-- Mul ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "Sub without carry 34 AND 30" SEVERITY NOTE;
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REPORT "Sub without carry 34 AND 30" SEVERITY NOTE;
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sel <= alu_mul;
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sel <= alu_mul;
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A <= conv_std_logic_vector(3, nBits);
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A <= conv_std_logic_vector(3, nBits);
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B <= conv_std_logic_vector(5, nBits);
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B <= conv_std_logic_vector(5, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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mulResult := (A * B);
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mulResult := (A * B);
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assert S = (mulResult((nBits - 1) downto 0)) report "Invalid Sum Sub" severity FAILURE;
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assert S = (mulResult((nBits - 1) downto 0)) report "Invalid Sum Sub" severity FAILURE;
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-- AND ---------------------------------------------------------------------------
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-- AND ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "AND without carry 2(10) AND 3(11)" SEVERITY NOTE;
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REPORT "AND without carry 2(10) AND 3(11)" SEVERITY NOTE;
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sel <= alu_and;
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sel <= alu_and;
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A <= conv_std_logic_vector(2, nBits);
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A <= conv_std_logic_vector(2, nBits);
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B <= conv_std_logic_vector(3, nBits);
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B <= conv_std_logic_vector(3, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A and B) report "Invalid AND output" severity FAILURE;
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assert S = (A and B) report "Invalid AND output" severity FAILURE;
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-- OR ---------------------------------------------------------------------------
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-- OR ---------------------------------------------------------------------------
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wait for 1 ns;
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wait for 1 ns;
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REPORT "OR without carry 5 OR 7" SEVERITY NOTE;
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REPORT "OR without carry 5 OR 7" SEVERITY NOTE;
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sel <= alu_or;
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sel <= alu_or;
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A <= conv_std_logic_vector(5, nBits);
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A <= conv_std_logic_vector(5, nBits);
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B <= conv_std_logic_vector(7, nBits);
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B <= conv_std_logic_vector(7, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A or B) report "Invalid OR output" severity FAILURE;
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assert S = (A or B) report "Invalid OR output" severity FAILURE;
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-- XOR ---------------------------------------------------------------------------
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-- XOR ---------------------------------------------------------------------------
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wait for 1 ns;
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wait for 1 ns;
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REPORT "OR without carry 11 XOR 9" SEVERITY NOTE;
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REPORT "OR without carry 11 XOR 9" SEVERITY NOTE;
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sel <= alu_xor;
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sel <= alu_xor;
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A <= conv_std_logic_vector(11, nBits);
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A <= conv_std_logic_vector(11, nBits);
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B <= conv_std_logic_vector(9, nBits);
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B <= conv_std_logic_vector(9, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (A xor B) report "Invalid XOR output" severity FAILURE;
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assert S = (A xor B) report "Invalid XOR output" severity FAILURE;
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-- NOT ---------------------------------------------------------------------------
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-- NOT ---------------------------------------------------------------------------
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wait for 1 ns;
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wait for 1 ns;
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REPORT "NOT 10" SEVERITY NOTE;
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REPORT "NOT 10" SEVERITY NOTE;
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sel <= alu_not;
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sel <= alu_not;
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A <= conv_std_logic_vector(10, nBits);
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A <= conv_std_logic_vector(10, nBits);
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B <= (others => 'X');
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B <= (others => 'X');
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (not A) report "Invalid NOT output" severity FAILURE;
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assert S = (not A) report "Invalid NOT output" severity FAILURE;
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-- Shift left---------------------------------------------------------------------
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wait for 1 ns;
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REPORT "Shift left 2" SEVERITY NOTE;
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sel <= alu_shfLt;
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A <= conv_std_logic_vector(2, nBits);
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B <= (others => 'X');
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wait for 1 ns; -- Wait to stabilize the response
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assert S = conv_std_logic_vector(4, nBits) report "Invalid shift left output expected " severity FAILURE;
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-- Shift right---------------------------------------------------------------------
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wait for 1 ns;
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REPORT "Shift right 4" SEVERITY NOTE;
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sel <= alu_shfRt;
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A <= conv_std_logic_vector(4, nBits);
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B <= (others => 'X');
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wait for 1 ns; -- Wait to stabilize the response
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assert S = conv_std_logic_vector(2, nBits) report "Invalid shift left output expected " severity FAILURE;
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-- Test flag zero ------------------------------------------------------------------
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wait for 1 ps;
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REPORT "Test zero flag 10 sub 10" SEVERITY NOTE;
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sel <= alu_sub;
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A <= conv_std_logic_vector(10, nBits);
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B <= conv_std_logic_vector(10, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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assert flagsOut(flag_zero) = '1' report "Invalid zero flag" severity FAILURE;
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-- Test flag carry ------------------------------------------------------------------
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wait for 1 ps;
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REPORT "Test carry flag 4294967056 sum 4294967056" SEVERITY NOTE;
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sel <= alu_sum;
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A <= "11111111111111111111111100010000";
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B <= "11111111111111111111111100010000";
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wait for 1 ns; -- Wait to stabilize the response
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assert flagsOut(flag_carry) = '1' report "Invalid carry flag" severity FAILURE;
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-- Test flag sign ------------------------------------------------------------------
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wait for 1 ps;
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REPORT "Test sign flag -4 sub 4" SEVERITY NOTE;
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sel <= alu_sub;
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A <= conv_std_logic_vector(-4, nBits);
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B <= conv_std_logic_vector(4, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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assert flagsOut(flag_sign) = '1' report "Invalid sign flag" severity FAILURE;
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assert S = conv_std_logic_vector(-8, nBits) report "Invalid Sub" severity FAILURE;
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-- Finish simulation
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-- Finish simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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END;
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END;
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