//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2011 Authors
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// Copyright (C) 2011 Authors
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_system_1.v
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// *File Name: omsp_system_1.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 System 0.
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// openMSP430 System 0.
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// This core is dedicated to communication and
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// This core is dedicated to communication and
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// display (i.e. UART, LEDs and 7-segment modport)
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// display (i.e. UART, LEDs and 7-segment modport)
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// It can also read the switches value.
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// It can also read the switches value.
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "openmsp430/openMSP430_defines.v"
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`include "openmsp430/openMSP430_defines.v"
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module omsp_system_0 (
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module omsp_system_0 (
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// Clock & Reset
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// Clock & Reset
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dco_clk, // Fast oscillator (fast clock)
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dco_clk, // Fast oscillator (fast clock)
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reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
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reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
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// Serial Debug Interface (I2C)
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// Serial Debug Interface (I2C)
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dbg_i2c_addr, // Debug interface: I2C Address
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dbg_i2c_addr, // Debug interface: I2C Address
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
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dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
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// Data Memory
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// Data Memory
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dmem_addr, // Data Memory address
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dmem_addr, // Data Memory address
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dmem_cen, // Data Memory chip enable (low active)
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dmem_cen, // Data Memory chip enable (low active)
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dmem_din, // Data Memory data input
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dmem_din, // Data Memory data input
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dmem_wen, // Data Memory write enable (low active)
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dmem_wen, // Data Memory write enable (low active)
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dmem_dout, // Data Memory data output
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dmem_dout, // Data Memory data output
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// Program Memory
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// Program Memory
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pmem_addr, // Program Memory address
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pmem_addr, // Program Memory address
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pmem_cen, // Program Memory chip enable (low active)
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pmem_cen, // Program Memory chip enable (low active)
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pmem_din, // Program Memory data input (optional)
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pmem_din, // Program Memory data input (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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pmem_dout, // Program Memory data output
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pmem_dout, // Program Memory data output
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// UART
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// UART
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uart_rxd, // UART Data Receive (RXD)
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uart_rxd, // UART Data Receive (RXD)
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uart_txd, // UART Data Transmit (TXD)
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uart_txd, // UART Data Transmit (TXD)
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// Switches & LEDs
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// Switches & LEDs
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switch, // Input switches
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switch, // Input switches
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led // LEDs
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led // LEDs
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);
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);
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// Clock & Reset
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// Clock & Reset
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input dco_clk; // Fast oscillator (fast clock)
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input dco_clk; // Fast oscillator (fast clock)
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input reset_n; // Reset Pin (low active, asynchronous and non-glitchy)
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input reset_n; // Reset Pin (low active, asynchronous and non-glitchy)
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// Serial Debug Interface (I2C)
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// Serial Debug Interface (I2C)
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input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
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input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
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output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
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// Data Memory
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// Data Memory
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input [15:0] dmem_dout; // Data Memory data output
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input [15:0] dmem_dout; // Data Memory data output
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output [`DMEM_MSB:0] dmem_addr; // Data Memory address
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output [`DMEM_MSB:0] dmem_addr; // Data Memory address
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output dmem_cen; // Data Memory chip enable (low active)
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output dmem_cen; // Data Memory chip enable (low active)
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output [15:0] dmem_din; // Data Memory data input
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output [15:0] dmem_din; // Data Memory data input
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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// Program Memory
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// Program Memory
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input [15:0] pmem_dout; // Program Memory data output
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input [15:0] pmem_dout; // Program Memory data output
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output pmem_cen; // Program Memory chip enable (low active)
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output pmem_cen; // Program Memory chip enable (low active)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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// UART
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// UART
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input uart_rxd; // UART Data Receive (RXD)
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input uart_rxd; // UART Data Receive (RXD)
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output uart_txd; // UART Data Transmit (TXD)
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output uart_txd; // UART Data Transmit (TXD)
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// Switches & LEDs
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// Switches & LEDs
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input [3:0] switch; // Input switches
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input [3:0] switch; // Input switches
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output [1:0] led; // LEDs
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output [1:0] led; // LEDs
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//=============================================================================
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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//=============================================================================
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// Clock & Reset
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// Clock & Reset
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wire mclk;
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wire mclk;
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wire aclk_en;
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wire aclk_en;
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wire smclk_en;
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wire smclk_en;
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wire puc_rst;
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wire puc_rst;
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// Debug interface
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// Debug interface
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wire dbg_freeze;
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wire dbg_freeze;
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// Data memory
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// Data memory
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wire [`DMEM_MSB:0] dmem_addr;
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wire [`DMEM_MSB:0] dmem_addr;
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wire dmem_cen;
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wire dmem_cen;
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wire [15:0] dmem_din;
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wire [15:0] dmem_din;
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wire [1:0] dmem_wen;
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wire [1:0] dmem_wen;
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wire [15:0] dmem_dout;
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wire [15:0] dmem_dout;
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// Program memory
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// Program memory
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wire [`PMEM_MSB:0] pmem_addr;
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wire [`PMEM_MSB:0] pmem_addr;
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wire pmem_cen;
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wire pmem_cen;
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wire [15:0] pmem_din;
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wire [15:0] pmem_din;
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wire [1:0] pmem_wen;
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wire [1:0] pmem_wen;
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wire [15:0] pmem_dout;
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wire [15:0] pmem_dout;
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// Peripheral bus
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// Peripheral bus
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wire [13:0] per_addr;
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wire [13:0] per_addr;
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wire [15:0] per_din;
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wire [15:0] per_din;
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wire [1:0] per_we;
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wire [1:0] per_we;
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wire per_en;
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wire per_en;
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wire [15:0] per_dout;
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wire [15:0] per_dout;
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// Interrupts
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// Interrupts
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wire [13:0] irq_acc;
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wire [13:0] irq_acc;
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wire [13:0] irq_bus;
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wire [13:0] irq_bus;
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wire nmi;
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wire nmi;
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// GPIO
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// GPIO
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wire [7:0] p1_din;
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wire [7:0] p1_din;
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wire [7:0] p1_dout;
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wire [7:0] p1_dout;
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wire [7:0] p1_dout_en;
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wire [7:0] p1_dout_en;
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wire [7:0] p1_sel;
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wire [7:0] p1_sel;
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wire [7:0] p2_din;
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wire [7:0] p2_din;
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wire [7:0] p2_dout;
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wire [7:0] p2_dout;
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wire [7:0] p2_dout_en;
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wire [7:0] p2_dout_en;
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wire [7:0] p2_sel;
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wire [7:0] p2_sel;
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wire [15:0] per_dout_gpio;
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wire [15:0] per_dout_gpio;
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// Timer A
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// Timer A
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wire [15:0] per_dout_tA;
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wire [15:0] per_dout_tA;
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// Hardware UART
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// Hardware UART
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wire [15:0] per_dout_uart;
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wire [15:0] per_dout_uart;
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//=============================================================================
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//=============================================================================
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// 2) OPENMSP430 CORE
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// 2) OPENMSP430 CORE
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//=============================================================================
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//=============================================================================
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openMSP430 #(.INST_NR (0),
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openMSP430 #(.INST_NR (0),
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.TOTAL_NR(1)) openMSP430_0 (
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.TOTAL_NR(1)) openMSP430_0 (
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// OUTPUTs
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// OUTPUTs
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.aclk (), // ASIC ONLY: ACLK
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.aclk (), // ASIC ONLY: ACLK
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.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
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.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
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.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
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.dbg_uart_txd (), // Debug interface: UART TXD
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.dbg_uart_txd (), // Debug interface: UART TXD
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.dco_enable (), // ASIC ONLY: Fast oscillator enable
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.dco_enable (), // ASIC ONLY: Fast oscillator enable
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.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_din (dmem_din), // Data Memory data input
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.dmem_din (dmem_din), // Data Memory data input
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.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
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.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
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.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
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.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.dma_dout (), // Direct Memory Access data output
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.dma_ready (), // Direct Memory Access is complete
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.dma_resp (), // Direct Memory Access response (0:Okay / 1:Error)
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.puc_rst (puc_rst), // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.smclk (), // ASIC ONLY: SMCLK
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.smclk (), // ASIC ONLY: SMCLK
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.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
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.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
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// INPUTs
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// INPUTs
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.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
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.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
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.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
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.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
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.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
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.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
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.dbg_uart_rxd (1'b1), // Debug interface: UART RXD (asynchronous)
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.dbg_uart_rxd (1'b1), // Debug interface: UART RXD (asynchronous)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_bus), // Maskable interrupts
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.irq (irq_bus), // Maskable interrupts
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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.dma_addr (15'h0000), // Direct Memory Access address
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.dma_din (16'h0000), // Direct Memory Access data input
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.dma_en (1'b0), // Direct Memory Access enable (high active)
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.dma_priority (1'b0), // Direct Memory Access priority (0:low / 1:high)
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.dma_we (2'b00), // Direct Memory Access write byte enable (high active)
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.dma_wkup (1'b0), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.per_dout (per_dout), // Peripheral data output
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.per_dout (per_dout), // Peripheral data output
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.pmem_dout (pmem_dout), // Program Memory data output
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.pmem_dout (pmem_dout), // Program Memory data output
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.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
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.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
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.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
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.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
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.scan_mode (1'b0), // ASIC ONLY: Scan mode
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.scan_mode (1'b0), // ASIC ONLY: Scan mode
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.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
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.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
|
);
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);
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|
|
|
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//=============================================================================
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//=============================================================================
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// 3) OPENMSP430 PERIPHERALS
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// 3) OPENMSP430 PERIPHERALS
|
//=============================================================================
|
//=============================================================================
|
|
|
//
|
//
|
// Digital I/O
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// Digital I/O
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//-------------------------------
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//-------------------------------
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|
|
omsp_gpio #(.P1_EN(1),
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omsp_gpio #(.P1_EN(1),
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.P2_EN(1),
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.P2_EN(1),
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.P3_EN(0),
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.P3_EN(0),
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.P4_EN(0),
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.P4_EN(0),
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.P5_EN(0),
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.P5_EN(0),
|
.P6_EN(0)) gpio_0 (
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.P6_EN(0)) gpio_0 (
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|
|
// OUTPUTs
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// OUTPUTs
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.irq_port1 (irq_port1), // Port 1 interrupt
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.irq_port1 (irq_port1), // Port 1 interrupt
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.irq_port2 (irq_port2), // Port 2 interrupt
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.irq_port2 (irq_port2), // Port 2 interrupt
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.p1_dout (p1_dout), // Port 1 data output
|
.p1_dout (p1_dout), // Port 1 data output
|
.p1_dout_en (p1_dout_en), // Port 1 data output enable
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.p1_dout_en (p1_dout_en), // Port 1 data output enable
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.p1_sel (p1_sel), // Port 1 function select
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.p1_sel (p1_sel), // Port 1 function select
|
.p2_dout (p2_dout), // Port 2 data output
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.p2_dout (p2_dout), // Port 2 data output
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.p2_dout_en (p2_dout_en), // Port 2 data output enable
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.p2_dout_en (p2_dout_en), // Port 2 data output enable
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.p2_sel (p2_sel), // Port 2 function select
|
.p2_sel (p2_sel), // Port 2 function select
|
.p3_dout (), // Port 3 data output
|
.p3_dout (), // Port 3 data output
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.p3_dout_en (), // Port 3 data output enable
|
.p3_dout_en (), // Port 3 data output enable
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.p3_sel (), // Port 3 function select
|
.p3_sel (), // Port 3 function select
|
.p4_dout (), // Port 4 data output
|
.p4_dout (), // Port 4 data output
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.p4_dout_en (), // Port 4 data output enable
|
.p4_dout_en (), // Port 4 data output enable
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.p4_sel (), // Port 4 function select
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.p4_sel (), // Port 4 function select
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.p5_dout (), // Port 5 data output
|
.p5_dout (), // Port 5 data output
|
.p5_dout_en (), // Port 5 data output enable
|
.p5_dout_en (), // Port 5 data output enable
|
.p5_sel (), // Port 5 function select
|
.p5_sel (), // Port 5 function select
|
.p6_dout (), // Port 6 data output
|
.p6_dout (), // Port 6 data output
|
.p6_dout_en (), // Port 6 data output enable
|
.p6_dout_en (), // Port 6 data output enable
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.p6_sel (), // Port 6 function select
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.p6_sel (), // Port 6 function select
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.per_dout (per_dout_gpio), // Peripheral data output
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.per_dout (per_dout_gpio), // Peripheral data output
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|
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// INPUTs
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// INPUTs
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.p1_din (p1_din), // Port 1 data input
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.p1_din (p1_din), // Port 1 data input
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.p2_din (p2_din), // Port 2 data input
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.p2_din (p2_din), // Port 2 data input
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.p3_din (8'h00), // Port 3 data input
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.p3_din (8'h00), // Port 3 data input
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.p4_din (8'h00), // Port 4 data input
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.p4_din (8'h00), // Port 4 data input
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.p5_din (8'h00), // Port 5 data input
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.p5_din (8'h00), // Port 5 data input
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.p6_din (8'h00), // Port 6 data input
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.p6_din (8'h00), // Port 6 data input
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc_rst (puc_rst) // Main system reset
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.puc_rst (puc_rst) // Main system reset
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);
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);
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|
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// Assign LEDs
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// Assign LEDs
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assign led = p2_dout[1:0] & p2_dout_en[1:0];
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assign led = p2_dout[1:0] & p2_dout_en[1:0];
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|
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// Assign Switches
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// Assign Switches
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assign p1_din[7:4] = 4'h0;
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assign p1_din[7:4] = 4'h0;
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assign p1_din[3:0] = switch;
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assign p1_din[3:0] = switch;
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|
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//
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//
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// Timer A
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// Timer A
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//----------------------------------------------
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//----------------------------------------------
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|
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omsp_timerA timerA_0 (
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omsp_timerA timerA_0 (
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|
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// OUTPUTs
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// OUTPUTs
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.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
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.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
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.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
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.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
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.per_dout (per_dout_tA), // Peripheral data output
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.per_dout (per_dout_tA), // Peripheral data output
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.ta_out0 (), // Timer A output 0
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.ta_out0 (), // Timer A output 0
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.ta_out0_en (), // Timer A output 0 enable
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.ta_out0_en (), // Timer A output 0 enable
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.ta_out1 (), // Timer A output 1
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.ta_out1 (), // Timer A output 1
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.ta_out1_en (), // Timer A output 1 enable
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.ta_out1_en (), // Timer A output 1 enable
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.ta_out2 (), // Timer A output 2
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.ta_out2 (), // Timer A output 2
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.ta_out2_en (), // Timer A output 2 enable
|
.ta_out2_en (), // Timer A output 2 enable
|
|
|
// INPUTs
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// INPUTs
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.aclk_en (aclk_en), // ACLK enable (from CPU)
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.aclk_en (aclk_en), // ACLK enable (from CPU)
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.dbg_freeze (dbg_freeze), // Freeze Timer A counter
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.dbg_freeze (dbg_freeze), // Freeze Timer A counter
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.inclk (1'b0), // INCLK external timer clock (SLOW)
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.inclk (1'b0), // INCLK external timer clock (SLOW)
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.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
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.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
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.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.ta_cci0a (1'b0), // Timer A capture 0 input A
|
.ta_cci0a (1'b0), // Timer A capture 0 input A
|
.ta_cci0b (1'b0), // Timer A capture 0 input B
|
.ta_cci0b (1'b0), // Timer A capture 0 input B
|
.ta_cci1a (1'b0), // Timer A capture 1 input A
|
.ta_cci1a (1'b0), // Timer A capture 1 input A
|
.ta_cci1b (1'b0), // Timer A capture 1 input B
|
.ta_cci1b (1'b0), // Timer A capture 1 input B
|
.ta_cci2a (1'b0), // Timer A capture 2 input A
|
.ta_cci2a (1'b0), // Timer A capture 2 input A
|
.ta_cci2b (1'b0), // Timer A capture 2 input B
|
.ta_cci2b (1'b0), // Timer A capture 2 input B
|
.taclk (1'b0) // TACLK external timer clock (SLOW)
|
.taclk (1'b0) // TACLK external timer clock (SLOW)
|
);
|
);
|
|
|
|
|
//
|
//
|
// Hardware UART
|
// Hardware UART
|
//----------------------------------------------
|
//----------------------------------------------
|
|
|
omsp_uart uart_0 (
|
omsp_uart uart_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.irq_uart_rx (irq_uart_rx), // UART receive interrupt
|
.irq_uart_rx (irq_uart_rx), // UART receive interrupt
|
.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
|
.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
|
.per_dout (per_dout_uart), // Peripheral data output
|
.per_dout (per_dout_uart), // Peripheral data output
|
.uart_txd (uart_txd), // UART Data Transmit (TXD)
|
.uart_txd (uart_txd), // UART Data Transmit (TXD)
|
|
|
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
.uart_rxd (uart_rxd) // UART Data Receive (RXD)
|
.uart_rxd (uart_rxd) // UART Data Receive (RXD)
|
);
|
);
|
|
|
|
|
//
|
//
|
// Combine peripheral data buses
|
// Combine peripheral data buses
|
//-------------------------------
|
//-------------------------------
|
|
|
assign per_dout = per_dout_gpio |
|
assign per_dout = per_dout_gpio |
|
per_dout_uart |
|
per_dout_uart |
|
per_dout_tA;
|
per_dout_tA;
|
|
|
//
|
//
|
// Assign interrupts
|
// Assign interrupts
|
//-------------------------------
|
//-------------------------------
|
|
|
assign nmi = 1'b0;
|
assign nmi = 1'b0;
|
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
|
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
irq_ta0, // Vector 9 (0xFFF2)
|
irq_ta0, // Vector 9 (0xFFF2)
|
irq_ta1, // Vector 8 (0xFFF0)
|
irq_ta1, // Vector 8 (0xFFF0)
|
irq_uart_rx, // Vector 7 (0xFFEE)
|
irq_uart_rx, // Vector 7 (0xFFEE)
|
irq_uart_tx, // Vector 6 (0xFFEC)
|
irq_uart_tx, // Vector 6 (0xFFEC)
|
1'b0, // Vector 5 (0xFFEA) - Reserved (Timer-A 0 from system 1)
|
1'b0, // Vector 5 (0xFFEA) - Reserved (Timer-A 0 from system 1)
|
1'b0, // Vector 4 (0xFFE8) - Reserved (Timer-A 1 from system 1)
|
1'b0, // Vector 4 (0xFFE8) - Reserved (Timer-A 1 from system 1)
|
irq_port2, // Vector 3 (0xFFE6)
|
irq_port2, // Vector 3 (0xFFE6)
|
irq_port1, // Vector 2 (0xFFE4)
|
irq_port1, // Vector 2 (0xFFE4)
|
1'b0, // Vector 1 (0xFFE2) - Reserved (Port 2 from system 1)
|
1'b0, // Vector 1 (0xFFE2) - Reserved (Port 2 from system 1)
|
1'b0}; // Vector 0 (0xFFE0) - Reserved (Port 1 from system 1)
|
1'b0}; // Vector 0 (0xFFE0) - Reserved (Port 1 from system 1)
|
|
|
|
|
endmodule // omsp_system_0
|
endmodule // omsp_system_0
|
|
|
|
|
|
|
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No newline at end of file
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No newline at end of file
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