//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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// Copyright (C) 2009 , Olivier Girard
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// modification, are permitted provided that the following conditions
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// are met:
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// are met:
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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// without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_dbg_i2c.v
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// *File Name: omsp_dbg_i2c.v
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//
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//
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// *Module Description:
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// *Module Description:
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// Debug I2C Slave communication interface
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// Debug I2C Slave communication interface
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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module omsp_dbg_i2c (
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module omsp_dbg_i2c (
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// OUTPUTs
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// OUTPUTs
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dbg_addr, // Debug register address
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dbg_addr, // Debug register address
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dbg_din, // Debug register data input
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dbg_din, // Debug register data input
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dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
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dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
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dbg_rd, // Debug register data read
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dbg_rd, // Debug register data read
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dbg_wr, // Debug register data write
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dbg_wr, // Debug register data write
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// INPUTs
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// INPUTs
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dbg_clk, // Debug unit clock
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dbg_clk, // Debug unit clock
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dbg_dout, // Debug register data output
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dbg_dout, // Debug register data output
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dbg_i2c_addr, // Debug interface: I2C ADDRESS
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dbg_i2c_addr, // Debug interface: I2C ADDRESS
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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dbg_rd_rdy, // Debug register data is ready for read
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dbg_rst, // Debug unit reset
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dbg_rst, // Debug unit reset
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mem_burst, // Burst on going
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mem_burst, // Burst on going
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mem_burst_end, // End TX/RX burst
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mem_burst_end, // End TX/RX burst
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mem_burst_rd, // Start TX burst
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mem_burst_rd, // Start TX burst
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mem_burst_wr, // Start RX burst
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mem_burst_wr, // Start RX burst
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mem_bw // Burst byte width
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mem_bw // Burst byte width
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [5:0] dbg_addr; // Debug register address
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output [5:0] dbg_addr; // Debug register address
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output [15:0] dbg_din; // Debug register data input
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output [15:0] dbg_din; // Debug register data input
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output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
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output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
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output dbg_rd; // Debug register data read
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output dbg_rd; // Debug register data read
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output dbg_wr; // Debug register data write
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output dbg_wr; // Debug register data write
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// INPUTs
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// INPUTs
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//=========
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//=========
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input dbg_clk; // Debug unit clock
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input dbg_clk; // Debug unit clock
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input [15:0] dbg_dout; // Debug register data output
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input [15:0] dbg_dout; // Debug register data output
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input [6:0] dbg_i2c_addr; // Debug interface: I2C ADDRESS
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input [6:0] dbg_i2c_addr; // Debug interface: I2C ADDRESS
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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input dbg_rd_rdy; // Debug register data is ready for read
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input dbg_rst; // Debug unit reset
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input dbg_rst; // Debug unit reset
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input mem_burst; // Burst on going
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input mem_burst; // Burst on going
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input mem_burst_end; // End TX/RX burst
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input mem_burst_end; // End TX/RX burst
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input mem_burst_rd; // Start TX burst
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input mem_burst_rd; // Start TX burst
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input mem_burst_wr; // Start RX burst
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input mem_burst_wr; // Start RX burst
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input mem_bw; // Burst byte width
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input mem_bw; // Burst byte width
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//=============================================================================
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//=============================================================================
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// 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING
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// 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING
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//=============================================================================
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//=============================================================================
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// Synchronize SCL/SDA inputs
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// Synchronize SCL/SDA inputs
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//--------------------------------
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//--------------------------------
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wire scl_sync_n;
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wire scl_sync_n;
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omsp_sync_cell sync_cell_i2c_scl (
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omsp_sync_cell sync_cell_i2c_scl (
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.data_out (scl_sync_n),
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.data_out (scl_sync_n),
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.data_in (~dbg_i2c_scl),
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.data_in (~dbg_i2c_scl),
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.clk (dbg_clk),
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.clk (dbg_clk),
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.rst (dbg_rst)
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.rst (dbg_rst)
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);
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);
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wire scl_sync = ~scl_sync_n;
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wire scl_sync = ~scl_sync_n;
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wire sda_in_sync_n;
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wire sda_in_sync_n;
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omsp_sync_cell sync_cell_i2c_sda (
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omsp_sync_cell sync_cell_i2c_sda (
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.data_out (sda_in_sync_n),
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.data_out (sda_in_sync_n),
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.data_in (~dbg_i2c_sda_in),
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.data_in (~dbg_i2c_sda_in),
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.clk (dbg_clk),
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.clk (dbg_clk),
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.rst (dbg_rst)
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.rst (dbg_rst)
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);
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);
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wire sda_in_sync = ~sda_in_sync_n;
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wire sda_in_sync = ~sda_in_sync_n;
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// SCL/SDA input buffers
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// SCL/SDA input buffers
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//--------------------------------
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//--------------------------------
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reg [1:0] scl_buf;
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reg [1:0] scl_buf;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) scl_buf <= 2'h3;
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if (dbg_rst) scl_buf <= 2'h3;
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else scl_buf <= {scl_buf[0], scl_sync};
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else scl_buf <= {scl_buf[0], scl_sync};
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reg [1:0] sda_in_buf;
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reg [1:0] sda_in_buf;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) sda_in_buf <= 2'h3;
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if (dbg_rst) sda_in_buf <= 2'h3;
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else sda_in_buf <= {sda_in_buf[0], sda_in_sync};
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else sda_in_buf <= {sda_in_buf[0], sda_in_sync};
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// SCL/SDA Majority decision
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// SCL/SDA Majority decision
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//------------------------------
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//------------------------------
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wire scl = (scl_sync & scl_buf[0]) |
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wire scl = (scl_sync & scl_buf[0]) |
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(scl_sync & scl_buf[1]) |
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(scl_sync & scl_buf[1]) |
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(scl_buf[0] & scl_buf[1]);
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(scl_buf[0] & scl_buf[1]);
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wire sda_in = (sda_in_sync & sda_in_buf[0]) |
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wire sda_in = (sda_in_sync & sda_in_buf[0]) |
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(sda_in_sync & sda_in_buf[1]) |
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(sda_in_sync & sda_in_buf[1]) |
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(sda_in_buf[0] & sda_in_buf[1]);
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(sda_in_buf[0] & sda_in_buf[1]);
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// SCL/SDA Edge detection
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// SCL/SDA Edge detection
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//------------------------------
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//------------------------------
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// SDA Edge detection
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// SDA Edge detection
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reg sda_in_dly;
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reg sda_in_dly;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) sda_in_dly <= 1'b1;
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if (dbg_rst) sda_in_dly <= 1'b1;
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else sda_in_dly <= sda_in;
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else sda_in_dly <= sda_in;
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wire sda_in_fe = sda_in_dly & ~sda_in;
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wire sda_in_fe = sda_in_dly & ~sda_in;
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wire sda_in_re = ~sda_in_dly & sda_in;
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wire sda_in_re = ~sda_in_dly & sda_in;
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wire sda_in_edge = sda_in_dly ^ sda_in;
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wire sda_in_edge = sda_in_dly ^ sda_in;
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// SCL Edge detection
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// SCL Edge detection
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reg scl_dly;
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reg scl_dly;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) scl_dly <= 1'b1;
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if (dbg_rst) scl_dly <= 1'b1;
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else scl_dly <= scl;
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else scl_dly <= scl;
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wire scl_fe = scl_dly & ~scl;
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wire scl_fe = scl_dly & ~scl;
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wire scl_re = ~scl_dly & scl;
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wire scl_re = ~scl_dly & scl;
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wire scl_edge = scl_dly ^ scl;
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wire scl_edge = scl_dly ^ scl;
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// Delayed SCL Rising-Edge for SDA data sampling
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// Delayed SCL Rising-Edge for SDA data sampling
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reg [1:0] scl_re_dly;
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reg [1:0] scl_re_dly;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) scl_re_dly <= 2'b00;
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if (dbg_rst) scl_re_dly <= 2'b00;
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else scl_re_dly <= {scl_re_dly[0], scl_re};
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else scl_re_dly <= {scl_re_dly[0], scl_re};
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wire scl_sample = scl_re_dly[1];
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wire scl_sample = scl_re_dly[1];
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//=============================================================================
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//=============================================================================
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// 2) I2C START & STOP CONDITION DETECTION
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// 2) I2C START & STOP CONDITION DETECTION
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//=============================================================================
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//=============================================================================
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//-----------------
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//-----------------
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// Start condition
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// Start condition
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//-----------------
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//-----------------
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wire start_detect = sda_in_fe & scl;
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wire start_detect = sda_in_fe & scl;
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//-----------------
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//-----------------
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// Stop condition
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// Stop condition
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//-----------------
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//-----------------
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wire stop_detect = sda_in_re & scl;
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wire stop_detect = sda_in_re & scl;
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//-----------------
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//-----------------
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// I2C Slave Active
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// I2C Slave Active
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//-----------------
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//-----------------
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// The I2C logic will be activated whenever a start condition
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// The I2C logic will be activated whenever a start condition
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// is detected and will be disactivated if the slave address
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// is detected and will be disactivated if the slave address
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// doesn't match or if a stop condition is detected.
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// doesn't match or if a stop condition is detected.
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wire i2c_addr_not_valid;
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wire i2c_addr_not_valid;
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reg i2c_active_seq;
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reg i2c_active_seq;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) i2c_active_seq <= 1'b0;
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if (dbg_rst) i2c_active_seq <= 1'b0;
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else if (start_detect) i2c_active_seq <= 1'b1;
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else if (start_detect) i2c_active_seq <= 1'b1;
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else if (stop_detect || i2c_addr_not_valid) i2c_active_seq <= 1'b0;
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else if (stop_detect || i2c_addr_not_valid) i2c_active_seq <= 1'b0;
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wire i2c_active = i2c_active_seq & ~stop_detect;
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wire i2c_active = i2c_active_seq & ~stop_detect;
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wire i2c_init = ~i2c_active | start_detect;
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wire i2c_init = ~i2c_active | start_detect;
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//=============================================================================
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//=============================================================================
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// 3) I2C STATE MACHINE
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// 3) I2C STATE MACHINE
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//=============================================================================
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//=============================================================================
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// State register/wires
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// State register/wires
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reg [2:0] i2c_state;
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reg [2:0] i2c_state;
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reg [2:0] i2c_state_nxt;
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reg [2:0] i2c_state_nxt;
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// Utility signals
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// Utility signals
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reg [8:0] shift_buf;
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reg [8:0] shift_buf;
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wire shift_rx_done;
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wire shift_rx_done;
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wire shift_tx_done;
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wire shift_tx_done;
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reg dbg_rd;
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reg dbg_rd;
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// State machine definition
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// State machine definition
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parameter RX_ADDR = 3'h0;
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parameter RX_ADDR = 3'h0;
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parameter RX_ADDR_ACK = 3'h1;
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parameter RX_ADDR_ACK = 3'h1;
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parameter RX_DATA = 3'h2;
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parameter RX_DATA = 3'h2;
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parameter RX_DATA_ACK = 3'h3;
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parameter RX_DATA_ACK = 3'h3;
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parameter TX_DATA = 3'h4;
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parameter TX_DATA = 3'h4;
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parameter TX_DATA_ACK = 3'h5;
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parameter TX_DATA_ACK = 3'h5;
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// State transition
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// State transition
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always @(i2c_state or i2c_init or shift_rx_done or i2c_addr_not_valid or shift_tx_done or scl_fe or shift_buf or sda_in)
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always @(i2c_state or i2c_init or shift_rx_done or i2c_addr_not_valid or shift_tx_done or scl_fe or shift_buf or sda_in)
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case (i2c_state)
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case (i2c_state)
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RX_ADDR : i2c_state_nxt = i2c_init ? RX_ADDR :
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RX_ADDR : i2c_state_nxt = i2c_init ? RX_ADDR :
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~shift_rx_done ? RX_ADDR :
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~shift_rx_done ? RX_ADDR :
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i2c_addr_not_valid ? RX_ADDR :
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i2c_addr_not_valid ? RX_ADDR :
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RX_ADDR_ACK;
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RX_ADDR_ACK;
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RX_ADDR_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
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RX_ADDR_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
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~scl_fe ? RX_ADDR_ACK :
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~scl_fe ? RX_ADDR_ACK :
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shift_buf[0] ? TX_DATA :
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shift_buf[0] ? TX_DATA :
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RX_DATA;
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RX_DATA;
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RX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
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RX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
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~shift_rx_done ? RX_DATA :
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~shift_rx_done ? RX_DATA :
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RX_DATA_ACK;
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RX_DATA_ACK;
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RX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
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RX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
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~scl_fe ? RX_DATA_ACK :
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~scl_fe ? RX_DATA_ACK :
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RX_DATA;
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RX_DATA;
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TX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
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TX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
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~shift_tx_done ? TX_DATA :
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~shift_tx_done ? TX_DATA :
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TX_DATA_ACK;
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TX_DATA_ACK;
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TX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
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TX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
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~scl_fe ? TX_DATA_ACK :
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~scl_fe ? TX_DATA_ACK :
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~sda_in ? TX_DATA :
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~sda_in ? TX_DATA :
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RX_ADDR;
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RX_ADDR;
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// pragma coverage off
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// pragma coverage off
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default : i2c_state_nxt = RX_ADDR;
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default : i2c_state_nxt = RX_ADDR;
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// pragma coverage on
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// pragma coverage on
|
endcase
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endcase
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|
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// State machine
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// State machine
|
always @(posedge dbg_clk or posedge dbg_rst)
|
always @(posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) i2c_state <= RX_ADDR;
|
if (dbg_rst) i2c_state <= RX_ADDR;
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else i2c_state <= i2c_state_nxt;
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else i2c_state <= i2c_state_nxt;
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|
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//=============================================================================
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//=============================================================================
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// 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
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// 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
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//=============================================================================
|
//=============================================================================
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|
|
wire shift_rx_en = ((i2c_state==RX_ADDR) | (i2c_state ==RX_DATA) | (i2c_state ==RX_DATA_ACK));
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wire shift_rx_en = ((i2c_state==RX_ADDR) | (i2c_state ==RX_DATA) | (i2c_state ==RX_DATA_ACK));
|
wire shift_tx_en = (i2c_state ==TX_DATA) | (i2c_state ==TX_DATA_ACK);
|
wire shift_tx_en = (i2c_state ==TX_DATA) | (i2c_state ==TX_DATA_ACK);
|
wire shift_tx_en_pre = (i2c_state_nxt==TX_DATA) | (i2c_state_nxt==TX_DATA_ACK);
|
wire shift_tx_en_pre = (i2c_state_nxt==TX_DATA) | (i2c_state_nxt==TX_DATA_ACK);
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|
|
assign shift_rx_done = shift_rx_en & scl_fe & shift_buf[8];
|
assign shift_rx_done = shift_rx_en & scl_fe & shift_buf[8];
|
assign shift_tx_done = shift_tx_en & scl_fe & (shift_buf==9'h100);
|
assign shift_tx_done = shift_tx_en & scl_fe & (shift_buf==9'h100);
|
|
|
wire shift_buf_rx_init = i2c_init | ((i2c_state==RX_ADDR_ACK) & scl_fe & ~shift_buf[0]) |
|
wire shift_buf_rx_init = i2c_init | ((i2c_state==RX_ADDR_ACK) & scl_fe & ~shift_buf[0]) |
|
((i2c_state==RX_DATA_ACK) & scl_fe);
|
((i2c_state==RX_DATA_ACK) & scl_fe);
|
wire shift_buf_rx_en = shift_rx_en & scl_sample;
|
wire shift_buf_rx_en = shift_rx_en & scl_sample;
|
|
|
wire shift_buf_tx_init = ((i2c_state==RX_ADDR_ACK) & scl_re & shift_buf[0]) |
|
wire shift_buf_tx_init = ((i2c_state==RX_ADDR_ACK) & scl_re & shift_buf[0]) |
|
((i2c_state==TX_DATA_ACK) & scl_re);
|
((i2c_state==TX_DATA_ACK) & scl_re);
|
wire shift_buf_tx_en = shift_tx_en_pre & scl_fe & (shift_buf!=9'h100);
|
wire shift_buf_tx_en = shift_tx_en_pre & scl_fe & (shift_buf!=9'h100);
|
|
|
wire [7:0] shift_tx_val;
|
wire [7:0] shift_tx_val;
|
|
|
wire [8:0] shift_buf_nxt = shift_buf_rx_init ? 9'h001 : // RX Init
|
wire [8:0] shift_buf_nxt = shift_buf_rx_init ? 9'h001 : // RX Init
|
shift_buf_tx_init ? {shift_tx_val, 1'b1} : // TX Init
|
shift_buf_tx_init ? {shift_tx_val, 1'b1} : // TX Init
|
shift_buf_rx_en ? {shift_buf[7:0], sda_in} : // RX Shift
|
shift_buf_rx_en ? {shift_buf[7:0], sda_in} : // RX Shift
|
shift_buf_tx_en ? {shift_buf[7:0], 1'b0} : // TX Shift
|
shift_buf_tx_en ? {shift_buf[7:0], 1'b0} : // TX Shift
|
shift_buf[8:0]; // Hold
|
shift_buf[8:0]; // Hold
|
|
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) shift_buf <= 9'h001;
|
if (dbg_rst) shift_buf <= 9'h001;
|
else shift_buf <= shift_buf_nxt;
|
else shift_buf <= shift_buf_nxt;
|
|
|
// Detect when the received I2C device address is not valid
|
// Detect when the received I2C device address is not valid
|
assign i2c_addr_not_valid = (i2c_state == RX_ADDR) && shift_rx_done && (
|
assign i2c_addr_not_valid = (i2c_state == RX_ADDR) && shift_rx_done && (
|
`ifdef DBG_I2C_BROADCAST
|
`ifdef DBG_I2C_BROADCAST
|
(shift_buf[7:1] != dbg_i2c_broadcast[6:0]) &&
|
(shift_buf[7:1] != dbg_i2c_broadcast[6:0]) &&
|
`endif
|
`endif
|
(shift_buf[7:1] != dbg_i2c_addr[6:0]));
|
(shift_buf[7:1] != dbg_i2c_addr[6:0]));
|
|
`ifdef DBG_I2C_BROADCAST
|
|
`else
|
|
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
|
|
`endif
|
|
|
// Utility signals
|
// Utility signals
|
wire shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA);
|
wire shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA);
|
wire shift_tx_data_done = shift_tx_done;
|
wire shift_tx_data_done = shift_tx_done;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) I2C TRANSMIT BUFFER
|
// 5) I2C TRANSMIT BUFFER
|
//=============================================================================
|
//=============================================================================
|
|
|
reg dbg_i2c_sda_out;
|
reg dbg_i2c_sda_out;
|
|
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) dbg_i2c_sda_out <= 1'b1;
|
if (dbg_rst) dbg_i2c_sda_out <= 1'b1;
|
else if (scl_fe) dbg_i2c_sda_out <= ~((i2c_state_nxt==RX_ADDR_ACK) ||
|
else if (scl_fe) dbg_i2c_sda_out <= ~((i2c_state_nxt==RX_ADDR_ACK) ||
|
(i2c_state_nxt==RX_DATA_ACK) ||
|
(i2c_state_nxt==RX_DATA_ACK) ||
|
(shift_buf_tx_en & ~shift_buf[8]));
|
(shift_buf_tx_en & ~shift_buf[8]));
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 6) DEBUG INTERFACE STATE MACHINE
|
// 6) DEBUG INTERFACE STATE MACHINE
|
//=============================================================================
|
//=============================================================================
|
|
|
// State register/wires
|
// State register/wires
|
reg [2:0] dbg_state;
|
reg [2:0] dbg_state;
|
reg [2:0] dbg_state_nxt;
|
reg [2:0] dbg_state_nxt;
|
|
|
// Utility signals
|
// Utility signals
|
reg dbg_bw;
|
reg dbg_bw;
|
|
|
// State machine definition
|
// State machine definition
|
parameter RX_CMD = 3'h0;
|
parameter RX_CMD = 3'h0;
|
parameter RX_BYTE_LO = 3'h1;
|
parameter RX_BYTE_LO = 3'h1;
|
parameter RX_BYTE_HI = 3'h2;
|
parameter RX_BYTE_HI = 3'h2;
|
parameter TX_BYTE_LO = 3'h3;
|
parameter TX_BYTE_LO = 3'h3;
|
parameter TX_BYTE_HI = 3'h4;
|
parameter TX_BYTE_HI = 3'h4;
|
|
|
// State transition
|
// State transition
|
always @(dbg_state or shift_rx_data_done or shift_tx_data_done or shift_buf or dbg_bw or
|
always @(dbg_state or shift_rx_data_done or shift_tx_data_done or shift_buf or dbg_bw or
|
mem_burst_wr or mem_burst_rd or mem_burst or mem_burst_end or mem_bw)
|
mem_burst_wr or mem_burst_rd or mem_burst or mem_burst_end or mem_bw)
|
case (dbg_state)
|
case (dbg_state)
|
RX_CMD : dbg_state_nxt = mem_burst_wr ? RX_BYTE_LO :
|
RX_CMD : dbg_state_nxt = mem_burst_wr ? RX_BYTE_LO :
|
mem_burst_rd ? TX_BYTE_LO :
|
mem_burst_rd ? TX_BYTE_LO :
|
~shift_rx_data_done ? RX_CMD :
|
~shift_rx_data_done ? RX_CMD :
|
shift_buf[7] ? RX_BYTE_LO :
|
shift_buf[7] ? RX_BYTE_LO :
|
TX_BYTE_LO;
|
TX_BYTE_LO;
|
|
|
RX_BYTE_LO : dbg_state_nxt = (mem_burst & mem_burst_end) ? RX_CMD :
|
RX_BYTE_LO : dbg_state_nxt = (mem_burst & mem_burst_end) ? RX_CMD :
|
~shift_rx_data_done ? RX_BYTE_LO :
|
~shift_rx_data_done ? RX_BYTE_LO :
|
(mem_burst & ~mem_burst_end) ?
|
(mem_burst & ~mem_burst_end) ?
|
(mem_bw ? RX_BYTE_LO :
|
(mem_bw ? RX_BYTE_LO :
|
RX_BYTE_HI) :
|
RX_BYTE_HI) :
|
dbg_bw ? RX_CMD :
|
dbg_bw ? RX_CMD :
|
RX_BYTE_HI;
|
RX_BYTE_HI;
|
|
|
RX_BYTE_HI : dbg_state_nxt = ~shift_rx_data_done ? RX_BYTE_HI :
|
RX_BYTE_HI : dbg_state_nxt = ~shift_rx_data_done ? RX_BYTE_HI :
|
(mem_burst & ~mem_burst_end) ? RX_BYTE_LO :
|
(mem_burst & ~mem_burst_end) ? RX_BYTE_LO :
|
RX_CMD;
|
RX_CMD;
|
|
|
TX_BYTE_LO : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_LO :
|
TX_BYTE_LO : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_LO :
|
( mem_burst & mem_bw) ? TX_BYTE_LO :
|
( mem_burst & mem_bw) ? TX_BYTE_LO :
|
( mem_burst & ~mem_bw) ? TX_BYTE_HI :
|
( mem_burst & ~mem_bw) ? TX_BYTE_HI :
|
~dbg_bw ? TX_BYTE_HI :
|
~dbg_bw ? TX_BYTE_HI :
|
RX_CMD;
|
RX_CMD;
|
|
|
TX_BYTE_HI : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_HI :
|
TX_BYTE_HI : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_HI :
|
mem_burst ? TX_BYTE_LO :
|
mem_burst ? TX_BYTE_LO :
|
RX_CMD;
|
RX_CMD;
|
|
|
// pragma coverage off
|
// pragma coverage off
|
default : dbg_state_nxt = RX_CMD;
|
default : dbg_state_nxt = RX_CMD;
|
// pragma coverage on
|
// pragma coverage on
|
endcase
|
endcase
|
|
|
// State machine
|
// State machine
|
always @(posedge dbg_clk or posedge dbg_rst)
|
always @(posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) dbg_state <= RX_CMD;
|
if (dbg_rst) dbg_state <= RX_CMD;
|
else dbg_state <= dbg_state_nxt;
|
else dbg_state <= dbg_state_nxt;
|
|
|
// Utility signals
|
// Utility signals
|
wire cmd_valid = (dbg_state==RX_CMD) & shift_rx_data_done;
|
wire cmd_valid = (dbg_state==RX_CMD) & shift_rx_data_done;
|
wire rx_lo_valid = (dbg_state==RX_BYTE_LO) & shift_rx_data_done;
|
wire rx_lo_valid = (dbg_state==RX_BYTE_LO) & shift_rx_data_done;
|
wire rx_hi_valid = (dbg_state==RX_BYTE_HI) & shift_rx_data_done;
|
wire rx_hi_valid = (dbg_state==RX_BYTE_HI) & shift_rx_data_done;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 7) REGISTER READ/WRITE ACCESS
|
// 7) REGISTER READ/WRITE ACCESS
|
//=============================================================================
|
//=============================================================================
|
|
|
parameter MEM_DATA = 6'h06;
|
parameter MEM_DATA = 6'h06;
|
|
|
// Debug register address & bit width
|
// Debug register address & bit width
|
reg [5:0] dbg_addr;
|
reg [5:0] dbg_addr;
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst)
|
if (dbg_rst)
|
begin
|
begin
|
dbg_bw <= 1'b0;
|
dbg_bw <= 1'b0;
|
dbg_addr <= 6'h00;
|
dbg_addr <= 6'h00;
|
end
|
end
|
else if (cmd_valid)
|
else if (cmd_valid)
|
begin
|
begin
|
dbg_bw <= shift_buf[6];
|
dbg_bw <= shift_buf[6];
|
dbg_addr <= shift_buf[5:0];
|
dbg_addr <= shift_buf[5:0];
|
end
|
end
|
else if (mem_burst)
|
else if (mem_burst)
|
begin
|
begin
|
dbg_bw <= mem_bw;
|
dbg_bw <= mem_bw;
|
dbg_addr <= MEM_DATA;
|
dbg_addr <= MEM_DATA;
|
end
|
end
|
|
|
|
|
// Debug register data input
|
// Debug register data input
|
reg [7:0] dbg_din_lo;
|
reg [7:0] dbg_din_lo;
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) dbg_din_lo <= 8'h00;
|
if (dbg_rst) dbg_din_lo <= 8'h00;
|
else if (rx_lo_valid) dbg_din_lo <= shift_buf[7:0];
|
else if (rx_lo_valid) dbg_din_lo <= shift_buf[7:0];
|
|
|
reg [7:0] dbg_din_hi;
|
reg [7:0] dbg_din_hi;
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) dbg_din_hi <= 8'h00;
|
if (dbg_rst) dbg_din_hi <= 8'h00;
|
else if (rx_lo_valid) dbg_din_hi <= 8'h00;
|
else if (rx_lo_valid) dbg_din_hi <= 8'h00;
|
else if (rx_hi_valid) dbg_din_hi <= shift_buf[7:0];
|
else if (rx_hi_valid) dbg_din_hi <= shift_buf[7:0];
|
|
|
assign dbg_din = {dbg_din_hi, dbg_din_lo};
|
assign dbg_din = {dbg_din_hi, dbg_din_lo};
|
|
|
|
|
// Debug register data write command
|
// Debug register data write command
|
reg dbg_wr;
|
reg dbg_wr;
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) dbg_wr <= 1'b0;
|
if (dbg_rst) dbg_wr <= 1'b0;
|
else dbg_wr <= (mem_burst & mem_bw) ? rx_lo_valid :
|
else dbg_wr <= (mem_burst & mem_bw) ? rx_lo_valid :
|
(mem_burst & ~mem_bw) ? rx_hi_valid :
|
(mem_burst & ~mem_bw) ? rx_hi_valid :
|
dbg_bw ? rx_lo_valid :
|
dbg_bw ? rx_lo_valid :
|
rx_hi_valid;
|
rx_hi_valid;
|
|
|
|
|
// Debug register data read command
|
// Debug register data read command
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (dbg_rst) dbg_rd <= 1'b0;
|
if (dbg_rst) dbg_rd <= 1'b0;
|
else dbg_rd <= (mem_burst & mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_LO)) :
|
else dbg_rd <= (mem_burst & mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_LO)) :
|
(mem_burst & ~mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_HI)) :
|
(mem_burst & ~mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_HI)) :
|
cmd_valid ? ~shift_buf[7] :
|
cmd_valid ? ~shift_buf[7] :
|
1'b0;
|
1'b0;
|
|
|
|
|
// Debug register data read value
|
// Debug register data read value
|
assign shift_tx_val = (dbg_state==TX_BYTE_HI) ? dbg_dout[15:8] :
|
assign shift_tx_val = (dbg_state==TX_BYTE_HI) ? dbg_dout[15:8] :
|
dbg_dout[7:0];
|
dbg_dout[7:0];
|
|
|
endmodule
|
endmodule
|
|
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_undefines.v"
|
`include "openMSP430_undefines.v"
|
`endif
|
`endif
|
|
|