//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's ALU ////
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//// OR1200's ALU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ALU ////
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//// ALU ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_alu.v,v $
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// $Log: or1200_alu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Defines added, flags are corrected.
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// Defines added, flags are corrected.
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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module or1200_alu(
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module or1200_alu(
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a, b, mult_mac_result, macrc_op,
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a, b, mult_mac_result, macrc_op,
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alu_op, alu_op2, comp_op,
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alu_op, alu_op2, comp_op,
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cust5_op, cust5_limm,
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cust5_op, cust5_limm,
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result, flagforw, flag_we,
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result, flagforw, flag_we,
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ovforw, ov_we,
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ovforw, ov_we,
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cyforw, cy_we, carry, flag
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cyforw, cy_we, carry, flag
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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|
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//
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//
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// I/O
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// I/O
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//
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//
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input [width-1:0] a;
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input [width-1:0] a;
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input [width-1:0] b;
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input [width-1:0] b;
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input [width-1:0] mult_mac_result;
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input [width-1:0] mult_mac_result;
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input macrc_op;
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input macrc_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
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input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
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input [4:0] cust5_op;
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input [4:0] cust5_op;
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input [5:0] cust5_limm;
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input [5:0] cust5_limm;
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output [width-1:0] result;
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output [width-1:0] result;
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output flagforw;
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output flagforw;
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output flag_we;
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output flag_we;
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output cyforw;
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output cyforw;
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output cy_we;
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output cy_we;
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output ovforw;
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output ovforw;
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output ov_we;
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output ov_we;
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input carry;
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input carry;
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input flag;
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input flag;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [width-1:0] result;
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reg [width-1:0] result;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] extended;
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reg [width-1:0] extended;
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reg [width-1:0] result_cust5;
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reg [width-1:0] result_cust5;
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reg flagforw;
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reg flagforw;
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reg flagcomp;
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reg flagcomp;
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reg flag_we;
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reg flag_we;
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reg cyforw;
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reg cyforw;
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reg cy_we;
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reg cy_we;
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reg ovforw;
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reg ovforw;
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reg ov_we;
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reg ov_we;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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wire [width-1:0] comp_b;
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wire a_eq_b;
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wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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wire [width-1:0] result_sum;
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wire [width-1:0] result_sum;
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wire [width-1:0] result_and;
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wire [width-1:0] result_and;
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wire cy_sum;
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wire cy_sum;
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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wire cy_sub;
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wire cy_sub;
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`endif
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`endif
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wire ov_sum;
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wire ov_sum;
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wire [width-1:0] carry_in;
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wire [width-1:0] carry_in;
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wire [width-1:0] b_mux;
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wire [width-1:0] b_mux;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_COMP3
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`ifdef OR1200_IMPL_ALU_COMP3
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assign a_eq_b = !(|result_sum);
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assign a_eq_b = !(|result_sum);
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// signed compare when comp_op[3] is set
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// signed compare when comp_op[3] is set
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assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
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assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
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(!a[width-1] & !b[width-1] & result_sum[width-1])|
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(!a[width-1] & !b[width-1] & result_sum[width-1])|
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(a[width-1] & b[width-1] & result_sum[width-1])):
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(a[width-1] & b[width-1] & result_sum[width-1])):
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// a < b if (a - b) subtraction wrapped and a[width-1] wasn't set
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(a < b);
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(result_sum[width-1] & !a[width-1]) |
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// or if (a - b) wrapped and both a[width-1] and b[width-1] were set
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(result_sum[width-1] & a[width-1] & b[width-1] );
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`endif
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`endif
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|
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_ALU_COMP3
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`ifdef OR1200_IMPL_ALU_COMP3
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assign cy_sub = a_lt_b;
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assign cy_sub = a_lt_b;
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`else
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`else
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assign cy_sub = (comp_a < comp_b);
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assign cy_sub = (comp_a < comp_b);
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`endif
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`endif
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`endif
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`endif
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|
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
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assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
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{{width-1{1'b0}},carry} : {width{1'b0}};
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{{width-1{1'b0}},carry} : {width{1'b0}};
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`else
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`else
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assign carry_in = {width-1{1'b0}};
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assign carry_in = {width-1{1'b0}};
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`endif
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`endif
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|
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`ifdef OR1200_IMPL_ALU_COMP3
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`ifdef OR1200_IMPL_ALU_COMP3
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
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assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
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(~b)+1 : b;
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(~b)+1 : b;
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`else
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`else
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assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
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assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
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`endif
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`endif
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`else // ! `ifdef OR1200_IMPL_ALU_COMP3
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`else // ! `ifdef OR1200_IMPL_ALU_COMP3
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`ifdef OR1200_IMPL_SUB
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`ifdef OR1200_IMPL_SUB
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assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
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assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
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`else
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`else
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assign b_mux = b;
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assign b_mux = b;
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`endif
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`endif
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`endif
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`endif
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assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
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assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
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// Numbers either both +ve and bit 31 of result set
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// Numbers either both +ve and bit 31 of result set
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assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
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assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
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// or both -ve and bit 31 of result clear
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// or both -ve and bit 31 of result clear
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((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
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((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
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assign result_and = a & b;
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assign result_and = a & b;
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|
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//
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//
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// Simulation check for bad ALU behavior
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// Simulation check for bad ALU behavior
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//
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//
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`ifdef OR1200_WARNINGS
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`ifdef OR1200_WARNINGS
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// synopsys translate_off
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// synopsys translate_off
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always @(result) begin
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always @(result) begin
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if (result === 32'bx)
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if (result === 32'bx)
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$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
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$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
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end
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end
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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//
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//
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// Central part of the ALU
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// Central part of the ALU
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//
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//
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always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
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always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
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or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
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`ifdef OR1200_IMPL_ALU_EXT
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`ifdef OR1200_IMPL_ALU_EXT
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or extended
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or extended
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`endif
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`endif
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) begin
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) begin
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`ifdef OR1200_CASE_DEFAULT
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`ifdef OR1200_CASE_DEFAULT
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casez (alu_op) // synopsys parallel_case
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casez (alu_op) // synopsys parallel_case
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`else
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`else
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casez (alu_op) // synopsys full_case parallel_case
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casez (alu_op) // synopsys full_case parallel_case
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`endif
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`endif
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`ifdef OR1200_IMPL_ALU_FFL1
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`ifdef OR1200_IMPL_ALU_FFL1
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`OR1200_ALUOP_FFL1: begin
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`OR1200_ALUOP_FFL1: begin
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`ifdef OR1200_CASE_DEFAULT
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`ifdef OR1200_CASE_DEFAULT
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casez (alu_op2) // synopsys parallel_case
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casez (alu_op2) // synopsys parallel_case
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`else
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`else
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casez (alu_op2) // synopsys full_case parallel_case
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casez (alu_op2) // synopsys full_case parallel_case
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`endif
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`endif
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0: begin // FF1
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0: begin // FF1
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result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
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result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
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end
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end
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default: begin // FL1
|
default: begin // FL1
|
result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
|
result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
|
end
|
end
|
endcase // casez (alu_op2)
|
endcase // casez (alu_op2)
|
end // case: `OR1200_ALUOP_FFL1
|
end // case: `OR1200_ALUOP_FFL1
|
`endif // `ifdef OR1200_IMPL_ALU_FFL1
|
`endif // `ifdef OR1200_IMPL_ALU_FFL1
|
`ifdef OR1200_IMPL_ALU_CUST5
|
`ifdef OR1200_IMPL_ALU_CUST5
|
|
|
`OR1200_ALUOP_CUST5 : begin
|
`OR1200_ALUOP_CUST5 : begin
|
result = result_cust5;
|
result = result_cust5;
|
end
|
end
|
`endif
|
`endif
|
`OR1200_ALUOP_SHROT : begin
|
`OR1200_ALUOP_SHROT : begin
|
result = shifted_rotated;
|
result = shifted_rotated;
|
end
|
end
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`OR1200_ALUOP_ADDC,
|
`OR1200_ALUOP_ADDC,
|
`endif
|
`endif
|
`ifdef OR1200_IMPL_SUB
|
`ifdef OR1200_IMPL_SUB
|
`OR1200_ALUOP_SUB,
|
`OR1200_ALUOP_SUB,
|
`endif
|
`endif
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
result = result_sum;
|
result = result_sum;
|
end
|
end
|
`OR1200_ALUOP_XOR : begin
|
`OR1200_ALUOP_XOR : begin
|
result = a ^ b;
|
result = a ^ b;
|
end
|
end
|
`OR1200_ALUOP_OR : begin
|
`OR1200_ALUOP_OR : begin
|
result = a | b;
|
result = a | b;
|
end
|
end
|
`ifdef OR1200_IMPL_ALU_EXT
|
`ifdef OR1200_IMPL_ALU_EXT
|
`OR1200_ALUOP_EXTHB : begin
|
`OR1200_ALUOP_EXTHB : begin
|
result = extended;
|
result = extended;
|
end
|
end
|
`OR1200_ALUOP_EXTW : begin
|
`OR1200_ALUOP_EXTW : begin
|
result = extended;
|
result = extended;
|
end
|
end
|
`endif
|
`endif
|
`OR1200_ALUOP_MOVHI : begin
|
`OR1200_ALUOP_MOVHI : begin
|
if (macrc_op) begin
|
if (macrc_op) begin
|
result = mult_mac_result;
|
result = mult_mac_result;
|
end
|
end
|
else begin
|
else begin
|
result = b << 16;
|
result = b << 16;
|
end
|
end
|
end
|
end
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_MULT_IMPLEMENTED
|
`ifdef OR1200_DIV_IMPLEMENTED
|
`ifdef OR1200_DIV_IMPLEMENTED
|
`OR1200_ALUOP_DIV,
|
`OR1200_ALUOP_DIV,
|
`OR1200_ALUOP_DIVU,
|
`OR1200_ALUOP_DIVU,
|
`endif
|
`endif
|
`OR1200_ALUOP_MUL,
|
`OR1200_ALUOP_MUL,
|
`OR1200_ALUOP_MULU : begin
|
`OR1200_ALUOP_MULU : begin
|
result = mult_mac_result;
|
result = mult_mac_result;
|
end
|
end
|
`endif
|
`endif
|
`OR1200_ALUOP_CMOV: begin
|
`OR1200_ALUOP_CMOV: begin
|
result = flag ? a : b;
|
result = flag ? a : b;
|
end
|
end
|
|
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
default: begin
|
default: begin
|
`else
|
`else
|
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
|
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
|
`endif
|
`endif
|
result=result_and;
|
result=result_and;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Generate flag and flag write enable
|
// Generate flag and flag write enable
|
//
|
//
|
always @(alu_op or result_sum or result_and or flagcomp
|
always @(alu_op or result_sum or result_and or flagcomp
|
) begin
|
) begin
|
casez (alu_op) // synopsys parallel_case
|
casez (alu_op) // synopsys parallel_case
|
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
|
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`OR1200_ALUOP_ADDC,
|
`OR1200_ALUOP_ADDC,
|
`endif
|
`endif
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
flagforw = (result_sum == 32'h0000_0000);
|
flagforw = (result_sum == 32'h0000_0000);
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
`OR1200_ALUOP_AND: begin
|
`OR1200_ALUOP_AND: begin
|
flagforw = (result_and == 32'h0000_0000);
|
flagforw = (result_and == 32'h0000_0000);
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
`endif
|
`endif
|
`OR1200_ALUOP_COMP: begin
|
`OR1200_ALUOP_COMP: begin
|
flagforw = flagcomp;
|
flagforw = flagcomp;
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
default: begin
|
default: begin
|
flagforw = flagcomp;
|
flagforw = flagcomp;
|
flag_we = 1'b0;
|
flag_we = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Generate SR[CY] write enable
|
// Generate SR[CY] write enable
|
//
|
//
|
always @(alu_op or cy_sum
|
always @(alu_op or cy_sum
|
`ifdef OR1200_IMPL_CY
|
`ifdef OR1200_IMPL_CY
|
`ifdef OR1200_IMPL_SUB
|
`ifdef OR1200_IMPL_SUB
|
or cy_sub
|
or cy_sub
|
`endif
|
`endif
|
`endif
|
`endif
|
) begin
|
) begin
|
casez (alu_op) // synopsys parallel_case
|
casez (alu_op) // synopsys parallel_case
|
`ifdef OR1200_IMPL_CY
|
`ifdef OR1200_IMPL_CY
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`OR1200_ALUOP_ADDC,
|
`OR1200_ALUOP_ADDC,
|
`endif
|
`endif
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
cyforw = cy_sum;
|
cyforw = cy_sum;
|
cy_we = 1'b1;
|
cy_we = 1'b1;
|
end
|
end
|
`ifdef OR1200_IMPL_SUB
|
`ifdef OR1200_IMPL_SUB
|
`OR1200_ALUOP_SUB: begin
|
`OR1200_ALUOP_SUB: begin
|
cyforw = cy_sub;
|
cyforw = cy_sub;
|
cy_we = 1'b1;
|
cy_we = 1'b1;
|
end
|
end
|
`endif
|
`endif
|
`endif
|
`endif
|
default: begin
|
default: begin
|
cyforw = 1'b0;
|
cyforw = 1'b0;
|
cy_we = 1'b0;
|
cy_we = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
//
|
//
|
// Generate SR[OV] write enable
|
// Generate SR[OV] write enable
|
//
|
//
|
always @(alu_op or ov_sum) begin
|
always @(alu_op or ov_sum) begin
|
casez (alu_op) // synopsys parallel_case
|
casez (alu_op) // synopsys parallel_case
|
`ifdef OR1200_IMPL_OV
|
`ifdef OR1200_IMPL_OV
|
`ifdef OR1200_IMPL_ADDC
|
`ifdef OR1200_IMPL_ADDC
|
`OR1200_ALUOP_ADDC,
|
`OR1200_ALUOP_ADDC,
|
`endif
|
`endif
|
`ifdef OR1200_IMPL_SUB
|
`ifdef OR1200_IMPL_SUB
|
`OR1200_ALUOP_SUB,
|
`OR1200_ALUOP_SUB,
|
`endif
|
`endif
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
ovforw = ov_sum;
|
ovforw = ov_sum;
|
ov_we = 1'b1;
|
ov_we = 1'b1;
|
end
|
end
|
`endif
|
`endif
|
default: begin
|
default: begin
|
ovforw = 1'b0;
|
ovforw = 1'b0;
|
ov_we = 1'b0;
|
ov_we = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Shifts and rotation
|
// Shifts and rotation
|
//
|
//
|
always @(alu_op2 or a or b) begin
|
always @(alu_op2 or a or b) begin
|
case (alu_op2) // synopsys parallel_case
|
case (alu_op2) // synopsys parallel_case
|
`OR1200_SHROTOP_SLL :
|
`OR1200_SHROTOP_SLL :
|
shifted_rotated = (a << b[4:0]);
|
shifted_rotated = (a << b[4:0]);
|
`OR1200_SHROTOP_SRL :
|
`OR1200_SHROTOP_SRL :
|
shifted_rotated = (a >> b[4:0]);
|
shifted_rotated = (a >> b[4:0]);
|
|
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`ifdef OR1200_IMPL_ALU_ROTATE
|
`OR1200_SHROTOP_ROR :
|
`OR1200_SHROTOP_ROR :
|
shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
|
shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
|
(a >> b[4:0]);
|
(a >> b[4:0]);
|
`endif
|
`endif
|
default:
|
default:
|
shifted_rotated = ({32{a[31]}} <<
|
shifted_rotated = ({32{a[31]}} <<
|
(6'd32-{1'b0, b[4:0]})) |
|
(6'd32-{1'b0, b[4:0]})) |
|
a >> b[4:0];
|
a >> b[4:0];
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// First type of compare implementation
|
// First type of compare implementation
|
//
|
//
|
`ifdef OR1200_IMPL_ALU_COMP1
|
`ifdef OR1200_IMPL_ALU_COMP1
|
always @(comp_op or a_eq_b or a_lt_b) begin
|
always @(comp_op or a_eq_b or a_lt_b) begin
|
case(comp_op[2:0]) // synopsys parallel_case
|
case(comp_op[2:0]) // synopsys parallel_case
|
`OR1200_COP_SFEQ:
|
`OR1200_COP_SFEQ:
|
flagcomp = a_eq_b;
|
flagcomp = a_eq_b;
|
`OR1200_COP_SFNE:
|
`OR1200_COP_SFNE:
|
flagcomp = ~a_eq_b;
|
flagcomp = ~a_eq_b;
|
`OR1200_COP_SFGT:
|
`OR1200_COP_SFGT:
|
flagcomp = ~(a_eq_b | a_lt_b);
|
flagcomp = ~(a_eq_b | a_lt_b);
|
`OR1200_COP_SFGE:
|
`OR1200_COP_SFGE:
|
flagcomp = ~a_lt_b;
|
flagcomp = ~a_lt_b;
|
`OR1200_COP_SFLT:
|
`OR1200_COP_SFLT:
|
flagcomp = a_lt_b;
|
flagcomp = a_lt_b;
|
`OR1200_COP_SFLE:
|
`OR1200_COP_SFLE:
|
flagcomp = a_eq_b | a_lt_b;
|
flagcomp = a_eq_b | a_lt_b;
|
default:
|
default:
|
flagcomp = 1'b0;
|
flagcomp = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
|
|
//
|
//
|
// Second type of compare implementation
|
// Second type of compare implementation
|
//
|
//
|
`ifdef OR1200_IMPL_ALU_COMP2
|
`ifdef OR1200_IMPL_ALU_COMP2
|
always @(comp_op or comp_a or comp_b) begin
|
always @(comp_op or comp_a or comp_b) begin
|
case(comp_op[2:0]) // synopsys parallel_case
|
case(comp_op[2:0]) // synopsys parallel_case
|
`OR1200_COP_SFEQ:
|
`OR1200_COP_SFEQ:
|
flagcomp = (comp_a == comp_b);
|
flagcomp = (comp_a == comp_b);
|
`OR1200_COP_SFNE:
|
`OR1200_COP_SFNE:
|
flagcomp = (comp_a != comp_b);
|
flagcomp = (comp_a != comp_b);
|
`OR1200_COP_SFGT:
|
`OR1200_COP_SFGT:
|
flagcomp = (comp_a > comp_b);
|
flagcomp = (comp_a > comp_b);
|
`OR1200_COP_SFGE:
|
`OR1200_COP_SFGE:
|
flagcomp = (comp_a >= comp_b);
|
flagcomp = (comp_a >= comp_b);
|
`OR1200_COP_SFLT:
|
`OR1200_COP_SFLT:
|
flagcomp = (comp_a < comp_b);
|
flagcomp = (comp_a < comp_b);
|
`OR1200_COP_SFLE:
|
`OR1200_COP_SFLE:
|
flagcomp = (comp_a <= comp_b);
|
flagcomp = (comp_a <= comp_b);
|
default:
|
default:
|
flagcomp = 1'b0;
|
flagcomp = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
`endif // `ifdef OR1200_IMPL_ALU_COMP2
|
`endif // `ifdef OR1200_IMPL_ALU_COMP2
|
|
|
`ifdef OR1200_IMPL_ALU_COMP3
|
`ifdef OR1200_IMPL_ALU_COMP3
|
always @(comp_op or a_eq_b or a_lt_b) begin
|
always @(comp_op or a_eq_b or a_lt_b) begin
|
case(comp_op[2:0]) // synopsys parallel_case
|
case(comp_op[2:0]) // synopsys parallel_case
|
`OR1200_COP_SFEQ:
|
`OR1200_COP_SFEQ:
|
flagcomp = a_eq_b;
|
flagcomp = a_eq_b;
|
`OR1200_COP_SFNE:
|
`OR1200_COP_SFNE:
|
flagcomp = ~a_eq_b;
|
flagcomp = ~a_eq_b;
|
`OR1200_COP_SFGT:
|
`OR1200_COP_SFGT:
|
flagcomp = ~(a_eq_b | a_lt_b);
|
flagcomp = ~(a_eq_b | a_lt_b);
|
`OR1200_COP_SFGE:
|
`OR1200_COP_SFGE:
|
flagcomp = ~a_lt_b;
|
flagcomp = ~a_lt_b;
|
`OR1200_COP_SFLT:
|
`OR1200_COP_SFLT:
|
flagcomp = a_lt_b;
|
flagcomp = a_lt_b;
|
`OR1200_COP_SFLE:
|
`OR1200_COP_SFLE:
|
flagcomp = a_eq_b | a_lt_b;
|
flagcomp = a_eq_b | a_lt_b;
|
default:
|
default:
|
flagcomp = 1'b0;
|
flagcomp = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
`ifdef OR1200_IMPL_ALU_EXT
|
`ifdef OR1200_IMPL_ALU_EXT
|
always @(alu_op or alu_op2 or a) begin
|
always @(alu_op or alu_op2 or a) begin
|
casez (alu_op2)
|
casez (alu_op2)
|
`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
|
`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
|
`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
|
`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
|
`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
|
`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
|
`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
|
`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
|
default: extended = a; // Used for l.extw instructions
|
default: extended = a; // Used for l.extw instructions
|
endcase // casez (alu_op2)
|
endcase // casez (alu_op2)
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// l.cust5 custom instructions
|
// l.cust5 custom instructions
|
//
|
//
|
`ifdef OR1200_IMPL_ALU_CUST5
|
`ifdef OR1200_IMPL_ALU_CUST5
|
// Examples for move byte, set bit and clear bit
|
// Examples for move byte, set bit and clear bit
|
//
|
//
|
always @(cust5_op or cust5_limm or a or b) begin
|
always @(cust5_op or cust5_limm or a or b) begin
|
casez (cust5_op) // synopsys parallel_case
|
casez (cust5_op) // synopsys parallel_case
|
5'h1 : begin
|
5'h1 : begin
|
casez (cust5_limm[1:0])
|
casez (cust5_limm[1:0])
|
2'h0: result_cust5 = {a[31:8], b[7:0]};
|
2'h0: result_cust5 = {a[31:8], b[7:0]};
|
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
|
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
|
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
|
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
|
2'h3: result_cust5 = {b[7:0], a[23:0]};
|
2'h3: result_cust5 = {b[7:0], a[23:0]};
|
endcase
|
endcase
|
end
|
end
|
5'h2 :
|
5'h2 :
|
result_cust5 = a | (1 << cust5_limm);
|
result_cust5 = a | (1 << cust5_limm);
|
5'h3 :
|
5'h3 :
|
result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
|
result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
|
//
|
//
|
// *** Put here new l.cust5 custom instructions ***
|
// *** Put here new l.cust5 custom instructions ***
|
//
|
//
|
default: begin
|
default: begin
|
result_cust5 = a;
|
result_cust5 = a;
|
end
|
end
|
endcase
|
endcase
|
end // always @ (cust5_op or cust5_limm or a or b)
|
end // always @ (cust5_op or cust5_limm or a or b)
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
