/* dcache-model.c -- data cache simulation
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/* dcache-model.c -- data cache simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Cache functions. At the moment these functions only simulate functionality
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/* Cache functions. At the moment these functions only simulate functionality
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of data caches and do not influence on fetche/decode/execute stages and
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of data caches and do not influence on fetche/decode/execute stages and
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timings. They are here only to verify performance of various cache
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timings. They are here only to verify performance of various cache
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configurations. */
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configurations. */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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/* Package includes */
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/* Package includes */
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#include "dcache-model.h"
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#include "dcache-model.h"
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#include "execute.h"
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#include "execute.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "misc.h"
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#include "misc.h"
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/* Data cache */
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/* Data cache */
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struct dc_set
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struct dc_set
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{
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{
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struct
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struct
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{
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{
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uint32_t line[MAX_DC_BLOCK_SIZE/4];
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uint32_t line[MAX_DC_BLOCK_SIZE/4];
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oraddr_t tagaddr; /* tag address */
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oraddr_t tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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} way[MAX_DC_WAYS];
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} way[MAX_DC_WAYS];
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} dc[MAX_DC_SETS];
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} dc[MAX_DC_SETS];
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void
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void
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dc_info (void)
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dc_info (void)
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{
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{
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
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{
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{
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PRINTF ("DCache not implemented. Set UPR[DCP].\n");
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PRINTF ("DCache not implemented. Set UPR[DCP].\n");
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return;
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return;
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}
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}
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PRINTF ("Data cache %dKB: ",
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PRINTF ("Data cache %dKB: ",
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config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
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config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
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PRINTF ("%d ways, %d sets, block size %d bytes\n", config.dc.nways,
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PRINTF ("%d ways, %d sets, block size %d bytes\n", config.dc.nways,
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config.dc.nsets, config.dc.blocksize);
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config.dc.nsets, config.dc.blocksize);
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC read hit stats,
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- increment DC read hit stats,
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- set 'lru' at this way to config.dc.ustates - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment DC read miss stats
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- increment DC read miss stats
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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- refill cache line
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- refill cache line
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*/
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*/
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uint32_t
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uint32_t
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dc_simulate_read (oraddr_t dataaddr, oraddr_t virt_addr, int width)
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dc_simulate_read (oraddr_t dataaddr, oraddr_t virt_addr, int width)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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uint32_t tmp = 0;
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uint32_t tmp = 0;
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
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!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci)
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!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci)
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{
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{
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if (width == 4)
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if (width == 4)
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tmp = evalsim_mem32 (dataaddr, virt_addr);
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tmp = evalsim_mem32 (dataaddr, virt_addr);
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else if (width == 2)
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else if (width == 2)
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tmp = evalsim_mem16 (dataaddr, virt_addr);
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tmp = evalsim_mem16 (dataaddr, virt_addr);
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else if (width == 1)
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else if (width == 1)
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tmp = evalsim_mem8 (dataaddr, virt_addr);
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tmp = evalsim_mem8 (dataaddr, virt_addr);
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if (cur_area && cur_area->log)
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if (cur_area && cur_area->log)
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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dataaddr, tmp);
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dataaddr, tmp);
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return tmp;
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return tmp;
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].tagaddr == tagaddr)
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if (dc[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if (way >= 0)
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if (way >= 0)
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{ /* Yes, we did. */
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{ /* Yes, we did. */
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dc_stats.readhit++;
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dc_stats.readhit++;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru > dc[set].way[way].lru)
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if (dc[set].way[i].lru > dc[set].way[way].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[way].lru = config.dc.ustates - 1;
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dc[set].way[way].lru = config.dc.ustates - 1;
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runtime.sim.mem_cycles += config.dc.load_hitdelay;
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runtime.sim.mem_cycles += config.dc.load_hitdelay;
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tmp =
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tmp =
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dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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return tmp;
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return tmp;
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else if (width == 2)
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else if (width == 2)
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{
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{
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tmp = ((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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tmp = ((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
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return tmp;
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return tmp;
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}
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}
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else if (width == 1)
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else if (width == 1)
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{
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{
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tmp = ((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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tmp = ((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
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return tmp;
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return tmp;
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}
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}
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}
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}
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else
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else
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{ /* No, we didn't. */
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{ /* No, we didn't. */
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int minlru = config.dc.ustates - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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dc_stats.readmiss++;
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dc_stats.readmiss++;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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{
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{
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if (dc[set].way[i].lru < minlru)
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if (dc[set].way[i].lru < minlru)
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{
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{
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minway = i;
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minway = i;
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minlru = dc[set].way[i].lru;
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minlru = dc[set].way[i].lru;
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}
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}
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}
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}
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for (i = 0; i < (config.dc.blocksize); i += 4)
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for (i = 0; i < (config.dc.blocksize); i += 4)
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{
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{
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/* FIXME: What is the virtual address meant to be? (ie. What happens if
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/* FIXME: What is the virtual address meant to be? (ie. What happens if
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* we read out of memory while refilling a cache line?) */
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* we read out of memory while refilling a cache line?) */
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tmp =
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tmp =
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evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
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evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
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(((dataaddr & ~ADDR_C (3)) +
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(((dataaddr & ~ADDR_C (3)) +
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i) & (config.dc.blocksize - 1)), 0);
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i) & (config.dc.blocksize - 1)), 0);
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dc[set].way[minway].
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dc[set].way[minway].
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line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = tmp;
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line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = tmp;
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if (!cur_area)
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if (!cur_area)
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{
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{
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].lru = 0;
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dc[set].way[minway].lru = 0;
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return 0;
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return 0;
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}
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}
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else if (cur_area->log)
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else if (cur_area->log)
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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dataaddr, tmp);
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dataaddr, tmp);
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}
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}
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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runtime.sim.mem_cycles += config.dc.load_missdelay;
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runtime.sim.mem_cycles += config.dc.load_missdelay;
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tmp =
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tmp =
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dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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return tmp;
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return tmp;
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else if (width == 2)
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else if (width == 2)
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{
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{
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tmp = (tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff;
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tmp = (tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff;
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return tmp;
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return tmp;
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}
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}
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else if (width == 1)
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else if (width == 1)
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{
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{
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tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff;
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tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff;
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return tmp;
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return tmp;
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}
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}
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}
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}
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return 0;
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return 0;
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC write hit stats,
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- increment DC write hit stats,
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- set 'lru' at this way to config.dc.ustates - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment DC write miss stats
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- increment DC write miss stats
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void
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void
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dc_simulate_write (oraddr_t dataaddr, oraddr_t virt_addr, uint32_t data,
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dc_simulate_write (oraddr_t dataaddr, oraddr_t virt_addr, uint32_t data,
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int width)
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int width)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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uint32_t tmp;
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uint32_t tmp;
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if (width == 4)
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if (width == 4)
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setsim_mem32 (dataaddr, virt_addr, data);
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setsim_mem32 (dataaddr, virt_addr, data);
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else if (width == 2)
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else if (width == 2)
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setsim_mem16 (dataaddr, virt_addr, data);
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setsim_mem16 (dataaddr, virt_addr, data);
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else if (width == 1)
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else if (width == 1)
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setsim_mem8 (dataaddr, virt_addr, data);
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setsim_mem8 (dataaddr, virt_addr, data);
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|
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
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!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci || !cur_area)
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!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci || !cur_area)
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return;
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return;
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|
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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|
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].tagaddr == tagaddr)
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if (dc[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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|
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if (way >= 0)
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if (way >= 0)
|
{ /* Yes, we did. */
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{ /* Yes, we did. */
|
dc_stats.writehit++;
|
dc_stats.writehit++;
|
|
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru > dc[set].way[way].lru)
|
if (dc[set].way[i].lru > dc[set].way[way].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
dc[set].way[way].lru = config.dc.ustates - 1;
|
runtime.sim.mem_cycles += config.dc.store_hitdelay;
|
runtime.sim.mem_cycles += config.dc.store_hitdelay;
|
|
|
tmp =
|
tmp =
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dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
|
if (width == 4)
|
if (width == 4)
|
tmp = data;
|
tmp = data;
|
else if (width == 2)
|
else if (width == 2)
|
{
|
{
|
tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
|
tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
|
tmp |= (data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
|
tmp |= (data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
|
}
|
}
|
else if (width == 1)
|
else if (width == 1)
|
{
|
{
|
tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
|
tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
|
tmp |= (data & 0xff) << (8 * (3 - (dataaddr & 3)));
|
tmp |= (data & 0xff) << (8 * (3 - (dataaddr & 3)));
|
}
|
}
|
dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] =
|
dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] =
|
tmp;
|
tmp;
|
}
|
}
|
else
|
else
|
{ /* No, we didn't. */
|
{ /* No, we didn't. */
|
int minlru = config.dc.ustates - 1;
|
int minlru = config.dc.ustates - 1;
|
int minway = 0;
|
int minway = 0;
|
|
|
dc_stats.writemiss++;
|
dc_stats.writemiss++;
|
|
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru < minlru)
|
if (dc[set].way[i].lru < minlru)
|
minway = i;
|
minway = i;
|
|
|
for (i = 0; i < (config.dc.blocksize); i += 4)
|
for (i = 0; i < (config.dc.blocksize); i += 4)
|
{
|
{
|
dc[set].way[minway].
|
dc[set].way[minway].
|
line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
|
line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
|
/* FIXME: Same comment as in dc_simulate_read */
|
/* FIXME: Same comment as in dc_simulate_read */
|
evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
|
evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
|
(((dataaddr & ~3ul) + i) & (config.dc.blocksize -
|
(((dataaddr & ~3ul) + i) & (config.dc.blocksize -
|
1)), 0);
|
1)), 0);
|
if (!cur_area)
|
if (!cur_area)
|
{
|
{
|
dc[set].way[minway].tagaddr = -1;
|
dc[set].way[minway].tagaddr = -1;
|
dc[set].way[minway].lru = 0;
|
dc[set].way[minway].lru = 0;
|
return;
|
return;
|
}
|
}
|
}
|
}
|
|
|
dc[set].way[minway].tagaddr = tagaddr;
|
dc[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].lru)
|
if (dc[set].way[i].lru)
|
dc[set].way[i].lru--;
|
dc[set].way[i].lru--;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
dc[set].way[minway].lru = config.dc.ustates - 1;
|
runtime.sim.mem_cycles += config.dc.store_missdelay;
|
runtime.sim.mem_cycles += config.dc.store_missdelay;
|
}
|
}
|
}
|
}
|
|
|
/* First check if data is already in the cache and if it is:
|
/* First check if data is already in the cache and if it is:
|
- invalidate block if way isn't locked
|
- invalidate block if way isn't locked
|
otherwise don't do anything.
|
otherwise don't do anything.
|
*/
|
*/
|
|
|
void
|
void
|
dc_inv (oraddr_t dataaddr)
|
dc_inv (oraddr_t dataaddr)
|
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
oraddr_t tagaddr;
|
oraddr_t tagaddr;
|
|
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
|
return;
|
return;
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
|
|
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE))
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE))
|
{
|
{
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
{
|
{
|
dc[set].way[i].tagaddr = -1;
|
dc[set].way[i].tagaddr = -1;
|
dc[set].way[i].lru = 0;
|
dc[set].way[i].lru = 0;
|
}
|
}
|
return;
|
return;
|
}
|
}
|
/* Scan all ways and try to find a matching way. */
|
/* Scan all ways and try to find a matching way. */
|
for (i = 0; i < config.dc.nways; i++)
|
for (i = 0; i < config.dc.nways; i++)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
if (dc[set].way[i].tagaddr == tagaddr)
|
way = i;
|
way = i;
|
|
|
/* Did we find our cached data? */
|
/* Did we find our cached data? */
|
if (way >= 0)
|
if (way >= 0)
|
{ /* Yes, we did. */
|
{ /* Yes, we did. */
|
dc[set].way[way].tagaddr = -1;
|
dc[set].way[way].tagaddr = -1;
|
dc[set].way[way].lru = 0;
|
dc[set].way[way].lru = 0;
|
}
|
}
|
}
|
}
|
|
|
/*-----------------------------------------------------[ DC configuration ]---*/
|
/*-----------------------------------------------------[ DC configuration ]---*/
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Enable or disable the data cache
|
/*!Enable or disable the data cache
|
|
|
Set the corresponding field in the UPR
|
Set the corresponding field in the UPR
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure (not used here) */
|
@param[in] dat The config data structure (not used here) */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dc_enabled (union param_val val,
|
dc_enabled (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
if (val.int_val)
|
if (val.int_val)
|
{
|
{
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DCP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DCP;
|
}
|
}
|
else
|
else
|
{
|
{
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DCP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DCP;
|
}
|
}
|
|
|
config.dc.enabled = val.int_val;
|
config.dc.enabled = val.int_val;
|
|
|
} /* dc_enabled() */
|
} /* dc_enabled() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of data cache sets
|
/*!Set the number of data cache sets
|
|
|
Value must be a power of 2 <= MAX_DC_SETS. If not issue a warning and
|
Value must be a power of 2 <= MAX_DC_SETS. If not issue a warning and
|
ignore. Set the relevant field in the data cache config register
|
ignore. Set the relevant field in the data cache config register
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure (not used here) */
|
@param[in] dat The config data structure (not used here) */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dc_nsets (union param_val val,
|
dc_nsets (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_SETS))
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_SETS))
|
{
|
{
|
int set_bits = log2_int (val.int_val);
|
int set_bits = log2_int (val.int_val);
|
|
|
config.dc.nsets = val.int_val;
|
config.dc.nsets = val.int_val;
|
|
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCS;
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCS;
|
cpu_state.sprs[SPR_DCCFGR] |= set_bits << SPR_DCCFGR_NCS_OFF;
|
cpu_state.sprs[SPR_DCCFGR] |= set_bits << SPR_DCCFGR_NCS_OFF;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning: data cache nsets not a power of 2 <= %d: "
|
fprintf (stderr, "Warning: data cache nsets not a power of 2 <= %d: "
|
"ignored\n", MAX_DC_SETS);
|
"ignored\n", MAX_DC_SETS);
|
}
|
}
|
} /* dc_nsets() */
|
} /* dc_nsets() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of data cache ways
|
/*!Set the number of data cache ways
|
|
|
Value must be a power of 2 <= MAX_DC_WAYS. If not issue a warning and
|
Value must be a power of 2 <= MAX_DC_WAYS. If not issue a warning and
|
ignore. Set the relevant field in the data cache config register
|
ignore. Set the relevant field in the data cache config register
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure (not used here) */
|
@param[in] dat The config data structure (not used here) */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dc_nways (union param_val val,
|
dc_nways (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_WAYS))
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_WAYS))
|
{
|
{
|
int way_bits = log2_int (val.int_val);
|
int way_bits = log2_int (val.int_val);
|
|
|
config.dc.nways = val.int_val;
|
config.dc.nways = val.int_val;
|
|
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCW;
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCW;
|
cpu_state.sprs[SPR_DCCFGR] |= way_bits << SPR_DCCFGR_NCW_OFF;
|
cpu_state.sprs[SPR_DCCFGR] |= way_bits << SPR_DCCFGR_NCW_OFF;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning: data cache nways not a power of 2 <= %d: "
|
fprintf (stderr, "Warning: data cache nways not a power of 2 <= %d: "
|
"ignored\n", MAX_DC_WAYS);
|
"ignored\n", MAX_DC_WAYS);
|
}
|
}
|
} /* dc_nways() */
|
} /* dc_nways() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the data cache block size
|
/*!Set the data cache block size
|
|
|
Value must be either MIN_DC_BLOCK_SIZE or MAX_DC_BLOCK_SIZE. If not issue a
|
Value must be either MIN_DC_BLOCK_SIZE or MAX_DC_BLOCK_SIZE. If not issue a
|
warning and ignore. Set the relevant field in the data cache config register
|
warning and ignore. Set the relevant field in the data cache config register
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure (not used here) */
|
@param[in] dat The config data structure (not used here) */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dc_blocksize (union param_val val,
|
dc_blocksize (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
switch (val.int_val)
|
switch (val.int_val)
|
{
|
{
|
case MIN_DC_BLOCK_SIZE:
|
case MIN_DC_BLOCK_SIZE:
|
config.dc.blocksize = val.int_val;
|
config.dc.blocksize = val.int_val;
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_CBS;
|
cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_CBS;
|
break;
|
break;
|
|
|
case MAX_DC_BLOCK_SIZE:
|
case MAX_DC_BLOCK_SIZE:
|
config.dc.blocksize = val.int_val;
|
config.dc.blocksize = val.int_val;
|
cpu_state.sprs[SPR_DCCFGR] |= SPR_DCCFGR_CBS;
|
cpu_state.sprs[SPR_DCCFGR] |= SPR_DCCFGR_CBS;
|
break;
|
break;
|
|
|
default:
|
default:
|
fprintf (stderr, "Warning: data cache block size not %d or %d: "
|
fprintf (stderr, "Warning: data cache block size not %d or %d: "
|
"ignored\n", MIN_DC_BLOCK_SIZE, MAX_DC_BLOCK_SIZE);
|
"ignored\n", MIN_DC_BLOCK_SIZE, MAX_DC_BLOCK_SIZE);
|
break;
|
break;
|
}
|
}
|
} /* dc_blocksize() */
|
} /* dc_blocksize() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of data cache usage states
|
/*!Set the number of data cache usage states
|
|
|
Value must be 2, 3 or 4. If not issue a warning and ignore.
|
Value must be 2, 3 or 4. If not issue a warning and ignore.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure (not used here) */
|
@param[in] dat The config data structure (not used here) */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dc_ustates (union param_val val,
|
dc_ustates (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
if ((val.int_val >= 2) && (val.int_val <= 4))
|
if ((val.int_val >= 2) && (val.int_val <= 4))
|
{
|
{
|
config.dc.ustates = val.int_val;
|
config.dc.ustates = val.int_val;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning number of data cache usage states must be "
|
fprintf (stderr, "Warning number of data cache usage states must be "
|
"2, 3 or 4: ignored\n");
|
"2, 3 or 4: ignored\n");
|
}
|
}
|
} /* dc_ustates() */
|
} /* dc_ustates() */
|
|
|
|
|
static void
|
static void
|
dc_load_hitdelay (union param_val val, void *dat)
|
dc_load_hitdelay (union param_val val, void *dat)
|
{
|
{
|
config.dc.load_hitdelay = val.int_val;
|
config.dc.load_hitdelay = val.int_val;
|
}
|
}
|
|
|
static void
|
static void
|
dc_load_missdelay (union param_val val, void *dat)
|
dc_load_missdelay (union param_val val, void *dat)
|
{
|
{
|
config.dc.load_missdelay = val.int_val;
|
config.dc.load_missdelay = val.int_val;
|
}
|
}
|
|
|
static void
|
static void
|
dc_store_hitdelay (union param_val val, void *dat)
|
dc_store_hitdelay (union param_val val, void *dat)
|
{
|
{
|
config.dc.store_hitdelay = val.int_val;
|
config.dc.store_hitdelay = val.int_val;
|
}
|
}
|
|
|
static void
|
static void
|
dc_store_missdelay (union param_val val, void *dat)
|
dc_store_missdelay (union param_val val, void *dat)
|
{
|
{
|
config.dc.store_missdelay = val.int_val;
|
config.dc.store_missdelay = val.int_val;
|
}
|
}
|
|
|
void
|
void
|
reg_dc_sec (void)
|
reg_dc_sec (void)
|
{
|
{
|
struct config_section *sec = reg_config_sec ("dc", NULL, NULL);
|
struct config_section *sec = reg_config_sec ("dc", NULL, NULL);
|
|
|
reg_config_param (sec, "enabled", paramt_int, dc_enabled);
|
reg_config_param (sec, "enabled", PARAMT_INT, dc_enabled);
|
reg_config_param (sec, "nsets", paramt_int, dc_nsets);
|
reg_config_param (sec, "nsets", PARAMT_INT, dc_nsets);
|
reg_config_param (sec, "nways", paramt_int, dc_nways);
|
reg_config_param (sec, "nways", PARAMT_INT, dc_nways);
|
reg_config_param (sec, "blocksize", paramt_int, dc_blocksize);
|
reg_config_param (sec, "blocksize", PARAMT_INT, dc_blocksize);
|
reg_config_param (sec, "ustates", paramt_int, dc_ustates);
|
reg_config_param (sec, "ustates", PARAMT_INT, dc_ustates);
|
reg_config_param (sec, "load_hitdelay", paramt_int, dc_load_hitdelay);
|
reg_config_param (sec, "load_hitdelay", PARAMT_INT, dc_load_hitdelay);
|
reg_config_param (sec, "load_missdelay", paramt_int, dc_load_missdelay);
|
reg_config_param (sec, "load_missdelay", PARAMT_INT, dc_load_missdelay);
|
reg_config_param (sec, "store_hitdelay", paramt_int, dc_store_hitdelay);
|
reg_config_param (sec, "store_hitdelay", PARAMT_INT, dc_store_hitdelay);
|
reg_config_param (sec, "store_missdelay", paramt_int, dc_store_missdelay);
|
reg_config_param (sec, "store_missdelay", PARAMT_INT, dc_store_missdelay);
|
}
|
}
|
|
|
