/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// or1200_fpu_intfloat_conv ////
|
//// or1200_fpu_intfloat_conv ////
|
//// Only conversion between 32-bit integer and single ////
|
//// Only conversion between 32-bit integer and single ////
|
//// precision floating point format ////
|
//// precision floating point format ////
|
//// ////
|
//// ////
|
//// Author: Rudolf Usselmann ////
|
//// Author: Rudolf Usselmann ////
|
//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// Modified by Julius Baxter, July, 2010 ////
|
//// Modified by Julius Baxter, July, 2010 ////
|
//// julius.baxter@orsoc.se ////
|
//// julius.baxter@orsoc.se ////
|
//// ////
|
//// ////
|
//// TODO: Fix bug where 1.0f in round up goes to integer 2 ////
|
//// TODO: Fix bug where 1.0f in round up goes to integer 2 ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Rudolf Usselmann ////
|
//// Copyright (C) 2000 Rudolf Usselmann ////
|
//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
`timescale 1ns / 100ps
|
`timescale 1ns / 100ps
|
|
|
/*
|
/*
|
|
|
FPU Operations (fpu_op):
|
FPU Operations (fpu_op):
|
========================
|
========================
|
|
|
0 =
|
0 =
|
1 =
|
1 =
|
2 =
|
2 =
|
3 =
|
3 =
|
4 = int to float
|
4 = int to float
|
5 = float to int
|
5 = float to int
|
6 =
|
6 =
|
7 =
|
7 =
|
|
|
Rounding Modes (rmode):
|
Rounding Modes (rmode):
|
=======================
|
=======================
|
|
|
0 = round_nearest_even
|
0 = round_nearest_even
|
1 = round_to_zero
|
1 = round_to_zero
|
2 = round_up
|
2 = round_up
|
3 = round_down
|
3 = round_down
|
|
|
*/
|
*/
|
|
|
|
|
module or1200_fpu_intfloat_conv
|
module or1200_fpu_intfloat_conv
|
(
|
(
|
clk, rmode, fpu_op, opa, out, snan, ine, inv,
|
clk, rmode, fpu_op, opa, out, snan, ine, inv,
|
overflow, underflow, zero
|
overflow, underflow, zero
|
);
|
);
|
input clk;
|
input clk;
|
input [1:0] rmode;
|
input [1:0] rmode;
|
input [2:0] fpu_op;
|
input [2:0] fpu_op;
|
input [31:0] opa;
|
input [31:0] opa;
|
output [31:0] out;
|
output [31:0] out;
|
output snan;
|
output snan;
|
output ine;
|
output ine;
|
output inv;
|
output inv;
|
output overflow;
|
output overflow;
|
output underflow;
|
output underflow;
|
output zero;
|
output zero;
|
|
|
|
|
parameter INF = 31'h7f800000,
|
parameter INF = 31'h7f800000,
|
QNAN = 31'h7fc00001,
|
QNAN = 31'h7fc00001,
|
SNAN = 31'h7f800001;
|
SNAN = 31'h7f800001;
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Local Wires
|
// Local Wires
|
//
|
//
|
reg zero;
|
reg zero;
|
reg [31:0] opa_r; // Input operand registers
|
reg [31:0] opa_r; // Input operand registers
|
reg [31:0] out; // Output register
|
reg [31:0] out; // Output register
|
reg div_by_zero; // Divide by zero output register
|
reg div_by_zero; // Divide by zero output register
|
wire [7:0] exp_fasu; // Exponent output from EQU block
|
wire [7:0] exp_fasu; // Exponent output from EQU block
|
reg [7:0] exp_r; // Exponent output (registerd)
|
reg [7:0] exp_r; // Exponent output (registerd)
|
wire co; // carry output
|
wire co; // carry output
|
wire [30:0] out_d; // Intermediate final result output
|
wire [30:0] out_d; // Intermediate final result output
|
wire overflow_d, underflow_d;// Overflow/Underflow
|
wire overflow_d, underflow_d;// Overflow/Underflow
|
reg inf, snan, qnan;// Output Registers for INF, S/QNAN
|
reg inf, snan, qnan;// Output Registers for INF, S/QNAN
|
reg ine; // Output Registers for INE
|
reg ine; // Output Registers for INE
|
reg [1:0] rmode_r1, rmode_r2,// Pipeline registers for round mode
|
reg [1:0] rmode_r1, rmode_r2,// Pipeline registers for round mode
|
rmode_r3;
|
rmode_r3;
|
reg [2:0] fpu_op_r1, fpu_op_r2,// Pipeline registers for fp
|
reg [2:0] fpu_op_r1, fpu_op_r2,// Pipeline registers for fp
|
// operation
|
// operation
|
fpu_op_r3;
|
fpu_op_r3;
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Input Registers
|
// Input Registers
|
//
|
//
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
opa_r <= opa;
|
opa_r <= opa;
|
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
rmode_r1 <= rmode;
|
rmode_r1 <= rmode;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
rmode_r2 <= rmode_r1;
|
rmode_r2 <= rmode_r1;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
rmode_r3 <= rmode_r2;
|
rmode_r3 <= rmode_r2;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
fpu_op_r1 <= fpu_op;
|
fpu_op_r1 <= fpu_op;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
fpu_op_r2 <= fpu_op_r1;
|
fpu_op_r2 <= fpu_op_r1;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
fpu_op_r3 <= fpu_op_r2;
|
fpu_op_r3 <= fpu_op_r2;
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Exceptions block
|
// Exceptions block
|
//
|
//
|
wire inf_d, ind_d, qnan_d, snan_d, opa_nan;
|
wire inf_d, ind_d, qnan_d, snan_d, opa_nan;
|
wire opa_00;
|
wire opa_00;
|
wire opa_inf;
|
wire opa_inf;
|
wire opa_dn;
|
wire opa_dn;
|
|
|
or1200_fpu_intfloat_conv_except u0
|
or1200_fpu_intfloat_conv_except u0
|
( .clk(clk),
|
( .clk(clk),
|
.opa(opa_r),
|
.opa(opa_r),
|
.opb(),
|
.opb(),
|
.inf(inf_d),
|
.inf(inf_d),
|
.ind(ind_d),
|
.ind(ind_d),
|
.qnan(qnan_d),
|
.qnan(qnan_d),
|
.snan(snan_d),
|
.snan(snan_d),
|
.opa_nan(opa_nan),
|
.opa_nan(opa_nan),
|
.opb_nan(),
|
.opb_nan(),
|
.opa_00(opa_00),
|
.opa_00(opa_00),
|
.opb_00(),
|
.opb_00(),
|
.opa_inf(opa_inf),
|
.opa_inf(opa_inf),
|
.opb_inf(),
|
.opb_inf(),
|
.opa_dn(opa_dn),
|
.opa_dn(opa_dn),
|
.opb_dn()
|
.opb_dn()
|
);
|
);
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Pre-Normalize block
|
// Pre-Normalize block
|
// - Adjusts the numbers to equal exponents and sorts them
|
// - Adjusts the numbers to equal exponents and sorts them
|
// - determine result sign
|
// - determine result sign
|
// - determine actual operation to perform (add or sub)
|
// - determine actual operation to perform (add or sub)
|
//
|
//
|
|
|
wire nan_sign_d, result_zero_sign_d;
|
wire nan_sign_d, result_zero_sign_d;
|
reg sign_fasu_r;
|
reg sign_fasu_r;
|
wire [1:0] exp_ovf;
|
wire [1:0] exp_ovf;
|
reg [1:0] exp_ovf_r;
|
reg [1:0] exp_ovf_r;
|
|
|
// This is all we need from post-norm module for int-float conversion
|
// This is all we need from post-norm module for int-float conversion
|
reg opa_sign_r;
|
reg opa_sign_r;
|
always @(posedge clk)
|
always @(posedge clk)
|
opa_sign_r <= opa_r[31];
|
opa_sign_r <= opa_r[31];
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
sign_fasu_r <= opa_sign_r; //sign_fasu;
|
sign_fasu_r <= opa_sign_r; //sign_fasu;
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Normalize Result
|
// Normalize Result
|
//
|
//
|
wire ine_d;
|
wire ine_d;
|
wire inv_d;
|
wire inv_d;
|
wire sign_d;
|
wire sign_d;
|
reg sign;
|
reg sign;
|
reg [30:0] opa_r1;
|
reg [30:0] opa_r1;
|
reg [47:0] fract_i2f;
|
reg [47:0] fract_i2f;
|
reg opas_r1, opas_r2;
|
reg opas_r1, opas_r2;
|
wire f2i_out_sign;
|
wire f2i_out_sign;
|
wire [47:0] fract_denorm;
|
wire [47:0] fract_denorm;
|
|
|
always @(posedge clk) // Exponent must be once cycle delayed
|
always @(posedge clk) // Exponent must be once cycle delayed
|
case(fpu_op_r2)
|
case(fpu_op_r2)
|
//4: exp_r <= 0;
|
//4: exp_r <= 0;
|
5: exp_r <= opa_r1[30:23];
|
5: exp_r <= opa_r1[30:23];
|
default: exp_r <= 0;
|
default: exp_r <= 0;
|
endcase
|
endcase
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
opa_r1 <= opa_r[30:0];
|
opa_r1 <= opa_r[30:0];
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
fract_i2f <= (fpu_op_r2==5) ?
|
fract_i2f <= (fpu_op_r2==5) ?
|
(sign_d ? 1-{24'h00, (|opa_r1[30:23]), opa_r1[22:0]}-1 :
|
(sign_d ? 1-{24'h00, (|opa_r1[30:23]), opa_r1[22:0]}-1 :
|
{24'h0, (|opa_r1[30:23]), opa_r1[22:0]})
|
{24'h0, (|opa_r1[30:23]), opa_r1[22:0]})
|
: (sign_d ? 1 - {opa_r1, 17'h01} : {opa_r1, 17'h0});
|
: (sign_d ? 1 - {opa_r1, 17'h01} : {opa_r1, 17'h0});
|
|
|
assign fract_denorm = fract_i2f;
|
assign fract_denorm = fract_i2f;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
opas_r1 <= opa_r[31];
|
opas_r1 <= opa_r[31];
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
opas_r2 <= opas_r1;
|
opas_r2 <= opas_r1;
|
|
|
assign sign_d = opa_sign_r; //sign_fasu;
|
assign sign_d = opa_sign_r; //sign_fasu;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
sign <= (rmode_r2==2'h3) ? !sign_d : sign_d;
|
sign <= (rmode_r2==2'h3) ? !sign_d : sign_d;
|
|
|
|
|
// Special case of largest negative integer we can convert to - usually
|
// Special case of largest negative integer we can convert to - usually
|
// gets picked up as invalid, but really it's not, so deal with it as a
|
// gets picked up as invalid, but really it's not, so deal with it as a
|
// special case.
|
// special case.
|
wire f2i_special_case_no_inv;
|
wire f2i_special_case_no_inv;
|
assign f2i_special_case_no_inv = (opa == 32'hcf000000);
|
assign f2i_special_case_no_inv = (opa == 32'hcf000000);
|
|
|
|
|
or1200_fpu_post_norm_intfloat_conv u4
|
or1200_fpu_post_norm_intfloat_conv u4
|
(
|
(
|
.clk(clk), // System Clock
|
.clk(clk), // System Clock
|
.fpu_op(fpu_op_r3), // Floating Point Operation
|
.fpu_op(fpu_op_r3), // Floating Point Operation
|
.opas(opas_r2), // OPA Sign
|
.opas(opas_r2), // OPA Sign
|
.sign(sign), // Sign of the result
|
.sign(sign), // Sign of the result
|
.rmode(rmode_r3), // Rounding mode
|
.rmode(rmode_r3), // Rounding mode
|
.fract_in(fract_denorm), // Fraction Input
|
.fract_in(fract_denorm), // Fraction Input
|
|
|
.exp_in(exp_r), // Exponent Input
|
.exp_in(exp_r), // Exponent Input
|
.opa_dn(opa_dn), // Operand A Denormalized
|
.opa_dn(opa_dn), // Operand A Denormalized
|
.opa_nan(opa_nan),
|
.opa_nan(opa_nan),
|
.opa_inf(opa_inf),
|
.opa_inf(opa_inf),
|
|
|
.opb_dn(), // Operand B Denormalized
|
.opb_dn(), // Operand B Denormalized
|
.out(out_d), // Normalized output (un-registered)
|
.out(out_d), // Normalized output (un-registered)
|
.ine(ine_d), // Result Inexact output (un-registered)
|
.ine(ine_d), // Result Inexact output (un-registered)
|
.inv(inv_d), // Invalid input for f2i operation
|
.inv(inv_d), // Invalid input for f2i operation
|
.overflow(overflow_d), // Overflow output (un-registered)
|
.overflow(overflow_d), // Overflow output (un-registered)
|
.underflow(underflow_d),// Underflow output (un-registered)
|
.underflow(underflow_d),// Underflow output (un-registered)
|
.f2i_out_sign(f2i_out_sign) // F2I Output Sign
|
.f2i_out_sign(f2i_out_sign) // F2I Output Sign
|
);
|
);
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// FPU Outputs
|
// FPU Outputs
|
//
|
//
|
reg fasu_op_r1, fasu_op_r2;
|
reg fasu_op_r1, fasu_op_r2;
|
wire [30:0] out_fixed;
|
wire [30:0] out_fixed;
|
wire output_zero_fasu;
|
wire output_zero_fasu;
|
wire overflow_fasu;
|
wire overflow_fasu;
|
wire out_d_00;
|
wire out_d_00;
|
wire ine_fasu;
|
wire ine_fasu;
|
wire underflow_fasu;
|
wire underflow_fasu;
|
|
|
|
|
/*
|
/*
|
always @(posedge clk)
|
always @(posedge clk)
|
fasu_op_r1 <= fasu_op;
|
fasu_op_r1 <= fasu_op;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
fasu_op_r2 <= fasu_op_r1;
|
fasu_op_r2 <= fasu_op_r1;
|
*/
|
*/
|
// Force pre-set values for non numerical output
|
// Force pre-set values for non numerical output
|
|
|
assign out_fixed = ( (qnan_d | snan_d) |
|
assign out_fixed = ( (qnan_d | snan_d) |
|
(ind_d /*& !fasu_op_r2*/)) ? QNAN : INF;
|
(ind_d /*& !fasu_op_r2*/)) ? QNAN : INF;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
out[30:0] <= /*((inf_d & (fpu_op_r3!=3'b101)) | snan_d | qnan_d)
|
out[30:0] <= /*((inf_d & (fpu_op_r3!=3'b101)) | snan_d | qnan_d)
|
& fpu_op_r3!=3'b100 ? out_fixed :*/ out_d;
|
& fpu_op_r3!=3'b100 ? out_fixed :*/ out_d;
|
|
|
assign out_d_00 = !(|out_d);
|
assign out_d_00 = !(|out_d);
|
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
out[31] <= (fpu_op_r3==3'b101) ?
|
out[31] <= (fpu_op_r3==3'b101) ?
|
f2i_out_sign : sign_fasu_r;
|
f2i_out_sign : sign_fasu_r;
|
|
|
|
|
|
|
// Exception Outputs
|
// Exception Outputs
|
assign ine_fasu = (ine_d | overflow_d | underflow_d) &
|
assign ine_fasu = (ine_d | overflow_d | underflow_d) &
|
!(snan_d | qnan_d | inf_d);
|
!(snan_d | qnan_d | inf_d);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
ine <= fpu_op_r3[2] ? ine_d : ine_fasu;
|
ine <= fpu_op_r3[2] ? ine_d : ine_fasu;
|
|
|
assign overflow = overflow_d & !(snan_d | qnan_d | inf_d);
|
assign overflow = overflow_d & !(snan_d | qnan_d | inf_d);
|
assign underflow = underflow_d & !(inf_d | snan_d | qnan_d);
|
assign underflow = underflow_d & !(inf_d | snan_d | qnan_d);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
snan <= snan_d & (fpu_op_r3==3'b101); // Only signal sNaN when ftoi
|
snan <= snan_d & (fpu_op_r3==3'b101); // Only signal sNaN when ftoi
|
|
|
// Status Outputs
|
// Status Outputs
|
assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d);
|
assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
zero <= fpu_op_r3==3'b101 ? out_d_00 & !(snan_d | qnan_d) :
|
zero <= fpu_op_r3==3'b101 ? out_d_00 & !(snan_d | qnan_d) :
|
output_zero_fasu ;
|
output_zero_fasu ;
|
assign inv = inv_d & !f2i_special_case_no_inv;
|
assign inv = inv_d & !f2i_special_case_no_inv;
|
|
|
endmodule // or1200_fpu_intfloat_conv
|
endmodule // or1200_fpu_intfloat_conv
|
|
|
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module or1200_fpu_intfloat_conv_except
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(
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clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
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opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn
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);
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input clk;
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input [31:0] opa, opb;
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output inf, ind, qnan, snan, opa_nan, opb_nan;
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output opa_00, opb_00;
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output opa_inf, opb_inf;
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output opa_dn;
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output opb_dn;
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////////////////////////////////////////////////////////////////////////
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//
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// Local Wires and registers
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//
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wire [7:0] expa, expb; // alias to opX exponent
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wire [22:0] fracta, fractb; // alias to opX fraction
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reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
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reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
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reg inf, ind, qnan, snan; // Output registers
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reg opa_nan, opb_nan;
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reg expa_00, expb_00, fracta_00, fractb_00;
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reg opa_00, opb_00;
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reg opa_inf, opb_inf;
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reg opa_dn, opb_dn;
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////////////////////////////////////////////////////////////////////////
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//
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// Aliases
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//
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assign expa = opa[30:23];
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assign expb = opb[30:23];
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assign fracta = opa[22:0];
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assign fractb = opb[22:0];
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////////////////////////////////////////////////////////////////////////
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//
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// Determine if any of the input operators is a INF or NAN or any other
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// special number
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//
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always @(posedge clk)
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expa_ff <= &expa;
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always @(posedge clk)
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expb_ff <= &expb;
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always @(posedge clk)
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infa_f_r <= !(|fracta);
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always @(posedge clk)
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infb_f_r <= !(|fractb);
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always @(posedge clk)
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qnan_r_a <= fracta[22];
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always @(posedge clk)
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snan_r_a <= !fracta[22] & |fracta[21:0];
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always @(posedge clk)
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qnan_r_b <= fractb[22];
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always @(posedge clk)
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snan_r_b <= !fractb[22]; // & |fractb[21:0];
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always @(posedge clk)
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ind <= (expa_ff & infa_f_r); // & (expb_ff & infb_f_r);
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always @(posedge clk)
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inf <= (expa_ff & infa_f_r); // | (expb_ff & infb_f_r);
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always @(posedge clk)
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qnan <= (expa_ff & qnan_r_a); // | (expb_ff & qnan_r_b);
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always @(posedge clk)
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snan <= (expa_ff & snan_r_a); // | (expb_ff & snan_r_b);
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always @(posedge clk)
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opa_nan <= &expa & (|fracta[22:0]);
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always @(posedge clk)
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opb_nan <= &expb & (|fractb[22:0]);
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always @(posedge clk)
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opa_inf <= (expa_ff & infa_f_r);
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always @(posedge clk)
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opb_inf <= (expb_ff & infb_f_r);
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always @(posedge clk)
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expa_00 <= !(|expa);
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always @(posedge clk)
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expb_00 <= !(|expb);
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always @(posedge clk)
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fracta_00 <= !(|fracta);
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always @(posedge clk)
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fractb_00 <= !(|fractb);
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always @(posedge clk)
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opa_00 <= expa_00 & fracta_00;
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always @(posedge clk)
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opb_00 <= expb_00 & fractb_00;
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always @(posedge clk)
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opa_dn <= expa_00;
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always @(posedge clk)
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opb_dn <= expb_00;
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endmodule // or1200_fpu_intfloat_conv_except
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