/*
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/*
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Copyright 2011, City University of Hong Kong
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Copyright 2011, City University of Hong Kong
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Author is Homer (Dongsheng) Xing.
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Author is Homer (Dongsheng) Xing.
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This file is part of Tate Bilinear Pairing Core.
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This file is part of Tate Bilinear Pairing Core.
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Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
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Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
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Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see http://www.gnu.org/licenses/lgpl.txt
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along with Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
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*/
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*/
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`include "inc.v"
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`include "inc.v"
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// out = (v1 & l1) | (v2 & l2)
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// out = (v1 & l1) | (v2 & l2)
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module f33m_mux2(v1, l1, v2, l2, out);
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module f33m_mux2(v1, l1, v2, l2, out);
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input [`W3:0] v1, v2;
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input [`W3:0] v1, v2;
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input l1, l2;
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input l1, l2;
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output [`W3:0] out;
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output [`W3:0] out;
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genvar i;
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genvar i;
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generate
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generate
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for(i=0;i<=`W3;i=i+1)
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for(i=0;i<=`W3;i=i+1)
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begin : label
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begin : label
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assign out[i] = (v1[i] & l1) | (v2[i] & l2);
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assign out[i] = (v1[i] & l1) | (v2[i] & l2);
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
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// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
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module f33m_mux3(v1, l1, v2, l2, v3, l3, out);
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module f33m_mux3(v1, l1, v2, l2, v3, l3, out);
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input [`W3:0] v1, v2, v3;
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input [`W3:0] v1, v2, v3;
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input l1, l2, l3;
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input l1, l2, l3;
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output [`W3:0] out;
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output [`W3:0] out;
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genvar i;
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genvar i;
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generate
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generate
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for(i=0;i<=`W3;i=i+1)
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for(i=0;i<=`W3;i=i+1)
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begin : label
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begin : label
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assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
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assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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// c == a+b in GF(3^{3*M})
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// c == a+b in GF(3^{3*M})
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module f33m_add(a, b, c);
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module f33m_add(a, b, c);
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input [`W3:0] a,b;
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input [`W3:0] a,b;
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output [`W3:0] c;
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output [`W3:0] c;
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wire [`WIDTH:0] a0,a1,a2,b0,b1,b2,c0,c1,c2;
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wire [`WIDTH:0] a0,a1,a2,b0,b1,b2,c0,c1,c2;
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assign {a2,a1,a0} = a;
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assign {a2,a1,a0} = a;
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assign {b2,b1,b0} = b;
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assign {b2,b1,b0} = b;
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assign c = {c2,c1,c0};
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assign c = {c2,c1,c0};
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f3m_add
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f3m_add
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ins1 (a0,b0,c0),
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ins1 (a0,b0,c0),
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ins2 (a1,b1,c1),
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ins2 (a1,b1,c1),
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ins3 (a2,b2,c2);
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ins3 (a2,b2,c2);
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endmodule
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endmodule
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// c == -a in GF(3^{3*M})
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// c == -a in GF(3^{3*M})
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module f33m_neg(a, c);
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module f33m_neg(a, c);
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input [`W3:0] a;
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input [`W3:0] a;
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output [`W3:0] c;
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output [`W3:0] c;
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wire [`WIDTH:0] a0,a1,a2,c0,c1,c2;
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wire [`WIDTH:0] a0,a1,a2,c0,c1,c2;
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assign {a2,a1,a0} = a;
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assign {a2,a1,a0} = a;
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assign c = {c2,c1,c0};
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assign c = {c2,c1,c0};
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f3m_neg
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f3m_neg
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ins1 (a0,c0),
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ins1 (a0,c0),
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ins2 (a1,c1),
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ins2 (a1,c1),
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ins3 (a2,c2);
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ins3 (a2,c2);
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endmodule
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endmodule
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// c == a*b in GF(3^{3*M})
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// c == a*b in GF(3^{3*M})
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module f33m_mult(clk, reset, a, b, c, done);
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module f33m_mult(clk, reset, a, b, c, done);
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input clk, reset;
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input clk, reset;
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input [`W3:0] a, b;
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input [`W3:0] a, b;
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output reg [`W3:0] c;
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output reg [`W3:0] c;
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output reg done;
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output reg done;
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reg [`WIDTH:0] x0, x1, x2, x3, x4, x5;
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reg [`WIDTH:0] x0, x1, x2, x3, x4, x5;
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wire [`WIDTH:0] a0, a1, a2,
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wire [`WIDTH:0] a0, a1, a2,
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b0, b1, b2,
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b0, b1, b2,
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c0, c1, c2,
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c0, c1, c2,
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v1, v2, v3, v4, v5, v6,
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v1, v2, v3, v4, v5, v6,
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nx0, nx2, nx5,
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nx0, nx2, nx5,
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d0, d1, d2, d3, d4;
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d0, d1, d2, d3, d4;
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reg [6:0] K;
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reg [6:0] K;
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wire e0, e1, e2,
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wire e0, e1, e2,
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e3, e4, e5,
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e3, e4, e5,
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mult_done, p, rst;
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mult_done, p, rst;
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wire [`WIDTH:0] in0, in1;
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wire [`WIDTH:0] in0, in1;
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wire [`WIDTH:0] o;
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wire [`WIDTH:0] o;
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reg mult_reset, delay1, delay2;
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reg mult_reset, delay1, delay2;
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assign {e0,e1,e2,e3,e4,e5} = K[6:1];
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assign {e0,e1,e2,e3,e4,e5} = K[6:1];
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assign {a2,a1,a0} = a;
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assign {a2,a1,a0} = a;
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assign {b2,b1,b0} = b;
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assign {b2,b1,b0} = b;
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assign d4 = x0;
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assign d4 = x0;
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assign d0 = x5;
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assign d0 = x5;
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assign rst = delay2;
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assign rst = delay2;
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f3m_mux6
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f3m_mux6
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ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
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ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
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ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
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ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
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f3m_mult
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f3m_mult
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ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
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ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
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func6
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func6
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ins4 (clk, reset, mult_done, p);
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ins4 (clk, reset, mult_done, p);
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f3m_add
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f3m_add
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ins5 (a1, a2, v1), // v1 == a1+a2
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ins5 (a1, a2, v1), // v1 == a1+a2
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ins6 (b1, b2, v2), // v2 == b1+b2
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ins6 (b1, b2, v2), // v2 == b1+b2
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ins7 (a0, a2, v3), // v3 == a0+a2
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ins7 (a0, a2, v3), // v3 == a0+a2
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ins8 (b0, b2, v4), // v4 == b0+b2
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ins8 (b0, b2, v4), // v4 == b0+b2
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ins9 (a0, a1, v5), // v5 == a0+a1
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ins9 (a0, a1, v5), // v5 == a0+a1
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ins10 (b0, b1, v6), // v6 == b0+b1
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ins10 (b0, b1, v6), // v6 == b0+b1
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ins11 (d0, d3, c0), // c0 == d0+d3
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ins11 (d0, d3, c0), // c0 == d0+d3
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ins12 (d2, d4, c2); // c2 == d2+d4
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ins12 (d2, d4, c2); // c2 == d2+d4
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f3m_neg
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f3m_neg
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ins13 (x0, nx0), // nx0 == -x0
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ins13 (x0, nx0), // nx0 == -x0
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ins14 (x2, nx2), // nx2 == -x2
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ins14 (x2, nx2), // nx2 == -x2
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ins15 (x5, nx5); // nx5 == -x5
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ins15 (x5, nx5); // nx5 == -x5
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f3m_add3
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f3m_add3
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ins16 (x1, nx0, nx2, d3), // d3 == x1-x0-x2
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ins16 (x1, nx0, nx2, d3), // d3 == x1-x0-x2
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ins17 (x4, nx2, nx5, d1), // d1 == x4-x2-x5
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ins17 (x4, nx2, nx5, d1), // d1 == x4-x2-x5
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ins18 (d1, d3, d4, c1); // c1 == d1+d3+d4
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ins18 (d1, d3, d4, c1); // c1 == d1+d3+d4
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f3m_add4
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f3m_add4
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ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
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ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (reset) K <= 7'b1000000;
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if (reset) K <= 7'b1000000;
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else if (p|K[0]) K <= {1'b0,K[6:1]};
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else if (p|K[0]) K <= {1'b0,K[6:1]};
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (e0) x0 <= o; // x0 == a2*b2
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if (e0) x0 <= o; // x0 == a2*b2
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if (e1) x1 <= o; // x1 == (a2+a1)*(b2+b1)
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if (e1) x1 <= o; // x1 == (a2+a1)*(b2+b1)
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if (e2) x2 <= o; // x2 == a1*b1
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if (e2) x2 <= o; // x2 == a1*b1
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if (e3) x3 <= o; // x3 == (a2+a0)*(b2+b0)
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if (e3) x3 <= o; // x3 == (a2+a0)*(b2+b0)
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if (e4) x4 <= o; // x4 == (a1+a0)*(b1+b0)
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if (e4) x4 <= o; // x4 == (a1+a0)*(b1+b0)
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if (e5) x5 <= o; // x5 == a0*b0
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if (e5) x5 <= o; // x5 == a0*b0
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (reset) done <= 0;
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if (reset) done <= 0;
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else if (K[0])
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else if (K[0])
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begin
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begin
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done <= 1; c <= {c2,c1,c0};
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done <= 1; c <= {c2,c1,c0};
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end
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end
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rst) mult_reset <= 1;
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if (rst) mult_reset <= 1;
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else if (mult_done) mult_reset <= 1;
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else if (mult_done) mult_reset <= 1;
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else mult_reset <= 0;
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else mult_reset <= 0;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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delay2 <= delay1; delay1 <= reset;
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delay2 <= delay1; delay1 <= reset;
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end
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end
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endmodule
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endmodule
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// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^{3*M})
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// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^{3*M})
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module f33m_mult3(clk, reset,
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module f33m_mult3(clk, reset,
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a0, b0, c0,
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a0, b0, c0,
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a1, b1, c1,
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a1, b1, c1,
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a2, b2, c2,
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a2, b2, c2,
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done);
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done);
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input clk, reset;
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input clk, reset;
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input [`W3:0] a0, b0, a1, b1, a2, b2;
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input [`W3:0] a0, b0, a1, b1, a2, b2;
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output reg [`W3:0] c0, c1, c2;
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output reg [`W3:0] c0, c1, c2;
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output reg done;
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output reg done;
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reg [3:0] K;
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reg [3:0] K;
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reg mult_reset, delay1, delay2;
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reg mult_reset, delay1, delay2;
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wire e1, e2, e3, mult_done, delay3, rst;
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wire e1, e2, e3, mult_done, delay3, rst;
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wire [`W3:0] in1, in2, o;
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wire [`W3:0] in1, in2, o;
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assign rst = delay2;
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assign rst = delay2;
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assign {e1,e2,e3} = K[3:1];
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assign {e1,e2,e3} = K[3:1];
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f33m_mux3
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f33m_mux3
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ins9 (a0, e1, a1, e2, a2, e3, in1),
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ins9 (a0, e1, a1, e2, a2, e3, in1),
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ins10 (b0, e1, b1, e2, b2, e3, in2);
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ins10 (b0, e1, b1, e2, b2, e3, in2);
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f33m_mult
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f33m_mult
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ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
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ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
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func6
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func6
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ins12 (clk, reset, mult_done, delay3);
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ins12 (clk, reset, mult_done, delay3);
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (e1) c0 <= o;
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if (e1) c0 <= o;
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if (e2) c1 <= o;
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if (e2) c1 <= o;
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if (e3) c2 <= o;
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if (e3) c2 <= o;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) K <= 4'b1000;
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if (reset) K <= 4'b1000;
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else if (delay3|K[0]) K <= {1'b0,K[3:1]};
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else if (delay3|K[0]) K <= {1'b0,K[3:1]};
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rst) mult_reset <= 1;
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if (rst) mult_reset <= 1;
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else if (mult_done) mult_reset <= 1;
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else if (mult_done) mult_reset <= 1;
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else mult_reset <= 0;
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else mult_reset <= 0;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) done <= 0;
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if (reset) done <= 0;
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else if (K[0]) done <= 1;
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else if (K[0]) done <= 1;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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delay2 <= delay1; delay1 <= reset;
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delay2 <= delay1; delay1 <= reset;
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end
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end
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endmodule
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endmodule
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// c0 == a0*b0; c1 == a1*b1; both in GF(3^{3*M})
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// c0 == a0*b0; c1 == a1*b1; both in GF(3^{3*M})
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module f33m_mult2(clk, reset,
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module f33m_mult2(clk, reset,
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a0, b0, c0,
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a0, b0, c0,
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a1, b1, c1,
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a1, b1, c1,
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done);
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done);
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input clk, reset;
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input clk, reset;
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input [`W3:0] a0, b0, a1, b1;
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input [`W3:0] a0, b0, a1, b1;
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output reg [`W3:0] c0, c1;
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output reg [`W3:0] c0, c1;
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output reg done;
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output reg done;
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reg [2:0] K;
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reg [2:0] K;
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reg mult_reset, delay1, delay2;
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reg mult_reset, delay1, delay2;
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wire e1, e2, mult_done, delay3, rst;
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wire e1, e2, mult_done, delay3, rst;
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wire [`W3:0] in1, in2, o;
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wire [`W3:0] in1, in2, o;
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assign rst = delay2;
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assign rst = delay2;
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assign {e1,e2} = K[2:1];
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assign {e1,e2} = K[2:1];
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f33m_mux2
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f33m_mux2
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ins9 (a0, e1, a1, e2, in1),
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ins9 (a0, e1, a1, e2, in1),
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ins10 (b0, e1, b1, e2, in2);
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ins10 (b0, e1, b1, e2, in2);
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f33m_mult
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f33m_mult
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ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
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ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
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func6
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func6
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ins12 (clk, reset, mult_done, delay3);
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ins12 (clk, reset, mult_done, delay3);
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (e1) c0 <= o;
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if (e1) c0 <= o;
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if (e2) c1 <= o;
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if (e2) c1 <= o;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) K <= 3'b100;
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if (reset) K <= 3'b100;
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else if (delay3|K[0]) K <= {1'b0,K[2:1]};
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else if (delay3|K[0]) K <= {1'b0,K[2:1]};
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|
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rst) mult_reset <= 1;
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if (rst) mult_reset <= 1;
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else if (mult_done) mult_reset <= 1;
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else if (mult_done) mult_reset <= 1;
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else mult_reset <= 0;
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else mult_reset <= 0;
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end
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end
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|
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) done <= 0;
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if (reset) done <= 0;
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else if (K[0]) done <= 1;
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else if (K[0]) done <= 1;
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|
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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delay2 <= delay1; delay1 <= reset;
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delay2 <= delay1; delay1 <= reset;
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end
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end
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endmodule
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endmodule
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// c == a^{-1} in GF(3^{3*M})
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// c == a^{-1} in GF(3^{3*M})
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module f33m_inv(clk, reset, a, c, done);
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module f33m_inv(clk, reset, a, c, done);
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input clk, reset;
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input clk, reset;
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input [`W3:0] a;
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input [`W3:0] a;
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output reg [`W3:0] c;
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output reg [`W3:0] c;
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output reg done;
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output reg done;
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wire [`WIDTH:0] a0, a1, a2,
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wire [`WIDTH:0] a0, a1, a2,
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c0, c1, c2,
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c0, c1, c2,
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v0, v1, v2, v3, v4, v5,
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v0, v1, v2, v3, v4, v5,
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v6, v7, v8, v9, v10, v11,
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v6, v7, v8, v9, v10, v11,
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v12, v13, v14, v15, v16,
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v12, v13, v14, v15, v16,
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v17, nv2, nv11, nv14;
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v17, nv2, nv11, nv14;
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wire rst1, rst2, rst3, rst4,
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wire rst1, rst2, rst3, rst4,
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done1, done2, done3, done4,
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done1, done2, done3, done4,
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dummy;
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dummy;
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reg [4:0] K;
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reg [4:0] K;
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assign {a2, a1, a0} = a;
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assign {a2, a1, a0} = a;
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assign rst1 = reset;
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assign rst1 = reset;
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f3m_mult3
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f3m_mult3
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ins1 (clk, rst1,
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ins1 (clk, rst1,
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a0, a0, v0, // v0 == a0^2
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a0, a0, v0, // v0 == a0^2
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a1, a1, v1, // v1 == a1^2
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a1, a1, v1, // v1 == a1^2
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a2, a2, v2, // v2 == a2^2
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a2, a2, v2, // v2 == a2^2
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done1),
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done1),
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ins2 (clk, rst2,
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ins2 (clk, rst2,
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v0, v3, v6, // v6 == (a0-a2)*(a0^2)
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v0, v3, v6, // v6 == (a0-a2)*(a0^2)
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v1, v4, v7, // v7 == (a1-a0)*(a1^2)
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v1, v4, v7, // v7 == (a1-a0)*(a1^2)
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v2, v5, v8, // v8 == (a0-a1+a2)*(a2^2)
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v2, v5, v8, // v8 == (a0-a1+a2)*(a2^2)
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done2),
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done2),
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ins3 (clk, rst1,
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ins3 (clk, rst1,
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a0, a2, v11, // v11 == a0*a2
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a0, a2, v11, // v11 == a0*a2
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a0, a1, v12, // v12 == a0*a1
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a0, a1, v12, // v12 == a0*a1
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a1, a2, v13, // v13 == a1*a2
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a1, a2, v13, // v13 == a1*a2
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dummy),
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dummy),
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ins4 (clk, rst4,
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ins4 (clk, rst4,
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v10, v15, c0,
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v10, v15, c0,
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v10, v16, c1,
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v10, v16, c1,
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v10, v17, c2,
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v10, v17, c2,
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done4);
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done4);
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f3m_sub
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f3m_sub
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ins5 (a0, a2, v3), // v3 == a0-a2
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ins5 (a0, a2, v3), // v3 == a0-a2
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ins6 (a1, a0, v4), // v4 == a1-a0
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ins6 (a1, a0, v4), // v4 == a1-a0
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ins7 (a2, v4, v5); // v5 == a2-v4 == a0-a1+a2
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ins7 (a2, v4, v5); // v5 == a2-v4 == a0-a1+a2
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f3m_add3
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f3m_add3
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ins8 (v6, v7, v8, v9), // v9 == v6+v7+v8
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ins8 (v6, v7, v8, v9), // v9 == v6+v7+v8
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ins9 (v11, v1, v13, v14), // v14 == v11+v1+v13
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ins9 (v11, v1, v13, v14), // v14 == v11+v1+v13
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ins10 (nv14, v0, v2, v15), // v15 == v0+v2-(v11+v1+v13)
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ins10 (nv14, v0, v2, v15), // v15 == v0+v2-(v11+v1+v13)
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ins11 (v1, nv2, nv11, v17); // v17 == a1^2-a0*a2-a2^2
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ins11 (v1, nv2, nv11, v17); // v17 == a1^2-a0*a2-a2^2
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f3m_neg
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f3m_neg
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ins12 (v2, nv2), // nv2 == -v2
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ins12 (v2, nv2), // nv2 == -v2
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ins13 (v11, nv11), // nv11 == -v11
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ins13 (v11, nv11), // nv11 == -v11
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ins14 (v14, nv14); // nv14 == -v14 == -(v11+v1+v13)
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ins14 (v14, nv14); // nv14 == -v14 == -(v11+v1+v13)
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f3m_sub
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f3m_sub
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ins15 (v2, v12, v16); // v16 == a2^2-a0*a1
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ins15 (v2, v12, v16); // v16 == a2^2-a0*a1
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f3m_inv
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f3m_inv
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ins16 (clk, rst3, v9, v10, done3); // v10 == v9^(-1)
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ins16 (clk, rst3, v9, v10, done3); // v10 == v9^(-1)
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func6
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func6
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ins17 (clk, reset, done1, rst2),
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ins17 (clk, reset, done1, rst2),
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ins18 (clk, reset, done2, rst3),
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ins18 (clk, reset, done2, rst3),
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ins19 (clk, reset, done3, rst4);
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ins19 (clk, reset, done3, rst4);
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) K <= 5'h10;
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if (reset) K <= 5'h10;
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else if ((K[4]&rst2)|(K[3]&rst3)|(K[2]&rst4)|(K[1]&done4)|K[0])
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else if ((K[4]&rst2)|(K[3]&rst3)|(K[2]&rst4)|(K[1]&done4)|K[0])
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K <= K >> 1;
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K <= K >> 1;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) done <= 0;
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if (reset) done <= 0;
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else if (K[0])
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else if (K[0])
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begin
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begin
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done <= 1; c <= {c2,c1,c0};
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done <= 1; c <= {c2,c1,c0};
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end
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end
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endmodule
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endmodule
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