/*
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/*
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Copyright 2011, City University of Hong Kong
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Copyright 2011, City University of Hong Kong
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Author is Homer (Dongsheng) Xing.
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Author is Homer (Dongsheng) Xing.
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This file is part of Tate Bilinear Pairing Core.
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This file is part of Tate Bilinear Pairing Core.
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Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
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Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
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Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see http://www.gnu.org/licenses/lgpl.txt
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along with Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
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*/
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*/
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// fun.v: Have you got fun reading the code ?
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// fun.v: Have you got fun reading the code ?
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`include "inc.v"
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`include "inc.v"
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// turn "00000001111111111111111" into "00000001000000000000000"
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// turn "00000001111111111111111" into "00000001000000000000000"
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module func6(clk, reset, in, out);
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module func6(clk, reset, in, out);
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input clk, reset, in;
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input clk, reset, in;
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output out;
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output out;
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reg reg1, reg2;
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reg reg1, reg2;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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begin
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begin
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reg1 <= 0; reg2 <= 0;
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reg1 <= 0; reg2 <= 0;
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end
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end
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else
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else
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begin
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begin
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reg2 <= reg1; reg1 <= in;
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reg2 <= reg1; reg1 <= in;
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end
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end
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assign out = {reg2,reg1}==2'b01 ? 1 : 0;
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assign out = {reg2,reg1}==2'b01 ? 1 : 0;
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endmodule
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endmodule
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